GA10SICP12-247
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Silicon Carbide Junction
Transistor/Schottky Diode Co-pack
Features Package
175 °C maximum operating temperature
Temperature independent switching performance
Gate oxide free SiC switch
Integrated SiC Schottky Rectifier
Positive temperature coefficient for easy paralleling
Low intrinsic device capacitance
Low gate charge
RoHS Compliant
TO-247AB
Advantages Applications
Low switching losses
High circuit efficiency
High temperature operation
High short circuit withstand capability
Reduced cooling requirements
Reduced system size
Down Hole Oil Drilling, Geothermal Instrumentation
Hybrid Electric Vehicles (HEV)
Solar Inverters
Switched-Mode Power Supply (SMPS)
Power Factor Correction (PFC)
Induction Heating
Uninterruptible Power Supply (UPS)
Motor Drives
Maximum Ratings at Tj = 175 °C, unless otherwise specified
Parameter Symbol Conditions Values Unit
SiC Junction Transistor
Drain – Source Voltage VDS VGS = 0 V 1200 V
Continuous Drain Current ID TC,MAX = 95 °C 10 A
Gate Peak Current IGM 10 A
Turn-Off Safe Operating Area RBSOA TVJ = 175 oC, IG = 1 A,
Clamped Inductive Load
ID,max = 10
@ VDS ≤ VDSmax A
Short Circuit Safe Operating Area SCSOA TVJ = 175 oC, IG = 1 A, VDS = 800 V,
Non Repetitive 20 µs
Reverse Gate – Source Voltage VSG 30 V
Reverse Drain – Source Voltage VSD 25 V
Power Dissipation Ptot TC = 95 °C 91 W
Storage Temperature Tstg -55 to 175 °C
Free-wheeling Silicon Carbide diode
DC-Forward Current IF TC ≤ 150 ºC 10 A
Non Repetitive Peak Forward Current IFM TC = 25 ºC, tP = 10 μs 280 A
Surge Non Repetitive Forward Current IF,SM tP = 10 ms, half sine, TC = 25 ºC 65 A
Thermal Characteristics
Thermal resistance, junction - case RthJC SiC Junction Transistor 0.88 °C/W
Thermal resistance, junction - case RthJC SiC Diode 0.85 °C/W
Mechanical Properties
Mounting torque M 0.6 Nm
G D S
D
VDS = 1200 V
VDS(ON) = 1.4 V
ID = 10 A
RDS(ON) = 140 mΩ
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Electrical Characteristics at Tj = 175 °C, unless otherwise specified
Parameter Symbol Conditions Values Unit
min. typ. max.
SJT On-State Characteristics
Drain – Source On Voltage VDS(ON)
ID = 10 A, IG = 200 mA, Tj = 25 °C 1.4
V
ID = 10 A, IG = 400 mA, Tj = 125 °C 1.6
ID = 10 A, IG = 800 mA, Tj = 175 °C 2.2
Drain – Source On Resistance RDS(ON)
ID = 10 A, IG = 200 mA, Tj = 25 °C 140
mΩ
ID = 10 A, IG = 400 mA, Tj = 125 °C 160
ID = 10 A, IG = 800 mA, Tj = 175 °C 220
Gate Forward Voltage VGS(FWD) IG = 500 mA, Tj = 25 °C 3.3 V
IG = 500 mA, Tj = 175 °C 3.1
DC Current Gain β VDS = 5 V, ID = 10 A, Tj = 25 °C
VDS = 5 V, ID = 10 A, Tj = 175 °C
TBD
TBD
SJT Off-State Characteristics
Drain Leakage Current IDSS
VR = 1200 V, VGS = 0 V, Tj = 25 °C
VR = 1200 V, VGS = 0 V, Tj = 125 °C
350
530 nA
VR = 1200 V, VGS = 0 V, Tj = 175 °C 700
Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C 20 nA
SJT Capacitance Characteristics
Gate-Source Capacitance C
g
s VGS = 0 V, f = 1 MHz tbd pF
Input Capacitance Ciss VGS = 0 V, VD = 1 V, f = 1 MHz tbd pF
Reverse Transfer/Output Capacitance Crss/Coss VD = 1 V, f = 1 MHz tbd pF
SJT Switching Characteristics
Turn On Delay Time td
(
on
)
VDD = 800 V, ID = 10 A,
RG(on) = RG(off) = tbd Ω,
FWD = GB10SLT12,
Tj = 25 ºC
Refer to Figure 15 for gate current
waveform
tbd ns
Rise Time tr
tbd ns
Turn Off Delay Time td
(
off
)
tbd ns
Fall Time tf
tbd ns
Turn-On Energy Per Pulse Eon
tbd µJ
Turn-Off Energy Per Pulse Eoff
tbd µJ
Total Switching Energy Ets
tbd µJ
Turn On Delay Time td
(
on
)
VDD = 800 V, ID = 10 A,
RG(on) = RG(off) = tbd Ω,
FWD = GB10SLT12,
Tj = 175 ºC
Refer to Figure 15 for gate current
waveform
tbd
Rise Time tr
tbd ns
Turn Off Delay Time td
(
off
)
tbd ns
Fall Time tf
tbd ns
Turn-On Energy Per Pulse Eon
tbd µJ
Turn-Off Energy Per Pulse Eoff
tbd µJ
Total Switching Energy Ets
tbd µJ
Free-wheeling Silicon Carbide Schottky Diode
Forward Voltage VF IF = 10 A, VGE = 0 V,
Tj = 25 ºC (175 ºC ) 1.55 V
Diode Knee Voltage VD
(
knee
)
Tj = 25 ºC, IF = 1 mA 0.8 V
Peak Reverse Recovery Current Irrm IF = 10 A, VGE = 0 V, VR = 800 V,
-dIF/dt = 625 A/µs, Tj = 175 ºC
tbd A
Reverse Recovery Time trr tbd ns
Rise Time tr
VDD= 800 V, ID = 10 A,
Rgon = Rgoff = tbd Ω,
Tj= 25 ºC
tbd ns
Fall Time tf tbd ns
Turn-On Energy Loss Per Pulse Eon tbd μJ
Turn-Off Energy Loss Per Pulse Eoff tbd μJ
Reverse Recovery Charge Qrr tbd nC
Rise Time tr
VDD= 800 V, ID = 10 A,
Rgon = Rgoff = tbd Ω,
Tj= 175 ºC
tbd ns
Fall Time tf tbd ns
Turn-On Energy Loss Per Pulse Eon tbd μJ
Turn-Off Energy Loss Per Pulse Eoff tbd μJ
Reverse Recovery Charge Qrr tbd nC
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Figures
TBD
TBD
Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 125 °C
TBD
TBD
Figure 3: Typical Output Characteristics at 175 °C Figure 4: Typical Gate Source I-V Characteristics vs.
Temperature
TBD
TBD
Figure 5: Normalized On-Resistance and Current Gain vs.
Temperature Figure 6: Typical Blocking Characteristics
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TBD TBD
Figure 7: Capacitance Characteristics Figure 8: Capacitance Characteristics
TBD TBD
Figure 9: Typical Hard-switched Turn On Waveforms Figure 10: Typical Hard-switched Turn Off Waveforms
TBD TBD
Figure 11: Typical Turn On Energy Losses and Switching
Times vs. Temperature Figure 12: Typical Turn Off Energy Losses and Switching
Times vs. Temperature
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TBD
TBD
Figure 13: Typical Turn On Energy Losses vs. Drain
Current Figure 14: Typical Turn Off Energy Losses vs. Drain
Current
TBD
TBD
Figure 15: Typical Gate Current Waveform Figure 16: Typical Hard Switched Device Power Loss vs.
Switching Frequency 1
TBD
TBD
Figure 17: Power Derating Curve Figure 18: Forward Bias Safe Operating Area
1 – Representative values based on device switching energy loss. Actual losses will depend on gate drive conditions, device load, and circuit topology.
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TBD TBD
Figure 19: Turn-Off Safe Operating Area Figure 20: Transient Thermal Impedance
Figure 21: Typical FWD Forward Characteristics
GA10SICP12-247
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Gate Drive Technique (Option #1)
To drive the GA10SICP12-247 with the lowest gate drive losses, please refer to the dual voltage source gate drive
configuration described in Application Note AN-10B (http://www.genesicsemi.com/index.php/references/notes).
Gate Drive Technique (Option #2)
The GA10SICP12-247 can be effectively driven using the IXYS IXDN614 / IXDD614 non-inverting gate driver IC or a
comparable product. A typical gate driver configuration along with component values using this driver is offered below.
Additional information is available in GeneSiC Application Note AN-10A and from the manufacturer at www.ixys.com.
Figure 21: Recommended Gate Diver Configuration (Option #2)
Parameter Symbol Conditions Values Unit
min. typ. max.
Option #2 Gate Drive Conditions (IXDD614/IXDN614)
Supply Voltage VCC -0.3 15 40 V
Gate Control Input Signal, Low IN -5.0 0 0.8 V
Gate Control Input Signal, High IN 3.0 5.0 VCC+0.3 V
Enable, Low EN IXDD614 Only 1/3*VCC V
Enable, High EN IXDD614 Only 2/3*VCC V
Output Voltage, Low VOUT 0.025 V
Output Voltage, High VOUT VCC-0.025 V
Output Current, Peak IOUT Package Limited tbd 14 A
Output Current, Continuous IOUT tbd 4.0 A
Passive Gate Components
Gate Resistance RGP IG ≈ 0.5 A 5 tbd Ω
Gate Capacitance CGP IG ≈ 0.5 A tbd nF
+5V / 0V
Gate Control Signal
RGP
CGP
G
D
S
SiC SJT Co-pack
IG
VCC
IN
OUT
VEE
Gate Drive IC
IXDN614/
IXDD614
VGG
(+15 V)
VO
VGG
(+15 V)
EN
GA10SICP12-247
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Package Dimensions:
TO-247AB PACKAGE OUTLINE
NOTE
1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER.
2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS
Revision History
Date Revision Comments Supersedes
2013/09/12 0 Initial release
Published by
GeneSiC Semiconductor, Inc.
43670 Trade Center Place Suite 155
Dulles, VA 20166
GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice.
GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any
intellectual property rights is granted by this document.
Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft
navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal
injury and/or property damage.
GA10SICP12-247
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SPICE Model Parameters
Copy the following code into a SPICE software program for simulation of the GA10SICP12-247 device.
* MODEL OF GeneSiC Semiconductor Inc.
*
* $Revision: 1.0 $
* $Date: 20-SEP-2013 $
*
* GeneSiC Semiconductor Inc.
* 43670 Trade Center Place Ste. 155
* Dulles, VA 20166
* http://www.genesicsemi.com/index.php/sic-products/copack
*
* COPYRIGHT (C) 2013 GeneSiC Semiconductor Inc.
* ALL RIGHTS RESERVED
*
* These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY
* OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE."
* Models accurate up to 2 times rated drain current.
*
* Start of GA10SICP12-247 SPICE Model
*
.SUBCKT GA10SIPC12 DRAIN GATE SOURCE
Q1 DRAIN GATE SOURCE GA10SIPC12_Q
D1 SOURCE DRAIN GA10SIPC12_D1
D2 SOURCE DRAIN GA10SIPC12_D2
.model GA10SIPC12_Q NPN
+ IS 5.00E-47 ISE 1.26E-28 EG 3.2
+ BF 100 BR 0.55 IKF 350
+ NF 1 NE 2 RB 0.26
+ RE 0.01 RC 0.1 CJC 3.5E-10
+ VJC 3 MJC 0.5 CJE 1.11E-09
+ VJE 3 MJE 0.5 XTI 3
+ XTB -1.2 TRC1 7.00E-03 MFG GeneSiC_Semi
.MODEL GA10SIPC12_D1 D
+ IS 4.55E-15 RS 0.0736 N 1
+ IKF 1000 EG 1.2 XTI -2
+ TRS1 0.005434 TRS2 2.71739E-05 CJO 6.40E-10
+ VJ 0.469 M 1.508 FC 0.5
+ TT 1.00E-10
.MODEL GA10SIPC12_D2 D
+ IS 1.54E-22 RS 0.19 TRS1 -0.004
+ N 3.941 EG 3.23 IKF 19
+ XTI 0 FC 0.5 TT 0
.ENDS
* End of GA10SICP12-247 SPICE Model
