A3936SEDTR-T - Allegro MicroSystems, Inc.

Description

Designed for pulse-width-modulated (PWM) current control

of three-phase brushless DC motors, the A3936 is capable of

peak output currents to ±3 A and operating voltages to 50 V.

Internal fixed off-time PWM current-control timing circuitry

can be configured to operate in slow-, fast- and mixed-decay

modes.

Internal synchronous rectification control circuitry is provided

to improve power dissipation during PWM operation.

Internal circuit protection includes thermal shutdown with

hysteresis, and crossover current protection. Special power-up

sequencing is not required.

The A3936 is supplied in a 44-pin plastic PLCC with internally

fused leads (three on each side) for enhanced heat dissipation.

These leads are at ground potential and need no electrical

isolation. This device is lead (Pb) free version, with 100%

matte tin leadframe plating.

A3936-DS, Rev. 8

Features and Benefits

▪ ±3 A, 50 V continuous output rating

▪ Low rDS(on) outputs (typically 500 mΩ source,

315 mΩ sink)

▪ Configurable mixed-, fast- and slow-current-decay modes

▪ Synchronous rectification for low power dissipation

▪ Internal UVLO and thermal shutdown circuitry

▪ Crossover-current protection

▪ Tachometer output for external speed control loop

DMOS Three-Phase PWM Motor Driver

Package: 44-pin PLCC (suffix ED)

Typical Application

Not to scale

A3936

3X Half Bridge

OUTA

VBB1

VCP

VDD

TACH

HBIAS

SLEEP

DIR

EXT MODE

BRAKE

ENABLE

BLANK

PFD1

PFD2

VDD

CP2CP1VREG

OUTB

OUTC

LSS1

LSS2

HA–

HB–

HC–

HA+

HB+

HC+

SENSE

VBB2

Charge PumpRegulator Osc

Zero Current Detect

Current Sense

OSC

GND GND GND

Control Logic

and Gate Drive

Fixed Off-Time

PWM Current Ctrl.

Blanking Time

Crossover

Current Protection

TSD

UVLO [VDD

VREG VCP]

Sync. Rect.

Fast, Slow, and

Mixed Decay

DMOS Three-Phase PWM Motor Driver

A3936

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units

Load Supply Voltage VBB 50 V

Logic Supply Voltage VDD 7.0 V

Logic Input Votage Range VIN tw > 30 ns –0.3 to VDD + 0.3 V

tw < 30 ns –1.0 to VDD + 1 V

Sense Voltage VSENSE 0.5 V

Reference Voltage VREF VDD V

Output Current IOUT

Output current rating may be limited by duty cycle,

ambient temperature, and heat sinking. Under any

set of conditions, do not exceed the specified cur-

rent rating or a junction temperature of 150°C.

±3 A

Operating Ambient Temperature T ARange S –20 to 85 ºC

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature Tstg –55 to 150 ºC

Selection Guide

Part Number Packing Package

A3936SEDTR-T* 450 pieces per reel 44-pin PLCC with internally fused leads

*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the vari-

ant is obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applica-

tions. The variant should not be purchased for new design applications because of obsolescence in the near future.

Samples are no longer available. Status date change November 2, 2009. Deadline for receipt of LAST TIME BUY

orders is April 30, 2010.

DMOS Three-Phase PWM Motor Driver

A3936

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

VDD

GND

REF

HA+

SENSE

CURRENT

SENSE

ZERO

CURRENT

DET ECT

.1uF

REGULATOR CHARG E PUMP

VREG

CP1

CP2

BANDGAP

.22uf/100V

.22uf/50V

GATE

DRIVE

HA-

HB+

PWM

TIMER

OSC

TACH

OUTA

OUTB

OUTC

OVERVOLTAGE

UNDERVOLTAGE

AND FAULT

DETECT

BUFFER/

DIVIDER

VCPVREG

HB-

HC+

HC-

HALL

Comm

Log ic

DIR

SLEEP

Control

Log ic

VCP

VBB1

ENABLE

EXTMODE

BRAKE

BLANK

HBIAS

PFD1

PFD2

VDD

VBB2

LSS1

LSS2

Functional Block Diagram

DMOS Three-Phase PWM Motor Driver

A3936

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS at TJ=+25°C,VBB=50V,V

DD =5.0V,fPWM < 50KHz (unless noted otherwise)

Limits

stinU.xaM.pyT.niMsnoitidnoCtseTlobmySscitsiretcarahC

Output Drivers

V05–9gnitarepOBBVegnaRegatloVylppuSdaoL

V050edoMpeelSgniruD

ItnerruCegakaeLtuptuO DSS VOUT =V

BB –<1.020 μA

VOUT 02-0.1–<–V0= MA

RecnatsiseRnOtuptuO DSON Source Driver, IOUT 55.–A3-= 7

Sink Driver, IOUT 53.–A3= 7

Body Diode Forward Voltage VFSource Diode, IFV4.1––A3-=

Sink Diode, IFV3.1––A3=

ItnerruCylppuSrotoM BB fPWM Am74–zHk05<

Charge Pump On, Outputs Disabled – 2 5 mA

Au02––edoMpeelS

IDD fPWM Am01–zHk05<

Am8–ffOstuptuO

Logic Supply Current

001)V5.wolebstupnI(edoMpeelS MA

Control Logic

Logic Supply Voltage Range VDD V5.50.53gnitarepO

VegatloVtupnIcigoL IN(1) VDD*.5 – – V

VIN(0) ––V

DD*.2 V

ItnerruCtupnIcigoL IN(1) VIN =V

DD Aμ020.1<02-5.*

I)ELBANEtpecxe( IN(0) VIN =V

DD Aμ020.1-<02-2.*

ItnerruCtupnIcigoL IN(1) VIN =V

DD Aμ001–5.*

ItupnIELBANE IN(0) VIN =V

DD Aμ03–2.*

zHM543DNGotdetrohsCSOfrotallicsOlanretnI OSC

ROSC zHM6.444.3K15=

Continued on the next page...

DMOS Three-Phase PWM Motor Driver

A3936

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICALCHARACTERISTICS (continued) at TJ=+25°C,V

BB =50V,V

DD = 5.0 V, fPWM <50KHz

(unless notedotherwise)

Limits

stinU.xaM.pyT.niMsnoit

dnoCt

eTlobmySscitsiretca

Control Logic

V.tloVtesffOtupnIreffuB IO ±10 mV

VREF V–0.0gnit

Oeg

IDD V

Reference Input Current IREF VREF =V

DD ,VBB 5.

V05ot0

=MA

Comparator Input Offset Volt. VIO VREF V

5±

VREF =V

DD -4 4 %GMVrorr

EERR

(Note 3) VREF %

141-V5.=

Propagation Delay Times tpd 50% TO 90%, SR Enabled

PWM CHANGE TO SOURCE ON 600 750 1000 ns

PWM CHANGE TO SOURCE OFF 50 150 350 ns

PWM CHANGE TO SINK ON 600 750 1000 ns

PWM CHANGE TO SINK OFF 50 100 150 ns

tyaleDrevossorC COD sn0001006003delbanERS

Thermal Shutdown Temp. TJ–165– °C

Thermal Shutdown Hysteresis $TJ–15– °C

Vgni

iRdlo

rhTe

LVU DD 2.45 2.7 2.95 V

UVLO Hysteresis 0.05 0.10 – V

Continued on the next page...

DMOS Three-Phase PWM Motor Driver

A3936

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Limits

sti

U.xaM.pyT.niMsnoitidnoCtseTlob

ySscitsiretcarahC

Hall Logic

ruCtu

aH HALL VIN 10

V2.

=MA

RMC

aRtupn

edoMn

omm

AC Input Voltage Range VHALL p

-pV021.

HHYS TAVm0301

Cged58o

Pulse Reject Filter 35.58 Ms

Hall Bias Output Sat Voltage VHB IOUT=40mA, TAV5.4..Cg

d58ot0

IHB 40 mA

hcaT OL IOUT V

005

ELECTRICALCHARACTERISTICS (continued) at TJ=+25°C,V

BB =50V,V

DD =5.0V,f

PWM <50KHz

(unless notedotherwise)

NOTES: 1. Typical Data is for design information only.

2. Negative current is defined as coming out of (sourcing) the specified device pin.

3. VERR =((VREF/10) – VSENSE)/(VREF/10)

Commutation Truth Table

120 spacing Outputs

HA HB HC DIR OUTA OUTB OUTC

1+-+FOR HI LO Z

2+- - FOR HI Z LO

3++- FOR Z HI LO

4-+-FOR LO HI Z

5-++FOR LO Z HI

6--+FOR Z LO HI

1+-+REV LO HI Z

2 + - - REV LO Z HI

3 + + - REV Z LO HI

4-+- REV HI LO Z

5-++REV HI Z LO

6 - - + REV Z HI LO

--- X Z Z Z

+++ X Z Z Z

DMOS Three-Phase PWM Motor Driver

A3936

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Description

VREG. The VREG pin should be decoupled with a 0.22

μF capacitor to ground. This supply voltage is used to run

the sink side DMOS outputs. VREG is internally monitored

and in the case of a fault condition, the outputs of the device

are disabled.

Charge Pump. The Charge Pump is used to generate a

supply above VBB to drive the source side DMOS gates. A

0.22 uF ceramic monolithic capacitor should be connected

between CP1and CP2for pumping purposes. A 0.22 uF

ceramic monolithic capacitor should be connected between

VCP and VBB to act as a reservoir to run the high side

DMOS devices. The VCP Voltage is internally monitored

and in the case of a fault condition the outputs of the device

are disabled.

Shutdown. In the event of a fault due to excessive

junction temperature, or low voltage on VCP or VREG,the

outputs of the device are disabled until the fault condition is

removed. At power up, and in the event of low VDD,the

UVLO circuit disables the drivers.

Current Regulation. Load current is regulated by an

internal fixed off time PWM control circuit. When the

outputs of the DMOS H-bridge are turned on, current

increases in the motor winding until it reaches a value given

by:

ITRIP =V

REF/(10*RSENSE)

At the trip point, the sense comparator resets the source

enable latch, turning off the source driver. At this point,

load inductance causes the current to recirculate for the

fixed off time period. The current path during recirculation

is determined by the configuration of slow/mixed decay

mode and the synchronous rectification control setting.

Enable Logic. The Enable input terminal allows

external PWM. ENABLE high turns ON the selected sink-

source pair, enable low switches off the appropriate drivers

and the load current decays. If the ENABLE pin is held

high, the current will rise until it reaches the level set by the

internal current control circuit.

ENABLE Outputs

0 Source

Chopped

1ON

Extmode Logic. When using external PWM current

control, the EXTMODE input determines the current path

during the chopped cycle. With EXTMODE set low, fast

decay mode, both the source and sink drivers are chopped

OFF during the decay time (ENABLE=0). With

EXTMODE high, slow decay mode, only the source driver

turns off during the current decay time.

EXTMODE Decay

0Fast

1Slow

Sleep Mode. The input pin SLEEP is dedicated to put

the device into a minimum current draw mode. When

asserted low, all circuits are disabled.

Fixed Off-Time. The 3936 is set for a fixed off time of

96 counts of the internal oscillator, typically 24 μs with

4Mhz oscillator.

Internal Current Control Mode. Input pins PFD1

and PFD2 determine the current decay method after an

overcurrent event is detected at sense input. In slow decay

mode both sink side drivers are turned on for the fixed off

time period. Mixed decay mode starts out in fast decay

mode for the selected percentage of the fixed off time, and

then is followed by slow decay for the rest of the period.

PFD2 PFD1 % tOFF Decay

00 0Slow

0 1 15 Mixed

1 0 48 Mixed

1 1 100 Fast

DMOS Three-Phase PWM Motor Driver

A3936

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

PWM Blank Timer. When a source driver turns on, a

current spike occurs due to the reverse recovery currents of

the clamp diodes and/or switching transients related to

distributed capacitance in the load. To prevent this current

spike from erroneously resetting the source enable latch, the

sense comparator is blanked. The blank timer runs after the

off time counter to provide the blanking function. The blank

timer is reset when ENABLE is chopped or DIR is changed.

For external PWM control, a DIR change or ENABLE ON

will trigger the blanking function. The duration is adjusted

by control input BLANK.

BLANK tBLANK

06/f

OSC

112/f

OSC

Synchronous Rectification. Logic high applied to

the SR terminal enables synchronous rectification. When a

PWM off cycle is triggered, either by an ENABLE chop

command or internal fixed off time cycle, load current will

recirculate according to the decaymode selected by control

logic. The A3936 synchronous rectification feature will turn

on the appropriate MOSFET(s)during the current decay and

effectively short out the body diodes with the low Rdson

driver. This will lower power dissipation significantly and

can eliminate the need for external schottky diodes.

Reversal of load current is prevented by turning off

synchronous rectification when a zero current level is

detected.

Brake. Logichightothebraketerminalactivatesthe

brake function, logic low allows normal operation. Brake

will turn all three sink drivers ON and effectively shorts out

the motor generated BEMF. It is important to note that the

internal PWM current control circuit will not limit the

current when braking, since the current does not flow

through the sense resistor. The maximum current can be

approximated by VBEMF/RL.Careshouldbetakentoinsure

that the maximum ratings of the device are not exceeded in

worse case braking situations of high speed and high

inertial loads.

Oscillator. The PWM timer is based on an internal

oscillator set by a resistor connected from the OSC terminal

to VDD. Typical value of 4Mhz is set with 51k resistor.

FOSC = 204E9/ROSC.

Tach. A tachometer signal is available for speed

measurement. This open collector output toggles at each

Hall transition.

DMOS Three-Phase PWM Motor Driver

A3936

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Terminal List

Pin No. Pin Name Pin Description

1GND

2GND

3 HA+ Hall input

4 HA- Hall input

5 HB+ Hall input

6 HB- Hall input

7 HC+ Hall input

8 HC- Hall input

DD Logic Supply Voltage

10 REF GmReference Input Voltage

11 GND

12 GND

13 GND

14 BRAKE Logic Input

15 SENSE Sense Resistor Connection

16 SR Logic Input (Disabled = Low, Active SR = High)

17 OUTA DMOS H – Bridge A

18 HBIAS Connection for hall element neg side

19 VBB1 Load Supply Voltage

20 LSS1 Low Side Source connection

21 OUTB DMOS H – Bridge B

22 GND

23 GND

24 GND

25 LSS2 Low Side Source connection

26 VBB2 Load Supply Voltage

27 TACH Speed output

28 OUTC DMOS H – Bridge C

29 VCP Reservoir Capacitor Terminal

30 CP1 Charge Pump Capacitor Terminal

31 CP2 Charge Pump Capacitor Terminal

32 SLEEP Logic input for SLEEP mode

33 GND

34 GND

35 GND

36 OSC Oscillator Terminal

37 VREG Regulator decoupling Terminal

38 DIR Logic Input

39 ENABLE Logic Input

40 EXTMODE Logic Input

41 BLANK Logic Input

42 PFD2 Logic Input

43 PFD1 Logic Input

44 GND Power Ground Tab

ENABLE

DIR

VREG

OSC

GND

SLEEP

CP2

CP1

VCP

HC+

HC-

VDD

REF

GND

BRAKE

SENSE

OUTA

HB-

HB+

HA-

HA+

GND

PFD1

PFD2

BLANK

EXTMODE

HBIAS

VBB1

LSS1

OUTB

GND

LSS2

VBB2

TACH

OUTC

Pin-out Diagram

DMOS Three-Phase PWM Motor Driver

A3936

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

2144

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

ATerminal #1 mark area

For Reference Only

(reference JEDEC MS-018 AC)

Dimensions in millimeters

Internally fused pins: 1, 2, and 44; 11, 12, and 13; 22, 23, and 24; and 33, 34, and 35.

SEATING

PLANE

0.51

4.57 MAX

16.59 ±0.08

7.75 ±0.36

7.75 ±0.367.75 ±0.36

C0.10

44X

0.74 ±0.08

17.53 ±0.13

1.27

0.43 ±0.10

Package ED 44-Pin PLCC