Features
•16 Mbit SRAM Multi Chip Module
•Allows 32-, 16- or 8-bit access configuration
•Operating Voltage: 3.3V + 0.3V, 5V Tolerant
•Access Time:
– 25 ns, 20 ns
– 18 ns (preliminary information)
•Very Low Power Consumption
– Active: 595 mW per byte (Max) @ 20 ns(1), 415mW per byte (Max) @ 50ns(2)
– Standby: 15 mW (Typ)
•Military Temperature Range: -55 to +125°C
•TTL-Compatible Inputs and Outputs
•Asynchronous
•Die manufactured on Atmel 0.25 µm Radiation Hardened Process
•No Single Event Latch Up below LET Threshold of 80 MeV/mg/cm2
•Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019
•ESD Better than 2000V
•Quality Grades:
– QML-Q or V with SMD 5962-06229
–ESCC
•950 Mils Wide MQFP 68 Package
•Mass : 8.5 grams
Notes: 1. For AT68166FT-20 only. 540mW for AT68166FT-25.
2. For AT68166FT-20 only. 450mW for AT68166FT-25.
Description
The AT68166FT is a 16Mbit SRAM packaged in a hermetic Multi Chip Module (MCM)
for space applications.
The AT68166FT MCM incorporates four 4Mbit AT60142FT SRAM dice. It can be orga-
nized as either one bank of 512Kx8, two banks of 512Kx16 or four banks of 512Kx8. It
combines rad-hard capabilities, a latch-up threshold of 80MeV.cm²/mg, a Multiple Bit
Upset immunity and a total dose tolerance of 300Krads, with a fast access time.
The MCM packaging technology allows a reduction of the PCB area by 50% with a
weight savings of 75% compared to four 4Mbit packages.
Thanks to the small size of the 4Mbit SRAM die, Atmel has been able to accommo-
date the assembly of the four dice on one side of the package which facilitates the
power dissipation.
The compatibility with other products allows designers to easily migrate to the Atmel
AT68166FT memory.
The AT68166FT is powered at 3.3V and is 5V tolerant.
The AT68166FT is processed according to the test methods of the latest revision of
the MIL-PRF-38535 or the ESCC 9000.
7531H–AERO–04/09
Rad Hard
16 MegaBit 3.3V
5V Tolerant
SRAM Multi-
Chip Module
AT68166FT
2
7531H–AERO–04/09
AT68166FT
Block Diagram Figure 1. AT68166FT Block Diagram
Figure 2. 512K x 8 Banks Block Diagram (AT60142FT)
Packages AT68166FT is packed in MQFP68.
The pin assignment depends on the access time. There are 2 versions:
– YM package where 3 pins are not connected.
– YS package where the 3 above pins are connected to GND or VCC.
A[18:0]
OE
CS1
WE1
I/O[15:8]
BANK1
512k x 8
CS2
WE2
I/O[23:16]
BANK2
512k x 8
CS3
WE3
I/O[31:24]
BANK3
512k x 8
CS0
WE0
I/O[7:0]
BANK0
512k x 8
or
I/O2[31:16]
or
I/O2[15:0]
or
I/O1[31:16]
or
I/O1[15:0]
or
I/O3[7:0]
or
I/O2[7:0]
or
I/O1[7:0]
or
I/O[7:0]
A0
-
-
-
A10
I/Ox0
I/Ox7
CSx
WEx
OE
Access Times
25 ns 20 ns 18 ns
AT68166FT YM YS YS
3
7531H–AERO–04/09
AT68166FT
Pin
Configuration Table 1. AT68166FT pin assignment in YS package
Note: In YM package leads 33, 34 and 68 are not connected.
Lead Signal Lead Signal Lead Signal Lead Signal
1 I/O0[0] 18 VCC 35 I/O3[7] 52 VCC
2 I/O0[1] 19 A11 36 I/O3[6] 53 A10
3 I/O0[2] 20 A12 37 I/O3[5] 54 A9
4 I/O0[3] 21 A13 38 I/O3[4] 55 A8
5 I/O0[4] 22 A14 39 I/O3[3] 56 A7
6 I/O0[5] 23 A15 40 I/O3[2] 57 A6
7 I/O0[6] 24 A16 41 I/O3[1] 58 WE0
8 I/O0[7] 25 CS0 42 I/O3[0] 59 CS3
9GND26OE43 GND 60 GND
10 I/O1[0] 27 CS1 44 I/O2[7] 61 CS2
11 I/O1[1] 28 A17 45 I/O2[6] 62 A5
12 I/O1[2] 29 WE1 46 I/O2[5] 63 A4
13 I/O1[3] 30 WE2 47 I/O2[4] 64 A3
14 I/O1[4] 31 WE3 48 I/O2[3] 65 A2
15 I/O1[5] 32 A18 49 I/O2[2] 66 A1
16 I/O1[6] 33 GND 50 I/O2[1] 67 A0
17 I/O1[7] 34 VCC 51 I/O2[0] 68 VCC
4
7531H–AERO–04/09
AT68166FT
Figure 3. AT68166FT pin assignment in YM package
Figure 4. AT68166FT pin assignment in YS package
I/O0[0]
I/O0[1]
I/O0[2]
I/O0[3]
I/O0[4]
I/O0[5]
I/O0[6]
I/O0[7]
GND
I/O1[0]
I/O1[1]
I/O1[2]
I/O1[3]
I/O1[4]
I/O1[5]
I/O1[6]
I/O1[7]
I/O2[0]
I/O2[1]
I/O2[2]
I/O2[3]
I/O2[4]
I/O2[5]
I/O2[6]
I/O2[7]
GND
I/O3[0]
I/O3[1]
I/O3[2]
I/O3[3]
I/O3[4]
I/O3[5]
I/O3[6]
I/O3[7]
AT68166FT
(top view)
NC
A0
A1
A2
A3
A4
A5
CS2
GND
CS3
WE0
A6
A7
A8
A9
A10
VCC
NC
NC
A18
WE3
WE2
WE1
A17
CS1
0E
CS0
A16
A15
A14
A13
A12
A11
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
I/O0[0]
I/O0[1]
I/O0[2]
I/O0[3]
I/O0[4]
I/O0[5]
I/O0[6]
I/O0[7]
GND
I/O1[0]
I/O1[1]
I/O1[2]
I/O1[3]
I/O1[4]
I/O1[5]
I/O1[6]
I/O1[7]
I/O2[0]
I/O2[1]
I/O2[2]
I/O2[3]
I/O2[4]
I/O2[5]
I/O2[6]
I/O2[7]
GND
I/O3[0]
I/O3[1]
I/O3[2]
I/O3[3]
I/O3[4]
I/O3[5]
I/O3[6]
I/O3[7]
AT68166FT
(top view)
VCC
A0
A1
A2
A3
A4
A5
CS2
GND
CS3
WE0
A6
A7
A8
A9
A10
VCC
VCC
GND
A18
WE3
WE2
WE1
A17
CS1
0E
CS0
A16
A15
A14
A13
A12
A11
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
5
7531H–AERO–04/09
AT68166FT
Pin Description
Table 2. Pin Names
Note: 1. The package lid is connected to GND
Table 3. Truth Table(1)
Name Description
A0 - A18 Address Inputs
I/O0 - I/O31 Data Input/Output
CS0 - CS3 Chip Select
WE0 - WE3 Write Enable
OE Output Enable
VCC Power Supply
GND(1) Ground
CSxWEx OE Inputs/Outputs Mode
H X X Z Standby
L H L Data Out Read
L L X Data In Write
L H H Z Output Disable
Note: 1. L=low, H=high, X= H or L, Z=high impedance.
6
7531H–AERO–04/09
AT68166FT
Electrical Characteristics
Absolute Maximum Ratings*
Military Operating Range
Recommended DC Operating Conditions
Note: 1. 5.8V in transient conditions.
Capacitance
Note: 1. Guaranteed but not tested.
Supply Voltage to GND Potential: ...................... -0.5V to 4.6V
Voltage range on any input: ......................... GND -0.5V to 7V
Voltage range on any ouput: ........................ GND -0.5V to 7V
Storage Temperature: .................................... -65⋅C to +150⋅C
Output Current from Outputs Pins: .............................. 20 mA
Electrostatic Discharge Voltage: ............................... > 2000V
(MIL STD 883D Method 3015.3)
*NOTE: Stresses beyond those listed under "Abso-
lute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions
beyond those indicated in the operational
sections of this specification is not implied.
Exposure between recommended DC
operating and absolute maximum rating
conditions for extended periods may
affect device reliability.
Operating Voltage Operating Temperature
3.3 + 0.3V -55°C to + 125°C
Parameter Description Min Typ Max Unit
Vcc Supply voltage 3 3.3 3.6 V
GND Ground 0.0 0.0 0.0 V
VIL Input low voltage GND - 0.3 0.0 0.8 V
VIH Input high voltage 2.2 – 5.5V(1) V
Parameter Description Min Typ Max Unit
Cin(1) (OE and Ax) Input capacitance – – 48 pF
Cin(1) (CSx and
WEx) Input capacitance – – 12 pF
Cio(1) I/O capacitance – – 12 pF
7
7531H–AERO–04/09
AT68166FT
DC Parameters
Notes: 1. GND < VIN < VCC, GND < VOUT < VCC Output Disabled.
2. VIN = 5.5V, VOUT = 5.5V, Output Disabled.
3. VCC min. - IOL = 6 mA
4. VCC min. IOH = -4 mA
Parameter Description Minimum Typical
Maximum
UnitAT68166FT-25 AT68166FT-20 AT68166FT-18
IIX(1) Input leakage
current -1–111μA
IOZ(1) Output leakage
current -1–111μA
IIH(2) at 5.5V
Input Leakage
Current (OE &
Axx)
–– 10 6 6 μA
Input Leakage
Current (WE &
CS)
––522µA
IOZH(2) at 5.5V Output Leakage
Current –– 5 1.5 1.5 μA
VOL(3) Output low
voltage – – 0.4 0.4 0.4 V
VOH(4) Output high
voltage 2.4–––– V
8
7531H–AERO–04/09
AT68166FT
Consumption
Notes: 1. All CSx >VIH
2. All CSx > VCC - 0.3V
3. F = 1/TAVAV, Iout = 0 mA, WEx = OE = VIH, VIN = GND/VCC, VCC max.
4. F = 1/TAVAW, Iout = 0 mA, WEx = VIL, OE = VIH , VIN = GND/VCC, VCC max.
Data Retention
Mode
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and sup-
ply current are guaranteed over temperature. The following rules insure data retention:
1. During data retention chip select CSx must be held high within VCC to VCC -0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, mini-
mizing power dissipation.
3. During power-up and power-down transitions CSx and OE must be kept between VCC +
0.3V and 70% of VCC.
4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages
(3V).
Figure 5. Data Retention Timing
Symbol Description
TAVAV/TAVAW
Test Condition
AT68166FT-25 AT68166FT-20 AT68166FT-18
(preliminary) Unit Value
ICCSB(1)
Standby
Supply
Current
– 10 7 7.5 mA max
ICCSB1(2)
Standby
Supply
Current
–867mAmax
ICCOP(3)
Read per
byte
Dynamic
Operating
Current
18 ns
20 ns
25 ns
50 ns
1 µs
–
–
150
85
15
–
165
145
80
12
170
165
145
80
12
mA max
ICCOP(4)
Write per
byte
Dynamic
Operating
Current
18 ns
20 ns
25 ns
50 ns
1 µs
–
–
150
125
110
–
140
135
115
105
145
140
135
115
105
mA max
vcc
CSx
9
7531H–AERO–04/09
AT68166FT
Data Retention Characteristics
Parameter Description Min Typ TA = 25°CMax Unit
VCCDR VCC for data retention 2.0 – – V
tCDR
Chip deselect to data
retention time 0.0 – – ns
tR
Operation recovery
time tAVAV (1)
1. TAVAV = Read cycle time.
––ns
ICCDR (2)
2. All CSx = VCC, VIN = GND/VCC.
Data retention current – 3
6 (AT68166FT-25)
mA4.5 (AT68166FT-20)
5 (AT68166FT-18)
10
7531H–AERO–04/09
AT68166FT
AC Characteristics
Temperature Range:................................................ -55 +125°C
Supply Voltage: ....................................................... 3.3 +0.3V
Input Pulse Levels: .................................................. GND to 3.0V
Input Rise and Fall Times:....................................... 3ns (10 - 90%)
Input and Output Timing Reference Levels: ............ 1.5V
Output Loading IOL/IOH:............................................ See Figure 3
Figure 6. AC Test Loads Waveforms
Write Cycle
Table 4. Write cycle timings(1)
Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 10.)
Specific (TWLQZ, TWHQX, TELQX, TEHQZ
TGLQX, TGHQZ)
General
Symbol Parameter
AT68166FT-25 AT68166FT-20 AT68166FT-18
(preliminary)
Unitmin max min max min max
TAVAW Write cycle time 20 - 20 - 18 - ns
TAVWL Address set-up time 2 - 2 - 2 - ns
TAVWH Address valid to end of write 14 - 11 - 10 - ns
TDVWH Data set-up time 9 - 8 - 7 - ns
TELWH CS low to write end 12 - 12 - 11 - ns
TWLQZ Write low to high Z(2) -10-10- 9 ns
TWLWH Write pulse width 12 - 9 - 9 - ns
TWHAX Address hold from end of
write 0-0-0-ns
TWHDX Data hold time 2 - 1 - 1 - ns
TWHQX Write high to low Z(2) 5-5-5-ns
11
7531H–AERO–04/09
AT68166FT
Figure 7. Write Cycle 1. WE Controlled, OE High During Write
Figure 8. Write Cycle 2. WE Controlled, OE Low
Figure 9. Write Cycle 3. CS Controlled
The internal write time of the memory is defined by the overlap of CS Low and WE LOW. Both signals must
be activated to initiate a write and either signal can terminate a write by going in active mode. The data
input setup and hold timing should be referenced to the active edge of the signal that terminates the write.
Data out is high impedance if OE= VIH.
E
E
ADDRESS
CSx
WEx
I/Os
OE
E
E
ADDRESS
CSx
WEx
I/Os
E
ADDRESS
CSx
WEx
I/Os
12
7531H–AERO–04/09
AT68166FT
Read Cycle
Table 5. Read cycle timings(1)
Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode.
2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 10.)
Symbol Parameter
AT68166FT-25 AT68166FT-20 AT68166FT-18
(preliminary)
Unitmin max min max min max
TAVAV Read cycle time 25 - 20 - 18 - ns
TAVQV Address access time - 25 - 20 - 18 ns
TAVQX Address valid to low Z 5 - 5 - 5 - ns
TELQV Chip-select access time - 25 - 20 - 18 ns
TELQX CS low to low Z(2) 5-5-5-ns
TEHQZ CS high to high Z(2) -10- 9 - 9ns
TGLQV Output Enable access time - 12 - 10 - 9 ns
TGLQX OE low to low Z(2) 2-2-2-ns
TGHQZ OE high to high Z (2) -10- 9 - 9ns
13
7531H–AERO–04/09
AT68166FT
Figure 10. Read Cycle nb 1: Address Controlled (CS = OE = VIL, WE = VIH)
Figure 11. Read Cycle nb 2: Chip Select Controlled (WE = VIH)
ADDRESS
DOUT
CSx
OE
DOUT
14
7531H–AERO–04/09
AT68166FT
Typical
Applications
This section presents some standard implementations of the AT68166FT in application.
32-bit mode
application
When used on a 32-bit (word) application, the module shall be connected as follow :
• The 32 lines of data are connected to distinct data lines
• The four CSx are connected together and linked to a single host CS output
• Each one of the four WEx is connected to a dedicated WE line on the host to allow byte, half
word and word format write.
Figure 12. 32-bit typical application ( 1 SRAM bank)
16-bit mode
application
When used on a 16-bit (half word) application, the module can be connected as presented in the
following figure. This allows use of a single AT68166FT part for two SRAM memory banks.
All input controls of the AT68166FT not used in the application shall be pulled-up.
Figure 13. 16-bit typical application (two SRAM banks)
8-bit mode
application
When used on a 8-bit (byte) application, the module can be connected as presented in the fol-
lowing figure. This allows use of a single AT68166FT part for up to four SRAM memory banks.
All input controls of the AT68166FT not used in the application shall be pulled-up.
CS[3:0]
OE
WE[3:0]
A[17:0]
I/O[31:0]
AT68166FT
RAMOE0*
AD
TSC695F
A[27:0]
D[31:0]
D[31:0]
A[19:2]
RWE[3:0]*
RAMS0* A[19:2]
D[31:0]
A[17:0]
I/O[15:0]
AT68166FT A
D
TSC695F
A[27:0]
D[31:0]
D[31:16]
A[18:1]
A[18:1]
D[31:0]
I/O[31:16] D[31:16]
CS[1:0]
WE[1:0]
RWE0*
RAMS0*
CS[3:2]
WE[3:2]
RWE0*
RAMS1*
OE
RAMOE[1:0]*
15
7531H–AERO–04/09
AT68166FT
Figure 14. 8-bit typical application (two SRAM banks)
A[17:0]
I/O[7:0]
AT68166FT
A
D
TSC695F
A[27:0]
D[31:0]
D[31:24]
A[17:0]
A[17:0]
D[31:0]
I/O[15:8] D[31:24]
CS[0]
WE[0]
RWE0*
RAMS0*
CS[1]
WE[1]
RWE0*
RAMS1*
OE
RAMOE[1:0]*
CS[3]
WE[3]
RWE0*
RAMS2*
CS[2]
WE[2]
RWE0*
RAMS2*
I/O[23:16] D[31:24]
I/O[31:24] D[31:24]
16
7531H–AERO–04/09
AT68166FT
Ordering Information
Note: 1. Please contact your local sales office.
2. Will be replaced by SMD part number when available.
Part Number Temperature Range Speed Package Flow
AT68166FT
AT68166FT-YM25-E 25°C 25 ns MQFPT68 Engineering Samples
5962-0622901QXC -55° to +125°C 25 ns MQFPT68 QML Q
5962-0622901VXC -55° to +125°C 25 ns MQFPT68 QML V
5962R0622901VXC -55° to +125°C 25 ns MQFPT68 QML V RHA
AT68166FT-YM25-SCC -55° to +125°C 25 ns MQFPT68 ESCC
AT68166FT-YS20-E 25°C 20 ns MQFPT68 Engineering Samples
5962-0622903QYC -55° to +125°C 20 ns MQFPT68 QML Q
5962-0622903VYC -55° to +125°C 20 ns MQFPT68 QML V
5962R0622903VYC -55° to +125°C 20 ns MQFPT68 QML V RHA
AT68166FT-YS20-SCC(2) -55° to +125°C 20 ns MQFPT68 ESCC
AT68166FT-YS18-E(1) 25°C 18 ns MQFPT68 Engineering Samples
AT68166FT-YS18-MQ(1)(2) -55° to +125°C 18 ns MQFPT68 QML Q
AT68166FT-YS18-SV(1)(2) -55° to +125°C 18 ns MQFPT68 QML V
AT68166FT-YS18-SR(1)(2) -55° to +125°C 18 ns MQFPT68 QML V RHA
AT68166FT-YS18-SCC(1)(2) -55° to +125°C 18 ns MQFPT68 ESCC
17
7531H–AERO–04/09
AT68166FT
Package
Drawings
68-lead Quad Flat Pack (950 Mils) with non conductive tie bar
Note: Lid is connected to Ground.
Note: YM and YS package drawings are identical.
18
7531H–AERO–04/09
AT68166FT
Document Revision History
Changes from
Rev. C to Rev. D
1. Update of access time parameters.
Changes from
Rev. D to Rev. E
1. Added YS package.
Changes from
Rev. E to Rev. F
1. Updated ordering information.
Changes from
Rev. F to Rev. G
1. Split datasheet into two seperate documents: removed AT68166F from this document.
Please refer to document 7747 on the Atmel web site.
Changes from
Rev. G to Rev. H
1. Update of Absolute Maximum Ratings section
Printed on recycled paper.
7531H–AERO–04/09
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Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/SmartCards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi‐RelMPU/
HighSpeedConverters/RFDatacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
LiteratureRequests
www.atmel.com/literature
