PDM Digital Input, Mono 2.7 W Class-D Audio Amplifier SSM2537 Data Sheet FEATURES architecture enables extremely low real-world power consumption from digital audio sources with excellent audio performance. Using the SSM2537, audio can be transmitted digitally to the audio amplifier, significantly reducing the effect of noise sources such as GSM interference or other digital signals on the transmitted audio. The SSM2537 is capable of delivering 2.7 W of continuous output power with <1% THD + N driving a 4 load from a 5.0 V supply. Filterless digital Class-D amplifier Pulse density modulation (PDM) digital input interface 2.7 W into 4 load and 1.4 W into 8 load at 5.0 V supply with <1% total harmonic distortion plus noise (THD + N) Available in 9-ball, 1.2 mm x 1.2 mm, 0.4 mm pitch WLCSP 93% efficiency into 8 at full scale Output noise: 25 V rms at 3.6 V, A-weighted THD + N: 0.005% at 1 kHz, 100 mW output power PSRR: 80 dB at 217 Hz, with dither input Quiescent power consumption: 5.1 mW (VDD = 1.8 V, PVDD = 3.6 V, 8 + 33 H load) Pop-and-click suppression Configurable with PDM pattern inputs Short-circuit and thermal protection with autorecovery Smart power-down when PDM stop condition or no clock input detected 64 x fS or 128 x fS operation supporting 3 MHz and 6 MHz clocks DC blocking high-pass filter and static input dc protection User-selectable ultralow EMI emissions and low latency modes Power-on reset (POR) Minimal external passive components The SSM2537 features a high efficiency, low noise modulation scheme that requires no external LC output filters. The closed-loop, three-level modulator design retains the benefits of an all-digital amplifier, yet enables very good PSRR and audio performance. The modulation continues to provide high efficiency even at low output power and has an SNR of 102 dB PDM input. Spread-spectrum pulse density modulation is used to provide lower EMI-radiated emissions compared with other Class-D architectures. The SSM2537 has a four-state gain and sample frequency selection pin that can select two different gain settings, optimized for 3.6 V and 5 V operation. This same pin controls the internal digital filtering and clocking, which can be set for a 64 x fS or 128 x fS input sample rate to support both 3 MHz and 6 MHz PDM clock rates. The SSM2537 has a micropower shutdown mode with a typical shutdown current of 1.6 A for both power supplies. Shutdown is enabled automatically by gating input clock and data signals. A standby mode can be entered by applying a designated PDM stop condition sequence. The device also includes pop-and-click suppression circuitry. This suppression circuitry minimizes voltage glitches at the output when entering or leaving the low power state, reducing audible noises on activation and deactivation. APPLICATIONS Mobile handsets GENERAL DESCRIPTION The SSM2537 is a PDM digital input Class-D power amplifier that offers higher performance than existing DAC plus Class-D solutions. The SSM2537 is ideal for power sensitive applications where system noise can corrupt the small analog signal sent to the amplifier, such as mobile phones and portable media players. The SSM2537 is specified over the industrial temperature range of -40C to +85C. It has built-in thermal shutdown and output short-circuit protection. It is available in a 9-ball, 1.2 mm x 1.2 mm wafer level chip scale package (WLCSP). The SSM2537 combines an audio digital-to-analog converter (DAC), a power amplifier, and a PDM digital interface on a single chip. The integrated DAC plus analog sigma-delta (-) modulator FUNCTIONAL BLOCK DIAGRAM VDD POWER-ON RESET CLOCKING POWER CONTROL INPUT INTERFACE FILTERING/ DAC PDAT PVDD PGND SSM2537 - CLASS-D MODULATOR OUT+ FULL-BRIDGE POWER STAGE GAIN_FS LRSEL 10981-001 OUT- PCLK Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com SSM2537 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Master Clock ............................................................................... 13 Applications ....................................................................................... 1 Power Supplies ............................................................................ 13 General Description ......................................................................... 1 Power Control ............................................................................. 13 Functional Block Diagram .............................................................. 1 Power-On Reset/Voltage Supervisor ....................................... 13 Revision History ............................................................................... 2 System Gain/Input Frequency .................................................. 13 Specifications..................................................................................... 3 PDM Pattern Control ................................................................ 14 Digital Input/Output Specifications........................................... 4 EMI Noise.................................................................................... 14 PDM Interface Digital Timing Specifications .......................... 5 PDM Channel Selection ............................................................ 14 Absolute Maximum Ratings ............................................................ 6 Output Modulation Description .............................................. 14 Thermal Resistance ...................................................................... 6 Applications Information .............................................................. 15 ESD Caution .................................................................................. 6 Layout .......................................................................................... 15 Pin Configuration and Function Descriptions ............................. 7 Power Supply Decoupling ......................................................... 15 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 16 Theory of Operation ...................................................................... 13 Ordering Guide .......................................................................... 16 REVISION HISTORY 10/12--Revision 0: Initial Version Rev. 0 | Page 2 of 16 Data Sheet SSM2537 SPECIFICATIONS PVDD = 5.0 V, VDD = 1.8 V, fS = 128x, TA = 25C, RL = 8 + 33 H, unless otherwise noted. When fS = 128x, PDM clock = 6.144 MHz; when fS = 64x, PDM clock = 3.072 MHz. Table 1. Parameter DEVICE CHARACTERISTICS Output Power Total Harmonic Distortion Plus Noise Symbol Test Conditions/Comments PO f = 1 kHz, BW = 20 kHz RL = 4 , THD = 1%, PVDD = 5.0 V RL = 8 , THD = 1%, PVDD = 5.0 V RL = 4 , THD = 1%, PVDD = 3.6 V RL = 8 , THD = 1%, PVDD = 3.6 V RL = 4 , THD = 1%, PVDD = 2.5 V RL = 8 , THD = 1%, PVDD = 2.5 V RL = 4 , THD = 10%, PVDD = 5.0 V RL = 8 , THD = 10%, PVDD = 5.0 V RL = 4 , THD = 10%, PVDD = 3.6 V RL = 8 , THD = 10%, PVDD = 3.6 V RL = 4 , THD = 10%, PVDD = 2.5 V RL = 8 , THD = 10%, PVDD = 2.5 V f = 1 kHz PO = 100 mW into 8 , PVDD = 3.6 V PO = 500 mW into 8 , PVDD = 3.6 V PO = 1 W into 8 , PVDD = 5.0 V PO = 2 W into 4 , PVDD = 5.0 V PO = 1.4 W into 8 , PVDD = 5.0 V No input -6 dBFS PDM input, BTL output, f = 1 kHz Gain = 3.6 V Gain = 5.0 V Gain = 3.6 V THD + N Efficiency Average Switching Frequency Closed-Loop Gain fSW Gain Differential Output Offset Voltage Low Power Mode Wake Time Input Sampling Frequency VOOS tWAKE fS Propagation Delay tPD POWER SUPPLY Supply Voltage Range Amplifier Power Supply Digital Power Supply Power Supply Rejection Ratio Supply Current, H-Bridge Standby Current Power-Down Current PVDD VDD PSRR IPVDD fS = 64x fS = 128x fS = 6.144 MHz, normal operation fS = 6.144 MHz, low latency operation VRIPPLE = 100 mV at 100 Hz VRIPPLE = 100 mV at 1 kHz VRIPPLE = 100 mV at 10 kHz Dither input, 8 + 33 H load PVDD = 5.0 V, fS = 64x PVDD = 5.0 V, fS = 128x PVDD = 3.6 V, fS = 64x PVDD = 3.6 V, fS = 128x PVDD = 2.5 V, fS = 64x PVDD = 2.5 V, fS = 128x PVDD = 5.0 V Rev. 0 | Page 3 of 16 Min Typ Max Unit 2.7 1.4 1.35 0.75 0.62 0.35 3.38 1.8 1.7 0.93 0.78 0.44 W W W W W W W W W W W W 0.005 0.015 0.02 88 93 290 % % % % % kHz 3.5 4.78 0.5 VP VP mV ms MHz MHz s s 1.84 3.68 3.072 6.144 35 15 2.5 1.65 3.6 1.8 80 80 75 1.4 1.4 1.1 1.2 1.0 1.1 2.5 100 0.5 3.23 6.46 5.5 1.95 V V dB dB dB mA mA mA mA mA mA A nA SSM2537 Parameter Supply Current, Modulator Data Sheet Symbol IVDD Standby Current Shutdown Current NOISE PERFORMANCE Output Voltage Noise Signal-to-Noise Ratio en SNR Test Conditions/Comments Dither input, 8 + 33 H load VDD = 1.8 V, fS = 64x VDD = 1.8 V, fS = 128x VDD = 1.8 V, fS = 64x VDD = 1.8 V, fS = 128x VDD = 1.8 V Min Dither input, A-weighted PVDD = 3.6 V, fS = 64x PVDD = 3.6 V, fS = 128x PVDD = 5.0 V, fS = 64x PVDD = 5.0 V, fS = 128x PO = 1.4 W, PVDD = 5.0 V, RL = 8 , A-weighted fS = 64x fS = 128x DIGITAL INPUT/OUTPUT SPECIFICATIONS Table 2. Parameter INPUT SPECIFICATIONS Input Voltage High PCLK, PDAT, LRSEL Pins Input Voltage Low PCLK, PDAT, LRSEL Pins Input Leakage Current High PDAT, LRSEL Pins PCLK Pin Input Leakage Current Low PDAT, LRSEL Pins PCLK Pin Input Capacitance Symbol Min Typ Max Unit 0.7 x VDD 3.6 -0.3 0.3 x VDD V V V 1 3 A A 1 3 5 A A pF VIH VIL IIH IIL Rev. 0 | Page 4 of 16 Typ Max Unit 0.3 0.6 37 68 1.6 mA mA A A A 25 27 33 30 V V V V 102 102 dB dB Data Sheet SSM2537 PDM INTERFACE DIGITAL TIMING SPECIFICATIONS Table 3. Parameter tCF tCR tDS tDH tMIN 10 7 Limit tMAX 10 10 7 Unit ns ns ns ns Description Clock fall time Clock rise time Data setup time Data hold time Timing Diagram PCLK PDAT LEFT DATA RIGHT DATA LEFT DATA Figure 2. PDM Interface Timing Rev. 0 | Page 5 of 16 RIGHT DATA 10981-002 tDS tDH SSM2537 Data Sheet ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25C, unless otherwise noted. Junction-to-air thermal resistance (JA) is specified for the worstcase conditions, that is, a device soldered in a printed circuit board (PCB) for surface-mount packages. JA is determined according to JEDEC JESD51-9 on a 4-layer PCB with natural convection cooling. Table 4. Parameter PVDD Supply Voltage VDD Supply Voltage Input Voltage (Signal Source) ESD Susceptibility OUT- and OUT+ Pins Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) THERMAL RESISTANCE Rating -0.3 V to +6 V -0.3 V to +2 V -0.3 V to +2 V 4 kV 8 kV -65C to +150C -40C to +85C -65C to +165C 300C Table 5. Thermal Resistance Package Type 9-Ball, 1.2 mm x 1.2 mm WLCSP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 6 of 16 PCB 2S0P JA 88 Unit C/W Data Sheet SSM2537 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 CORNER 1 2 3 PDAT LRSEL OUT- VDD PVDD PGND PCLK GAIN_FS OUT+ A B TOP VIEW (BALL SIDE DOWN) Not to Scale 10981-003 C Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. A1 A2 A3 B1 B2 B3 C1 C2 C3 Mnemonic PDAT LRSEL OUT- VDD PVDD PGND PCLK GAIN_FS OUT+ Function Input Input Output Supply Supply Ground Input Input Output Description PDM Data Signal. Left/Right Channel Select. Tie to ground for left channel; pull up to VDD for right channel. Inverting Output. Digital Power, 1.8 V. Amplifier Power, 2.5 V to 5.5 V. Amplifier Ground. PDM Interface Master Clock. Gain and Sample Rate Selection Pin. (Connect to PVDD for typical operation.) Noninverting Output. Rev. 0 | Page 7 of 16 SSM2537 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 100 RL = 8 + 33H fS = 64x 10 1 THD + N (%) 10 THD + N (%) RL = 4 + 15H fS = 128x PVDD = 2.5V 0.1 0.01 PVDD = 2.5V 1 0.1 0.01 PVDD = 5V PVDD = 5V PVDD = 3.6V PVDD = 3.6V 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 0.001 10981-007 0.001 0.001 0.1 1 10 OUTPUT POWER (W) Figure 4. THD + N vs. Output Power into 8 , Gain = 5 V, fS = 64x Figure 7. THD + N vs. Output Power into 4 , Gain = 5 V, fS = 128x 100 100 RL = 8 + 33H fS = 128x RL = 8 + 33H PVDD = 5V fS = 64x 10 1 THD + N (%) 10 THD + N (%) 0.01 10981-010 100 PVDD = 2.5V 0.1 1 0.1 1W 0.25W 0.01 PVDD = 5V PVDD = 3.6V 0.01 0.1 1 0.5W 10 OUTPUT POWER (W) 0.001 10 10981-008 100 RL = 4 + 15H fS = 64x 100k RL = 8 + 33H PVDD = 3.6V fS = 64x THD + N (%) 10 1 PVDD = 2.5V 0.1 1 0.1 0.25W 0.01 0.5W 0.01 PVDD = 5V 0.01 0.1 1 10 OUTPUT POWER (W) 10981-009 PVDD = 3.6V 0.001 0.001 10k Figure 8. THD + N vs. Frequency, PVDD = 5 V, RL = 8 , fS = 64x 10 THD + N (%) 1k FREQUENCY (Hz) Figure 5. THD + N vs. Output Power into 8 , Gain = 5 V, fS = 128x 100 100 Figure 6. THD + N vs. Output Power into 4 , Gain = 5 V, fS = 64x 0.001 10 0.125W 100 1k 10k 100k FREQUENCY (Hz) Figure 9. THD + N vs. Frequency, PVDD = 3.6 V, RL = 8 , fS = 64x Rev. 0 | Page 8 of 16 10981-011 0.001 0.001 10981-012 0.01 Data Sheet 100 SSM2537 100 RL = 8 + 33H PVDD = 2.5V fS = 64x 10 THD + N (%) THD + N (%) 10 RL = 4 + 15H PVDD = 2.5V fS = 64x 1 0.1 1 0.1 0.5W 0.25W 0.0625W 0.125W 0.01 0.01 0.25W 1k 10k 100k FREQUENCY (Hz) 10981-013 100 0.001 10 1k 10k 100k FREQUENCY (Hz) Figure 10. THD + N vs. Frequency, PVDD = 2.5 V, RL = 8 , fS = 64x Figure 13. THD + N vs. Frequency, PVDD = 2.5 V, RL = 4 , fS = 64x 100 100 RL = 4 + 15H PVDD = 5V fS = 64x RL = 8 + 33H PVDD = 5V fS = 128x 10 THD + N (%) 10 THD + N (%) 100 10981-016 0.125W 0.001 10 1 0.1 2W 0.5W 1 0.1 1W 0.25W 0.01 0.01 1W 1k 10k 100k FREQUENCY (Hz) 0.001 10 10981-014 100 1k 10k 100k FREQUENCY (Hz) Figure 11. THD + N vs. Frequency, PVDD = 5 V, RL = 4 , fS = 64x Figure 14. THD + N vs. Frequency, PVDD = 5 V, RL = 8 , fS = 128x 100 100 RL = 4 + 15H PVDD = 3.6V fS = 64x THD + N (%) 1 0.1 RL = 8 + 33H PVDD = 3.6V fS = 128x 10 10 THD + N (%) 100 10981-017 0.5W 0.001 10 1W 1 0.1 0.5W 0.25W 0.25W 0.01 100 1k 10k 100k FREQUENCY (Hz) 10981-015 0.5W 0.001 10 0.001 10 0.125W 100 1k 10k 100k FREQUENCY (Hz) Figure 15. THD + N vs. Frequency, PVDD = 3.6 V, RL = 8 , fS = 128x Figure 12. THD + N vs. Frequency, PVDD = 3.6 V, RL = 4 , fS = 64x Rev. 0 | Page 9 of 16 10981-018 0.01 SSM2537 100 RL = 8 + 33H PVDD = 2.5V fS = 128x 10 THD + N (%) 10 1 0.1 1 0.1 0.5W 0.25W 0.01 0.01 0.0625W 100 0.125W 1k 10k 100k FREQUENCY (Hz) 100k fS = 64x 1.9 1.8 SUPPLY CURRENT (mA) THD + N (%) 10k 2.0 RL = 4 + 15H PVDD = 5V fS = 128x 1 0.1 2W 0.01 1.7 1.6 8 + 33H 1.5 1.4 4 + 15H 1.3 NO LOAD 1.2 0.001 10 100 1.1 1W 1k 10k 100k FREQUENCY (Hz) 1.0 2.5 10981-020 0.5W 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) Figure 17. THD + N vs. Frequency, PVDD = 5 V, RL = 4 , fS = 128x Figure 20. Quiescent Current vs. Supply Voltage, fS = 64x 2.0 fS = 128x RL = 4 + 15H PVDD = 3.6V fS = 128x 1.9 1.8 SUPPLY CURRENT (mA) 10 THD + N (%) 1k Figure 19. THD + N vs. Frequency, PVDD = 2.5 V, RL = 4 , fS = 128x 10 100 100 FREQUENCY (Hz) Figure 16. THD + N vs. Frequency, PVDD = 2.5 V, RL = 8 , fS = 128x 100 0.125W 0.25W 0.001 10 10981-019 0.001 10 10981-022 THD + N (%) RL = 4 + 15H PVDD = 2.5V fS = 128x 10981-024 100 Data Sheet 1 0.1 1W 1.7 1.6 1.5 8 + 33H 1.4 NO LOAD 1.3 1.2 0.01 4 + 15H 0.25W 100 0.5W 1k 10k 100k FREQUENCY (Hz) 10981-021 0.001 10 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) Figure 21. Quiescent Current vs. Supply Voltage, fS = 128x Figure 18. THD + N vs. Frequency, PVDD = 3.6 V, RL = 4 , fS = 128x Rev. 0 | Page 10 of 16 10981-118 1.1 Data Sheet SSM2537 4.0 2.0 RL = 8 + 33H 1.8 fS = 64x RL = 4 + 15H fS = 128x 3.5 1.6 OUTPUT POWER (W) OUTPUT POWER (W) 3.0 1.4 1.2 1.0 THD = 10% 0.8 THD = 1% 0.6 2.5 2.0 THD = 10% 1.5 THD = 1% 1.0 0.4 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 0 2.5 10981-025 0 2.5 Figure 22. Maximum Output Power vs. Supply Voltage, RL = 8 , fS = 64x 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 10981-028 0.5 0.2 Figure 25. Maximum Output Power vs. Supply Voltage, RL = 4 , fS = 128x 2.0 100 RL = 8 + 33H 1.8 fS = 128x 90 1.6 PVDD = 5V PVDD = 3.6V 80 1.4 1.0 THD = 10% 0.8 THD = 1% 60 50 40 0.6 30 0.4 20 0.2 10 0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 0 RL = 8 + 33 fS = 64x 0 3.5 0.6 1.0 0.8 1.6 1.4 1.2 2.0 1.8 Figure 26. Efficiency vs. Output Power into 8 , fS = 64x 100 RL = 4 + 15H fS = 64x 90 80 PVDD = 2.5V 3.0 PVDD = 3.6V PVDD = 5V 70 EFFICIENCY (%) OUTPUT POWER (W) 0.4 OUTPUT POWER (W) Figure 23. Maximum Output Power vs. Supply Voltage, RL = 8 , fS = 128x 4.0 0.2 10981-023 EFFICIENCY (%) 70 1.2 10981-026 OUTPUT POWER (W) PVDD = 2.5V 2.5 THD = 10% 2.0 THD = 1% 1.5 60 50 40 30 1.0 20 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 4.5 5.0 10981-027 0 2.5 RL = 8 + 33 fS = 128x 10 Figure 24. Maximum Output Power vs. Supply Voltage, RL = 4 , fS = 64x Rev. 0 | Page 11 of 16 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT POWER (W) Figure 27. Efficiency vs. Output Power into 8 , fS = 128x 10981-030 0.5 SSM2537 Data Sheet 100 90 80 PVDD = 5V PVDD = 3.6V PVDD = 2.5V EFFICIENCY (%) 70 60 50 40 30 20 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 0 OUTPUT POWER (W) -20 -30 -40 -50 -60 -70 -80 -90 10 10981-032 0 RL = 4 + 15 fS = 64x -10 100 1k 10k 100k FREQUENCY (Hz) Figure 28. Efficiency vs. Output Power into 4 , fS = 64x 10981-035 POWER SUPPLY REJECTION RATIO (dB) 0 Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency 100 3 90 2 PCLK 80 PVDD = 5V PVDD = 3.6V 1 VOLTAGE (V) EFFICIENCY (%) 70 60 50 PVDD = 2.5V 40 0 OUTPUT -1 -2 30 -3 20 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 OUTPUT POWER (W) -20 RL = 8 + 33H PVDD = 5V fS = 128x -60 -80 -100 -120 -140 100 1k 10k FREQUENCY (Hz) 100k 10981-034 AMPLITUDE (dBV) -40 -160 10 -0.2 0 0.2 0.4 0.6 0.8 1.0 TIME (ms) Figure 32. Turn-On Response Figure 29. Efficiency vs. Output Power into 4 , fS = 128x 0 -5 -0.4 Figure 30. Output Spectrum vs. Frequency Rev. 0 | Page 12 of 16 1.2 1.4 1.6 10981-036 0 10981-033 0 -4 RL = 4 + 15 fS = 128x 10 Data Sheet SSM2537 THEORY OF OPERATION MASTER CLOCK POWER-ON RESET/VOLTAGE SUPERVISOR The SSM2537 requires a clock present at the PCLK input pin to operate. This clock must be fully synchronous with the incoming digital audio on the serial interface. Clock frequencies must fall into one of these ranges: 1.84 MHz to 3.23 MHz or 3.68 MHz to 6.46 MHz. The SSM2537 includes an internal power-on reset and voltage supervisor circuit. This circuit provides an internal reset to BMMcircuitry when PVDD or VDD is substantially below the nominal operating threshold. This simplifies supply sequencing during initial power-on. POWER SUPPLIES The circuit also monitors the power supplies to the IC. If the supply voltages fall below the nominal operating threshold, this circuit stops the output and issues a reset. This is done to ensure that no damage occurs due to low voltage operation and that no pops can occur under nearly any power removal condition. The SSM2537 requires two power supplies: PVDD and VDD. PVDD PVDD supplies power to the full-bridge power stage of the MOSFET and its associated drive, control, and protection circuitry. It also supplies power to the digital-to-analog converter (DAC) and to the Class-D PDM modulator. PVDD can operate from 2.5 V to 5.5 V and must be present to obtain audio output. Lowering the supply voltage of PVDD results in lower maximum output power and, therefore, lower power consumption. VDD VDD provides power to the digital logic circuitry. VDD can operate from 1.65 V to 1.95 V and must be present to obtain audio output. Lowering the supply voltage of VDD results in lower power consumption but does not affect audio performance. POWER CONTROL On device power-up, PVDD must first be applied to the device, which latches in the designated GAIN_FS pin functionality. The SSM2537 contains a smart power-down feature. When enabled, the smart power-down feature looks at the incoming digital audio and, if it receives the PDM stop condition of at least 129 repeated 0xAC bytes (1024 clock cycles), it places the SSM2537 in standby mode. In standby mode, PCLK can be removed, resulting in a full power-down state. This state is the lowest power condition possible. When PCLK is turned on again and a single non-stop condition input is received, the SSM2537 leaves the full power-down state and resumes normal operation under the default setting as indicated by the GAIN_FS pin state. SYSTEM GAIN/INPUT FREQUENCY The GAIN_FS pin is used to set the internal gain and filtering configuration for different sample rates of the SSM2537. This pin can be set to one of four states by connecting the pin either to PVDD or to PGND with or without a 47 k resistor (see Table 7). The internal gain and filtering can also be set via PDM pattern control, allowing these settings to be modified during operation (see the PDM Pattern Control section). The SSM2537 has an internal analog gain control such that when GAIN_FS is tied to PGND or PVDD via a 47 k resistor (5 V gain setting), a -6.02 dBFS PDM input signal results in an amplifier output voltage of 5 V peak. This setting should produce optimal noise performance when PVDD is 5 V. When the GAIN_FS pin is tied to PVDD or pulled directly to PGND, the gain is adjusted so that a -6.02 dBFS PDM input signal results in an amplifier output voltage of 3.6 V peak. This setting should produce optimal noise performance when PVDD is 3.6 V. The SSM2537 can handle input sample rates of 64 x fS (~3 MHz) and 128 x fS (~6 MHz). Different internal digital filtering is used in each of these cases. Selection of the sample rate is also set via the GAIN_FS pin (see Table 7). Because the 64 x fS mode provides better performance with lower power consumption, its use is recommended. The 128 x fS mode should be used only when overall system noise performance is limited by the source modulator. Table 7. GAIN_FS Function Descriptions Device Setting fS = 128 x PCLK, Gain = 5 V fS = 64 x PCLK, Gain = 5 V fS = 128 x PCLK, Gain = 3.6 V fS = 64 x PCLK, Gain = 3.6 V Rev. 0 | Page 13 of 16 GAIN_FS Pin Configuration Pull up to PVDD with a 47 k resistor Pull down to PGND with a 47 k resistor Pull up to PVDD Pull down to PGND SSM2537 Data Sheet PDM PATTERN CONTROL OUTPUT MODULATION DESCRIPTION The SSM2537 has a simple control mechanism that can set the part for low power states and control functionality. This is accomplished by sending a repeating 8-bit pattern to the device. Different patterns set different functionality (see Table 8). The SSM2537 uses three-level, - output modulation. Each output can swing from PGND to PVDD and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, there are always noise sources present. Any pattern must be repeated a minimum of 129 times. The part is automatically muted when a pattern is detected so that a pattern can be set while the part is operational without a pop/click due to pattern transition. All functionality set via patterns returns to its default values after a clock-loss power-down. Table 8. PDM Watermarking Pattern Control Descriptions Pattern 0xD2 0xD4 0xD8 0xE1 0xE2 0xE4 0xAA 0x66 0xAC Control Description Gain optimized for PVDD = 3.6 V operation. Gain optimized for PVDD = 2.5 V operation. Gain optimized for PVDD = 5 V operation. Ultralow EMI mode. Low latency mode with pattern delay (~15 s latency). fS set to opposite value determined by GAIN_FS pin. Device reset: Place device into default configuration. Mute. Power-down: All blocks off except for PDM interface. Normal start-up time. Due to this constant presence of noise, a differential pulse is generated, when required, in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. Most of the time, however, the output differential voltage is 0 V, due to the Analog Devices, Inc., three-level, - output modulation. This feature ensures that the current flowing through the inductive load is small. When the user wants to send an input signal, an output pulse (OUT+ and OUT-) is generated to follow the input voltage. The differential pulse density (VOUT) is increased by raising the input signal level. Figure 33 depicts three-level, - output modulation with and without input stimulus. OUTPUT = 0V +5V OUT+ 0V +5V OUT- 0V +5V VOUT EMI NOISE 0V -5V The SSM2537 uses a proprietary modulation and spreadspectrum technology to minimize EMI emissions from the device. For applications that have difficulty passing FCC Class B emission tests, the SSM2537 includes a modulation select mode (ultralow EMI emissions mode) that significantly reduces the radiated emissions at the Class-D outputs, particularly above 100 MHz. This mode is enabled by activating PDM Watermarking Pattern 0xE1 (see Table 8). OUTPUT > 0V +5V OUT+ 0V +5V OUT- 0V +5V VOUT 0V OUTPUT < 0V +5V OUT+ 0V +5V PDM CHANNEL SELECTION OUT- The SSM2537 includes a left/right input select pin, LRSEL (see Table 9), that determines which of the time-multiplexed input streams is routed to the amplifier. To select the left input channel, connect LRSEL to PGND. To select the right channel, connect LRSEL to VDD. At any point during amplifier operation, the logic level applied to LRSEL may be changed and the output will switch the input streams without audible artifacts. No muting, watermarking pattern or synchronizing are necessary to achieve a click/pop free LRSEL transition. VOUT 0V -5V Figure 33. Three-Level, - Output Modulation With and Without Input Stimulus Table 9. LRSEL Pin Function Descriptions Device Setting Right Channel Select Left Channel Select 10981-006 0V LRSEL Pin Configuration VDD PGND Rev. 0 | Page 14 of 16 Data Sheet SSM2537 APPLICATIONS INFORMATION LAYOUT As output power increases, take care to lay out PCB traces and wires properly among the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Avoid ground loops where possible to minimize common-mode current associated with separate paths to ground. Ensure that track widths are at least 200 mil per inch of track length for the lowest DCR, and use 1 oz or 2 oz copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding helps to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load, as well as the PCB traces to the supply pins, should be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. Properly designed multilayer PCBs can reduce EMI emissions and increase immunity to the RF field by a factor of 10 or more, compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input must be decoupled with a good quality, low ESL, low ESR capacitor, with a minimum value of 4.7 F. This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, use a 0.1 F capacitor as close as possible to the PVDD and VDD pins of the device. Placing the decoupling capacitors as close as possible to the SSM2537 helps to maintain efficient performance. In addition, good PCB layout isolates critical analog paths from sources of high interference. Separate high frequency circuits (analog and digital) from low frequency circuits. Rev. 0 | Page 15 of 16 SSM2537 Data Sheet OUTLINE DIMENSIONS 1.240 1.200 SQ 1.160 3 2 1 A BALL A1 IDENTIFIER 0.80 REF B C 0.40 REF BOTTOM VIEW (BALL SIDE UP) TOP VIEW (BALL SIDE DOWN) 0.560 0.500 0.440 0.80 REF END VIEW SEATING PLANE 0.300 0.260 0.220 0.230 0.200 0.170 06-25-2012-A COPLANARITY 0.05 Figure 34. 9-Ball Wafer Level Chip Scale Package [WLCSP] (CB-9-5) Dimensions shown in millimeters ORDERING GUIDE Model1 SSM2537ACBZ-R7 SSM2537ACBZ-RL EVAL-SSM2537Z 1 Temperature Range -40C to +85C -40C to +85C Package Description 9-Ball Wafer Level Chip Scale Package [WLCSP] 9-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. (c)2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10981-0-10/12(0) Rev. 0 | Page 16 of 16 Package Option CB-9-5 CB-9-5 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: EVAL-SSM2537Z SSM2537ACBZ-R7 SSM2537ACBZ-RL