74LVC1G32GM-H - NXP Semiconductors / Philips Semiconductors

1. General description

The 74LVC1G32 provides one 2-input OR function.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in mixed 3.3 V and 5 V applications.

Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall

time.

This device is fully speciﬁed for partial power-down applications using IOFF.

The IOFF circuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

2. Features

■Wide supply voltage range from 1.65 V to 5.5 V

■High noise immunity

■Complies with JEDEC standard:

◆JESD8-7 (1.65 V to 1.95 V)

◆JESD8-5 (2.3 V to 2.7 V)

◆JESD8-B/JESD36 (2.7 V to 3.6 V)

■±24 mA output drive (VCC = 3.0 V)

■CMOS low power consumption

■Latch-up performance exceeds 250 mA

■Direct interface with TTL levels

■Inputs accept voltages up to 5 V

■ESD protection:

◆HBM JESD22-A114E exceeds 2000 V

◆MM JESD22-A115-A exceeds 200 V

■Multiple package options

■Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

74LVC1G32

Single 2-input OR gate

Rev. 06 — 2 August 2007 Product data sheet

Product data sheet Rev. 06 — 2 August 2007 2 of 14

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

3. Ordering information

4. Marking

5. Functional diagram

Table 1. Ordering information

Type number Package

Temperature

range Name Description Version

74LVC1G32GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads;

body width 1.25 mm SOT353-1

74LVC1G32GV −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753

74LVC1G32GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package;

no leads; 6 terminals; body 1 ×1.45 ×0.5 mm SOT886

74LVC1G32GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package;

no leads; 6 terminals; body 1 ×1×0.5 mm SOT891

Table 2. Marking

Type number Marking code

74LVC1G32GW VG

74LVC1G32GV V32

74LVC1G32GM VG

74LVC1G32GF VG

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram

mna164

mna165

≥1

mna166

Product data sheet Rev. 06 — 2 August 2007 3 of 14

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

[1] H = HIGH voltage level; L = LOW voltage level

Fig 4. Pin conﬁguration SOT353-1

and SOT753 Fig 5. Pin conﬁguration SOT886 Fig 6. Pin conﬁguration SOT891

74LVC1G32

GND Y

001aab640

74LVC1G32

001aab641

GND

n.c.

VCC

Transparent top view

674LVC1G32

001aaf000

GND

n.c.

VCC

Transparent top view

Table 3. Pin description

Symbol Pin Description

SOT353-1/SOT753 SOT886/SOT891

B 1 1 data input

A 2 2 data input

GND 3 3 ground (0 V)

Y 4 4 data output

n.c. - 5 not connected

VCC 5 6 supply voltage

Table 4. Function table[1]

Input Output

ABY

LLL

LHH

HLH

HHH

Product data sheet Rev. 06 — 2 August 2007 4 of 14

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

8. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

[3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.

For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.

9. Recommended operating conditions

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +6.5 V

IIK input clamping current VI < 0 V −50 - mA

VIinput voltage [1] −0.5 +6.5 V

IOK output clamping current VO > VCC or VO < 0 V - ±50 mA

VOoutput voltage Active mode [1][2] −0.5 VCC + 0.5 V

Power-down mode [1][2] −0.5 +6.5 V

IOoutput current VO = 0 V to VCC -±50 mA

ICC supply current - 100 mA

IGND ground current −100 - mA

Ptot total power dissipation Tamb =−40 °C to +125 °C[3] - 250 mW

Tstg storage temperature −65 +150 °C

Table 6. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 1.65 - 5.5 V

VIinput voltage 0 - 5.5 V

VOoutput voltage Active mode 0 - VCC V

VCC = 0 V; Power-down mode 0 - 5.5 V

Tamb ambient temperature −40 - +125 °C

∆t/∆V input transition rise and fall rate VCC = 1.65 V to 2.7 V - - 20 ns/V

VCC = 2.7 V to 5.5 V - - 10 ns/V

Product data sheet Rev. 06 — 2 August 2007 5 of 14

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

10. Static characteristics

[1] All typical values are measured at VCC = 3.3 V and Tamb =25°C.

Table 7. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

VIH HIGH-level

input voltage VCC = 1.65 V to 1.95 V 0.65VCC - - 0.65VCC -V

VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V

VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V

VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC -V

VIL LOW-level

input voltage VCC = 1.65 V to 1.95 V - - 0.35VCC - 0.35VCC V

VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V

VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V

VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V

VOH HIGH-level

output voltage VI=V

IH or VIL

IO=−100 µA;

VCC = 1.65 V to 5.5 V VCC −0.1 - - VCC −0.1 - V

IO=−4 mA; VCC = 1.65 V 1.2 - - 0.95 - V

IO=−8 mA; VCC = 2.3 V 1.9 - - 1.7 - V

IO=−12 mA; VCC = 2.7 V 2.2 - - 1.9 - V

IO=−24 mA; VCC = 3.0 V 2.3 - - 2.0 - V

IO=−32 mA; VCC = 4.5 V 3.8 - - 3.4 - V

VOL LOW-level

output voltage VI=V

IH or VIL

IO= 100 µA;

VCC = 1.65 V to 5.5 V - - 0.10 - 0.10 V

IO= 4 mA; VCC = 1.65 V - - 0.45 - 0.70 V

IO= 8 mA; VCC = 2.3 V - - 0.30 - 0.45 V

IO= 12 mA; VCC = 2.7 V - - 0.40 - 0.60 V

IO= 24 mA; VCC = 3.0 V - - 0.55 - 0.80 V

IO= 32 mA; VCC = 4.5 V - - 0.55 - 0.80 V

IIinput leakage

current VI = 5.5 V or GND;

VCC = 0 V to 5.5 V -±0.1 ±5-±100 µA

IOFF power-off

leakage

current

VCC = 0 V; VIor VO= 5.5 V - ±0.1 ±10 - ±200 µA

ICC supply current VI = 5.5 V or GND; IO = 0 A;

VCC = 1.65 V to 5.5 V - 0.1 10 - 200 µA

∆ICC additional

supply current per pin; VCC = 2.3 V to 5.5 V;

VI=V

CC −0.6 V; IO=0 A - 5 500 - 5000 µA

CIinput

capacitance VCC = 3.3 V; VI = GND to VCC -5---pF

Product data sheet Rev. 06 — 2 August 2007 6 of 14

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

11. Dynamic characteristics

[1] Typical values are measured at Tamb =25°C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.

[2] tpd is the same as tPLH and tPHL.

[3] CPD is used to determine the dynamic power dissipation (PDin µW).

PD=(C

PD ×VCC2×fi×N) + (CL×VCC2×fo) where:

VCC = supply voltage in V,

fi= input frequency in MHz,

N = number of inputs switching,

CL= output load capacitance in pF,

fo= output frequency in MHz.

12. AC waveforms

Table 8. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 8.

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

tpd propagation delay A, B to Y; see Figure 7 [2]

VCC = 1.65 V to 1.95 V 1.0 3.1 8.0 1.0 10.5 ns

VCC = 2.3 V to 2.7 V 0.5 2.1 5.5 0.5 7.0 ns

VCC = 2.7 V 0.5 2.5 5.5 0.5 7.0 ns

VCC = 3.0 V to 3.6 V 0.5 2.1 4.5 0.5 6.0 ns

VCC = 4.5 V to 5.5 V 0.5 1.7 4.0 0.5 5.5 ns

CPD power dissipation

capacitance VI = GND to VCC; VCC = 3.3 V [3] -16- - -pF

Measurement points are given in Table 9.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 7. The input A, B to output Y propagation delays

mna615

tPHL tPLH

A, B input

Y output

GND

VOH

VOL

Product data sheet Rev. 06 — 2 August 2007 7 of 14

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

Table 9. Measurement points

Supply voltage Input Output

VCC VMVM

1.65 V to 1.95 V 0.5VCC 0.5VCC

2.3 V to 2.7 V 0.5VCC 0.5VCC

2.7 V 1.5 V 1.5 V

3.0 V to 3.6 V 1.5 V 1.5 V

4.5 V to 5.5 V 0.5VCC 0.5VCC

Test data is given in Table 10.

Deﬁnitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance; should be equal to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 8. Load circuitry for switching times

VEXT

VCC

VIVO

mna616

DUT

Table 10. Test data

Supply voltage Input Load VEXT

VCC VItr=t

fCLRLtPLH, tPHL

1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩopen

2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ωopen

2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ωopen

3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ωopen

4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ωopen

Product data sheet Rev. 06 — 2 August 2007 8 of 14

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

13. Package outline

Fig 9. Package outline SOT353-1 (TSSOP5)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(1) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.1

01.0

0.8 0.30

0.15 0.25

0.08 2.25

1.85 1.35

1.15 0.65

1.3 2.25

2.0 0.60

0.15 7°

0°

0.1 0.10.30.425

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

0.46

0.21

SOT353-1 MO-203 SC-88A 00-09-01

03-02-19

0.15

(A3)

detail X

vMA

1.5 3 mm0

scale

TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1

1.1

Product data sheet Rev. 06 — 2 August 2007 9 of 14

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

Fig 10. Package outline SOT753 (SC-74A)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT753 SC-74A

wBM

detail X

vMA

0 1 2 mm

scale

132

Plastic surface-mounted package; 5 leads SOT753

UNIT A1bpcDEHELpQywv

mm 0.100

0.013 0.40

0.25 3.1

2.7

0.26

0.10 1.7

1.3

0.95 3.0

2.5 0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.6

0.2 0.33

0.23

1.1

0.9

02-04-16

06-03-16

Product data sheet Rev. 06 — 2 August 2007 10 of 14

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

Fig 11. Package outline SOT886 (XSON6)

terminal 1

index area

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT886 MO-252

SOT886

04-07-15

04-07-22

DIMENSIONS (mm are the original dimensions)

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm

0 1 2 mm

scale

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

UNIT

mm 0.25

0.17 1.5

1.4 0.35

0.27

max b E

1.05

0.95

Dee

0.40

0.32

0.50.6

A(1)

max

0.5 0.04

6×

(2)

4×

(2)

Product data sheet Rev. 06 — 2 August 2007 11 of 14

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

Fig 12. Package outline SOT891 (XSON6)

terminal 1

index area

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT891

05-04-06

07-05-15

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

mm 0.20

0.12 1.05

0.95 0.35

0.27

max b E

1.05

0.95

Dee

0.40

0.32

0.350.55

max

0.5 0.04

6×

(1)

4×

(1)

Note

1. Can be visible in some manufacturing processes.

Product data sheet Rev. 06 — 2 August 2007 12 of 14

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

14. Abbreviations

15. Revision history

Table 11. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVC1G32_6 20070802 Product data sheet - 74LVC1G32_5

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

•Section 10 “Static characteristics”:

Changed: Conditions for input leakage current and supply current.

•New package outline drawing for XSON6/SOT891.

74LVC1G32_5 20060619 Product data sheet - 74LVC1G32_4

74LVC1G32_4 20040915 Product speciﬁcation - 74LVC1G32_3

74LVC1G32_3 20021115 Product speciﬁcation - 74LVC1G32_2

74LVC1G32_2 20020521 Product speciﬁcation - 74LVC1G32_1

74LVC1G32_1 20001121 Product speciﬁcation - -

Product data sheet Rev. 06 — 2 August 2007 13 of 14

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74LVC1G32

Single 2-input OR gate

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 August 2007

Document identifier: 74LVC1G32_6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 3

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

9 Recommended operating conditions. . . . . . . . 4

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

12 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 6

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13

16.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

17 Contact information. . . . . . . . . . . . . . . . . . . . . 13

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14