MPC9456FAR2 - Motorola / Freescale Semiconductor

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA Order Number: MPC9456/D

Rev 1, 03/2002

 Motorola, Inc. 2002

2.5V and 3.3V LVCMOS Clock

Fanout Buffer

The MPC9456 is a 2.5V and 3.3V compatible 1:10 clock distribution

buffer designed for low-voltage mid-range to high-performance telecom,

networking and computing applications. Both 3.3V, 2.5V and dual supply

voltages are supported for mixed-voltage applications. The MPC9456

offers 10 low-skew outputs and a differential LVPECL clock input. The

outputs are configurable and support 1:1 and 1:2 output to input

frequency ratios. The MPC9456 is specified for the extended temperature

range of –40 to 85°C.

Features

•Configurable 10 outputs LVCMOS clock distribution buffer

•Compatible to single, dual and mixed 3.3V/2.5V voltage supply

•Wide range output clock frequency up to 250 MHz

•Designed for mid-range to high-performance telecom, networking and

computer applications

•Supports high-performance differential clocking applications

•Max. output skew of 200 ps (150 ps within one bank)

•Selectable output configurations per output bank

•Tristable outputs

•32 ld LQFP package

•Ambient operating temperature range of –40 to 85°C

Functional Description

The MPC9456 is a full static design supporting clock frequencies up to

250 MHz. The signals are generated and retimed on-chip to ensure

minimal skew between the three output banks.

Each of the three output banks can be individually supplied by 2.5V or 3.3V supporting mixed voltage applications. The FSELx

pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for

each of the three output banks. The MPC9456 can be reset and the outputs are disabled by deasserting the MR/OE pin (logic

high state). Asserting MR/OE will enable the outputs.

All control inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive

terminated 50 Ω transmission lines. The clock input is low voltage PECL compatible for differential clock distribution support.

Please consult the MPC9446 specification for a full CMOS compatible device. For series terminated transmission lines, each of

the MPC9456 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7

mm2 32-lead LQFP package.

FA SUFFIX

LQFP PACKAGE

CASE 873A–02

MPC9456

LOW VOLTAGE SINGLE OR

DUAL SUPPLY 2.5V AND 3.3V

LVCMOS CLOCK

DISTRIBUTION BUFFER

MPC9456

MOTOROLA TIMING SOLUTIONS2

Figure 1. MPC9456 Logic Diagram

VCCA

QA2

GND

QA1

VCCA

QA0

GND

QC3

GND

QC2

VCCC

QC1

GND

QB0

VCCB

QB1

GND

QB2

VCCB

VCCC

VCC

PECL_CLK

FSELA

FSELB

FSELC

GND

12345678

24 23 22 21 20 19 18 17 16

MPC9456

VCCB is internally connected to VCC

Figure 2. Pinout: 32–Lead Package Pinout (Top View)

MR/OE

QC0

VCCC

CLK ÷ 2

MR/OE

PCLK

FSELA

FSELB

FSELC

QA0

QA1

QA2

QB0

QB1

QB2

QC0

QC1

QC2

QC3

CLK Bank A

Bank B

Bank C

25k

25k VCC/2

MPC9456

TIMING SOLUTIONS 3 MOTOROLA

Table 1: Pin Configuration

Pin I/O Type Function

PECL_CLK,

PECL_CLK Input LVPECL Differential clock reference

Low voltage positive ECL input

FSELA, FSELB, FSELCInput LVCMOS Output bank divide select input

MR/OE Input LVCMOS Internal reset and output tristate control

GND Supply Negative voltage supply output bank (GND)

VCCA, VCCB*, VCCC Supply Positive voltage supply for output banks

VCC Supply Positive voltage supply core (VCC)

QA0 - QA2 Output LVCMOS Bank A outputs

QB0 - QB2 Output LVCMOS Bank B outputs

QC0 - QC3 Output LVCMOS Bank C outputs

CCB is internally connected to VCC.

Table 2: Supported Single and Dual Supply Configurations

Supply voltage configuration VCCaVCCAbVCCBcVCCCdGND

3.3V 3.3V 3.3V 3.3V 3.3V 0V

Mixed voltage supply 3.3V 3.3V or 2.5V 3.3V 3.3V or 2.5V 0 V

2.5V 2.5V 2.5V 2.5V 2.5V 0 V

a. VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels

b. VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels

c. VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC.

d. VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels

Table 3: Function Table (Controls)

Control Default 0 1

FSELA 0 fQA0:2 = fREF fQA0:2 = fREF ÷ 2

FSELB 0 fQB0:2 = fREF fQB0:2 = fREF ÷ 2

FSELC 0 fQC0:3 = fREF fQC0:3 = fREF ÷ 2

MR/OE 0 Outputs enabled Internal reset

Outputs disabled (tristate)

Table 4: Absolute Maximum Ratingsa

Symbol Characteristics Min Max Unit Condition

VCC Supply Voltage -0.3 4.6 V

VIN DC Input Voltage -0.3 VCC+0.3 V

VOUT DC Output Voltage -0.3 VCC+0.3 V

IIN DC Input Current ±20 mA

IOUT DC Output Current ±50 mA

TSStorage temperature -40 125 °C

a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur . Exposure to these conditions

or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not

implied.

Table 5: General Specifications

Symbol Characteristics Min Typ Max Unit Condition

VTT Output Termination Voltage VCC ÷ 2 V

MM ESD Protection (Machine Model) 200 V

HBM ESD Protection (Human Body Model) 2000 V

LU Latch–Up Immunity 200 mA

CPD Power Dissipation Capacitance 10 pF Per output

CIN Input Capacitance 4.0 pF

MPC9456

MOTOROLA TIMING SOLUTIONS4

Table 6: DC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, TA = –40 to +85°C)

Symbol Characteristics Min Typ Max Unit Condition

VIH Input high voltage 2.0 VCC + 0.3 V LVCMOS

VIL Input low voltage -0.3 0.8 V LVCMOS

VPP Peak-to-peak input voltage PCLK 250 mV LVPECL

VCMRaCommon Mode Range PCLK 1.1 VCC-0.6 V LVPECL

IIN Input currentb200 µA VIN=GND or VIN=VCC

VOH Output High Voltage 2.4 V IOH=-24 mAc

VOL Output Low Voltage 0.55

0.30 V

VIOL= 24mAb

IOL= 12mA

ZOUT Output impedance 14 - 17

ICCQdMaximum Quiescent Supply Current 2.0 mA All VCC Pins

a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range

and the input swing lies within the VPP (DC) specification.

b. Input pull-up / pull-down resistors influence input current.

c. The MPC9456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated

transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines.

d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.

Table 7: AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, TA = –40 to +85°C)a

Symbol Characteristics Min Typ Max Unit Condition

fref Input Frequency 0 250bMHz

fMAX Maximum Output Frequency ÷1 output

÷2 output 0

0250b

125 MHz

MHz FSELx=0

FSELx=1

VPP Peak-to-peak input voltage PCLK 500 1000 mV LVPECL

VCMRcCommon Mode Range PCLK 1.3 VCC-0.8 V LVPECL

tP, REF Reference Input Pulse Width 1.4 ns

tr, tfPCLK Input Rise/Fall Time 1.0dns 0.8 to 2.0V

tPLH

tPHL Propagation delay CCLK to any Q

CCLK to any Q 2.2

2.2 2.8

2.8 4.45

4.2 ns

tPLZ, HZ Output Disable T ime 10 ns

tPZL, LZ Output Enable T ime 10 ns

tsk(O) Output-to-output Skew Within one bank

Any output bank, same output divider

Any output, Any output divider

150

200

350

tsk(PP) Device-to-device Skew 2.25 ns

tSK(P)

DCQ

Output pulse skewe

Output Duty Cycle ÷1 output

÷2 output 47

45 50

200

%DCREF = 50%

DCREF = 25%-75%

tr, tfOutput Rise/Fall Time 0.1 1.0 ns 0.55 to 2.4V

a. AC characteristics apply for parallel output termination of 50Ω to VTT.

b. The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.

c. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range

and the input swing lies within the VPP (AC) specification.

d. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew , reference input

pulse width, output duty cycle and maximum frequency specifications.

e. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.

MPC9456

TIMING SOLUTIONS 5 MOTOROLA

Table 8: DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, TA = –40 to +85°C)

Symbol Characteristics Min Typ Max Unit Condition

VIH Input high voltage 1.7 VCC + 0.3 V LVCMOS

VIL Input low voltage -0.3 0.7 V LVCMOS

VPP Peak-to-peak input voltage PCLK 250 mV LVPECL

VCMRaCommon Mode Range PCLK 1.1 VCC-0.7 V LVPECL

VOH Output High Voltage 1.8 V IOH=-15 mAb

VOL Output Low Voltage 0.6 V IOL= 15 mA

ZOUT Output impedance 17 - 20b

IIN Input currentc±200 µA VIN=GND or VIN=VCC

ICCQdMaximum Quiescent Supply Current 2.0 mA All VCC Pins

a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range

and the input swing lies within the VPP (DC) specification.

b. The MPC9456 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated

transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per

output.

c. Input pull-up / pull-down resistors influence input current.

d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.

Table 9: AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, TA = –40 to +85°C)a

Symbol Characteristics Min Typ Max Unit Condition

fref Input Frequency 0 250bMHz

fMAX Maximum Output Frequency ÷1 output

÷2 output 0

0250b

125 MHz

MHz FSELx=0

FSELx=1

VPP Peak-to-peak input voltage PCLK 500 1000 mV LVPECL

VCMRcCommon Mode Range PCLK 1.1 VCC-0.7 V LVPECL

tP, REF Reference Input Pulse Width 1.4 ns

tr, tfPCLK Input Rise/Fall Time 1.0dns 0.7 to 1.7V

tPLH

tPHL Propagation delay PCLK to any Q

PCLK to any Q 2.6

2.6 5.6

5.5 ns

tPLZ, HZ Output Disable T ime 10 ns

tPZL, LZ Output Enable T ime 10 ns

tsk(O) Output-to-output Skew Within one bank

Any output bank, same output divider

Any output, Any output divider

150

200

350

tsk(PP) Device-to-device Skew 3.0 ns

tSK(P)

DCQ

Output pulse skewe

Output Duty Cycle ÷1 or ÷2 output 45 50

200

%DCREF = 50%

tr, tfOutput Rise/Fall Time 0.1 1.0 ns 0.6 to 1.8V

a. AC characteristics apply for parallel output termination of 50Ω to VTT.

b. The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.

c. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range

and the input swing lies within the VPP (AC) specification.

d. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew , reference input

pulse width, output duty cycle and maximum frequency specifications.

e. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.

MPC9456

MOTOROLA TIMING SOLUTIONS6

Table 10: AC Characteristics (VCC = 3.3V ± 5%, VCCA = VCCB = VCCC = 2.5V ± 5% or 3.3V ± 5%,

TA = –40 to +85°C)a b

Symbol Characteristics Min Typ Max Unit Condition

tsk(O) Output-to-output Skew Within one bank

Any output bank, same output divider

Any output, Any output divider

150

250

350

tsk(PP) Device-to-device Skew 2.5 ns

tPLH,HL Propagation delay PCLK to any Q See 3.3V table

tSK(P)

DCQ

Output pulse skewc

Output Duty Cycle ÷1 or ÷2 output 45 50

250

%DCREF = 50%

a. AC characteristics apply for parallel output termination of 50Ω to VTT.

b. For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.

c. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.

MPC9456

TIMING SOLUTIONS 7 MOTOROLA

APPLICATIONS INFORMATION

Driving Transmission Lines

The MPC9456 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 20Ω the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to application note AN1091. In

most high performance clock networks point-to-point

distribution of signals is the method of choice. In a

point-to-point scheme either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50Ω resistance to VCC÷2.

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the MPC9456 clock driver . For the series terminated

case however there is no DC current draw, thus the outputs

can drive multiple series terminated lines. Figure 3. “Single

versus Dual T ransmission Lines” illustrates an output driving

a single series terminated line versus two series terminated

lines in parallel. When taken to its extreme the fanout of the

MPC9456 clock driver is effectively doubled due to its

capability to drive multiple lines.

Figure 3. Single versus Dual Transmission Lines

14Ω

MPC9456

OUTPUT

BUFFER

RS = 36ΩZO = 50ΩOutA

14Ω

MPC9456

OUTPUT

BUFFER RS = 36ΩZO = 50ΩOutB0

RS = 36ΩZO = 50ΩOutB1

The waveform plots in Figure 4. “Single versus Dual Line

Termination Waveforms” show the simulation results of an

output driving a single line versus two lines. In both cases the

drive capability of the MPC9456 output buffer is more than

sufficient to drive 50Ω transmission lines on the incident

edge. Note from the delay measurements in the simulations a

delta of only 43ps exists between the two differently loaded

outputs. This suggests that the dual line driving need not be

used exclusively to maintain the tight output-to-output skew

of the MPC9456. The output waveform in Figure 4. “Single

versus Dual Line Termination Waveforms” shows a step in

the waveform, this step is caused by the impedance

mismatch seen looking into the driver. The parallel

combination of the 36Ω series resistor plus the output

impedance does not match the parallel combination of the

line impedances. The voltage wave launched down the two

lines will equal:

VL = VS ( Z0 ÷ (RS+R0 +Z0))

Z0 = 50Ω || 50Ω

RS = 36Ω || 36Ω

R0 = 14Ω

VL = 3.0 ( 25 ÷ (18+14+25)

= 1.31V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.5V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

Figure 4. Single versus Dual Waveforms

TIME (nS)

VOLTAGE (V)

3.0

2.5

2.0

1.5

1.0

0.5

02 4 6 8 10 12 14

OutB

tD = 3.9386

OutA

tD = 3.8956

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the

situation in Figure 5. “Optimized Dual Line Termination”

should be used. In this case the series terminating resistors

are reduced such that when the parallel combination is added

to the output buffer impedance the line impedance is perfectly

matched.

Figure 5. Optimized Dual Line Termination

14Ω

MPC9456

OUTPUT

BUFFER RS = 22ΩZO = 50Ω

RS = 22ΩZO = 50Ω

14Ω + 22Ω

22Ω = 50Ω

50Ω

25Ω = 25Ω

MPC9456

MOTOROLA TIMING SOLUTIONS8

Figure 6. PCLK MPC9456 AC test reference for Vcc = 3.3V and Vcc = 2.5V

Differential

Pulse Generator

Z = 50

RT = 50Ω

ZO = 50Ω

RT = 50Ω

ZO = 50Ω

MPC9456 DUT

VCC – 2V VTT

Figure 7. Output Transition T ime Test Reference Figure 8. Propagation delay (tPD) test reference

Figure 9. Output Duty Cycle (DC) Figure 10. Output–to–output Skew tSK(O)

The pin–to–pin skew is defined as the worst case difference

in propagation delay between any similar delay path within a

single device

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

VCC

GND

DC = tP/T0 x 100%

tFtR

VCC=3.3V VCC=2.5V

2.4 1.8V

0.55 0.6V

VCC

GND

VOH

VCC

GND

VCC

GND

t(LH)

PCLK

PCLK VCMR

VPP

t(HL)

tSK(LH) tSK(HL)

Figure 11. Output Transition Time test reference

tFtR

VCC=3.3V VCC=2.5V

2.4 1.8V

0.55 0.6V

MPC9456

TIMING SOLUTIONS 9 MOTOROLA

OUTLINE DIMENSIONS

FA SUFFIX

LQFP PACKAGE

CASE 873A-02

ISSUE A

ÏÏ

DETAIL Y

BASE

METAL

SECTION AE–AE

SEATING

PLANE

0.250 (0.010)

GAUGE PLANE

DETAIL AD

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –AB– IS LOCATED AT BOTTOM

OF LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED

AT DATUM PLANE –AB–.

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE –AC–.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B

DO INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE –AB–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.520 (0.020).

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076 (0.0003).

9. EXACT SHAPE OF EACH CORNER MAY VARY

FROM DEPICTION.

DIM

AMIN MAX MIN MAX

INCHES

7.000 BSC 0.276 BSC

MILLIMETERS

B7.000 BSC 0.276 BSC

C1.400 1.600 0.055 0.063

D0.300 0.450 0.012 0.018

E1.350 1.450 0.053 0.057

F0.300 0.400 0.012 0.016

G0.800 BSC 0.031 BSC

H0.050 0.150 0.002 0.006

J0.090 0.200 0.004 0.008

K0.500 0.700 0.020 0.028

M12 REF 12 REF

N0.090 0.160 0.004 0.006

P0.400 BSC 0.016 BSC

Q1 5 1 5

R0.150 0.250 0.006 0.010

V9.000 BSC 0.354 BSC

V1 4.500 BSC 0.177 BSC

____

DETAIL AD

B1 V1

B1 3.500 BSC 0.138 BSC

A1 3.500 BSC 0.138 BSC

S9.000 BSC 0.354 BSC

S1 4.500 BSC 0.177 BSC

W0.200 REF 0.008 REF

X1.000 REF 0.039 REF

–T–

–Z–

–U–

T–U0.20 (0.008) Z

T–U0.20 (0.008) ZAB

0.10 (0.004) AC

–AC–

–AB–

–T–, –U–, –Z–

T–U

0.20 (0.008) ZAC

MPC9456

MOTOROLA TIMING SOLUTIONS10

NOTES

MPC9456

TIMING SOLUTIONS 11 MOTOROLA

NOTES

MPC9456

MOTOROLA TIMING SOLUTIONS12

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”

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MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.

Motorola, Inc. 2002.

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MPC9456/D

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