1. General description
The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs,
clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the nQ output on the
LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt trigger action at all input s makes the circuit hi ghly tolerant of slower input rise and
fall times.
2. Features and benefits
5 V tolerant inputs for interlacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V t o 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 7 — 20 November 2012 Product data sheet
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 2 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
3. Ordering information
4. Functional diagram
Tabl e 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads;
body width 3.9 mm SOT108-1
74LVC74ADB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm SOT337-1
74LVC74APW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74LVC74ABQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 14 terminals;
body 2.5 30.85 mm
SOT762-1
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Functional diagram
mna418
RD
FF
SD
410
Q1Q
2Q
1Q
2Q
5
9
2
12
3
11 6
8
Q
1SD
CP
2CP
1CP
2D
1D D
2SD
113
1RD 2RD
mna419
6
3
2C1
4S
1D
1R
5
8
11
12 C1
10 S
1D
13 R
9
RD
FF
SD
4
Q1Q
1Q
5
2
3
6
Q
1SD
CP
1CP
1D D
11RD
mna420
RD
FF
SD
10
Q2Q
2Q
9
12
11
8
Q
2SD
CP
2CP
2D D
13 2RD
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 3 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
5. Pinning information
5.1 Pinning
Fig 4. Logic diagram for one flip-flop
mna421
SD
CP
RD
D
C
C
Q
C
C
C
C
C
C
Q
C
C
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration fo r SO14 and (T)SSOP14 Fig 6. Pin configuration for DHVQFN14
74
1RD VCC
1D 2RD
1CP 2D
1SD 2CP
1Q 2SD
1Q 2Q
GND 2Q
001aad106
1
2
3
4
5
6
7 8
10
9
12
11
14
13
001aad107
74
Transparent top view
1Q 2Q
1Q 2SD
1SD 2CP
1CP 2D
2RD1D
GND(1)
GND
2Q
1RD
VCC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 4 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level
L = LOW voltage level
X = don’t care
[1] H = HIGH voltage level
L = LOW voltage level
= LOW-to-HIGH transition
Qn+1 = state after the next LOW-to-HIGH CP transition
X = don’t care
Table 2. Pin description
Symbol Pin Description
1RD 1 asynchronous reset-direct input (active LOW)
1D 2 data input
1CP 3 clock input (LOW-to-HIGH, edge-triggered)
1SD 4 asynchronous set-direct input (active LOW)
1Q 5 true outp u t
1Q 6 complement outp ut
GND 7 ground (0 V)
2Q 8 complement outp ut
2Q 9 true outp u t
2SD 10 asynchronous set-direct input (active LOW)
2CP 11 clock input (LOW-to-HIGH, edge-triggered)
2D 12 data input
2RD 13 asynchronous reset-direct input (active LOW)
VCC 14 supply voltage
Table 3. Function table[1]
Input Output
nSDnRDnCP nD nQ nQ
LHXXHL
HLXXLH
LLXXHH
Table 4. Function table[1]
Input Output
nSDnRDnCP nD nQn+1 nQn+1
HHLLH
HHHHL
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 5 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO14 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA
VOoutput voltage [2] 0.5 VCC + 0.5 V
IOoutput current VO = 0 V to VCC -50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C[3] - 500 mW
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage for maximum speed performance 1.65 - 3.6 V
for low-voltage applications 1.2 - 3 .6 V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and
fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 6 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
9. Static characteristics
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25C.
Table 7. Static characteristics
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC -0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage
VI=V
IH or VIL
IO=100 A;
VCC =1.65Vto3.6V VCC 0.2 - - VCC 0.3 - V
IO=4mA; V
CC = 1.65 V 1.2 - - 1.05 - V
IO=8mA; V
CC = 2.3 V 1.8 - - 1.65 - V
IO=12 mA; VCC = 2.7 V 2.2 - - 2.05 - V
IO=18 mA; VCC = 3.0 V 2.4 - - 2.25 - V
IO=24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage
VI=V
IH or VIL
IO= 100 A;
VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V
IO=4mA; V
CC = 1.65 V - - 0.45 - 0.65 V
IO=8mA; V
CC = 2.3 V - - 0.6 - 0.8 V
IO=12mA; V
CC = 2.7 V - - 0.4 - 0.6 V
IO=24mA; V
CC = 3.0 V - - 0.55 - 0.8 V
IIinput leakage
current VCC = 3.6 V; VI=5.5VorGND - 0.1 5-20 A
ICC supply
current VCC = 3.6 V; VI=V
CC or GND;
IO=0A -0.110 - 40A
ICC additional
supply
current
per input pin;
VCC = 2.7 V to 3.6 V;
VI=V
CC 0.6 V; IO=0A
- 5 500 - 5000 A
CIinput
capacitance VCC = 0 V to 3.6 V;
VI=GNDtoV
CC
-4.0- - -pF
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 7 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
10. Dynamic characteristics
Table 8. Dynamic characteristics
Vo ltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation
delay nCP to nQ, nQ; see Figure 7 [2]
VCC = 1.2 V - 15 - - - ns
VCC = 1.65 V to 1.95 V 1.0 5.0 10.3 1.0 11.9 ns
VCC = 2.3 V to 2.7 V 1.8 2.9 5.8 1.8 6.7 ns
VCC = 2.7 V 1.0 2.7 6.0 1.0 7.5 ns
VCC = 3.0 V to 3.6 V 1.0 2.6 5.2 1.0 6.5 ns
nSDtonQ, nQ; see Figure 8
VCC = 1.2 V - 15 - - - ns
VCC = 1.65 V to 1.95 V 0.5 4.0 10.6 0.5 12.2 ns
VCC = 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns
VCC = 2.7 V 1.0 2.9 6.4 1.0 8.0 ns
VCC = 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns
nRD to nQ, nQ; see Figure 8
VCC = 1.2 V - 15 - - - ns
VCC = 1.65 V to 1.95 V 0.5 4.1 10.7 0.5 12.4 ns
VCC = 2.3 V to 2.7 V 1.0 2.4 6.1 1.0 7.1 ns
VCC = 2.7 V 1.0 3.0 6.4 1.0 8.0 ns
VCC = 3.0 V to 3.6 V 1.0 2.2 5.4 1.0 7.0 ns
tWpulse width clock HIGH or LOW; see Figure 7
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns
VCC = 2.7 V 3.3 - - 4.5 - ns
VCC = 3.0 V to 3.6 V 3.3 1.3 - 4.5 - ns
set or reset LOW; see Figure 8
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns
VCC = 2.7 V 3.3 - - 4.5 - ns
VCC = 3.0 V to 3.6 V 3.3 1.7 - 4.5 - ns
trec recovery time set or reset; see Figure 8
VCC = 1.65 V to 1.95 V 1.5 - - 1.5 - ns
VCC = 2.3 V to 2.7 V 1.5 - - 1.5 - ns
VCC = 2.7 V 1.5 - - 1.0 - ns
VCC = 3.0 V to 3.6 V +1.0 3.0 - 1.0 - ns
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 8 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
[1] Typical values are measured at Tamb =25C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CLVCC2fo) = sum of the outputs
tsu set-up time nD to nCP; see Figure 7
VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns
VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns
VCC = 2.7 V 2.2 - - 2.2 - ns
VCC = 3.0 V to 3.6 V 2.0 0.8 - 2.0 - ns
thhold time nD to nCP; see Figure 7
VCC = 1.65 V to 1.95 V 2.0 - - 2.0 - ns
VCC = 2.3 V to 2.7 V 1.5 - - 1.5 - ns
VCC = 2.7 V 1.0 - - 1.0 - ns
VCC = 3.0 V to 3.6 V +1.0 0.2 - 1.0 - ns
fmax maximum
frequency nCP; see Figure 7
VCC = 1.65 V to 1.95 V 100 - - 80 - MHz
VCC = 2.3 V to 2.7 V 125 - - 100 - MHz
VCC = 2.7 V 150 - - 120 - MHz
VCC = 3.0 V to 3.6 V 150 250 - 120 - MHz
tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns
CPD power
dissipation
capacitance
per flip-flop; VI=GNDtoV
CC [4]
VCC = 1.65 V to 1.95 V - 12.4 - - - pF
VCC = 2.3 V to 2.7 V - 16.0 - - - pF
VCC = 3.0 V to 3.6 V - 19.1 - - - pF
Table 8. Dynamic characteristics …continued
Vo ltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 9 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
11. AC waveforms
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The clock input (nCP) to output (nQ, nQ) prop agation delays, the clock pulse width, the nD to nCP set-up,
the nCP to nD hold times, and the maximum frequency
mna422
t
h
t
su
t
h
t
PHL
t
PHL
t
W
t
PLH
t
PLH
t
su
1/f
max
V
M
V
M
V
M
V
M
V
I
GND
V
I
GND
nCP input
nD input
V
OH
V
OL
nQ output
V
OH
V
OL
nQ output
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 10 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse
widths, and the nRD to nCP recovery time
mna423
trec
tPHL
tPHL
tW
tPLH
tPLH
VM
VM
VM
tW
VM
VM
VI
GND
VI
GND
nSD input
VI
GND
nRD input
nCP input
VOH
VOL
nQ output
VOH
VOL
nQ output
Table 9. Measurement points
Supply voltage Input Output
VCC VIVMVM
1.2 V VCC 0.5 VCC 0.5 VCC
1.65 V to 1.95 V VCC 0.5 VCC 0.5 VCC
2.3 V to 2.7 V VCC 0.5 VCC 0.5 VCC
2.7 V 2.7 V 1.5 V 1.5 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 11 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 9. Load circuitry for switching times
Table 10. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
1.2 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
1.65 V to 1.95 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND
2.7V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 12 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
12. Package outline
Fig 10. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 13 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Fig 11. Package outline SOT337-1 (SSOP14)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25 0.2
7.9
7.6 1.03
0.63 0.9
0.7 1.4
0.9 8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
A
max.
2
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 14 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Fig 12. Package outline SOT402-1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 15 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Fig 13. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 16 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
13. Abbreviations
14. Revision history
Table 11. Abbreviations
Acronym Description
CDM Charged Device Mo del
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC74A v.7 20121120 Product data sheet - 74LVC74A v.6
Modifications: •Table 6, Table 7, Table 8, Table 9 and Table 10: values added for lower voltage ranges.
74LVC74A v.6 20070604 Product data sheet - 74LVC74A v.5
74LVC74A v.5 20070525 Product data sheet - 74LVC74A v.4
74LVC74A v.4 20030526 Product specification - 74LVC74A v.3
74LVC74A v.3 20020618 Product specification - 74LVC74A v.2
74LVC74A v.2 19980617 Product specification - 74LVC74A v.1
74LVC74A v.1 19980617 Product specification - -
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 17 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVC74A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 20 November 2012 18 of 19
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of rele ase: 20 November 2012
Document identifier: 74LVC74A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16 Contact information. . . . . . . . . . . . . . . . . . . . . 18
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19