Data Sheet
©2006 Silicon Storage Technology, Inc.
S71288-02-000 7/06
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
64 Mbit (x16) Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
FEATURES:
Organized as 4M x16
Single Voltage Read and Write Operations
2.7-3.6V
Superior Reliability
Endurance: 100,000 Cycles (Typical)
Greater than 100 years Data Retention
Low Power Consumption (typical values at 5 MHz)
Active Current: 9 mA (typical)
Standby Current: 3 µA (typical)
Auto Low Power Mode: 3 µA (typical)
Hardware Block-Protection/WP# Input Pin
Top Block-Protection (top 32 KWord)
for SST39VF6402B
Bottom Block-Protection (bottom 32 KWord)
for SST39VF6401B
Sector-Erase Capability
Uniform 2 KWord sectors
Block-Erase Capability
Uniform 32 KWord blocks
Chip-Erase Capability
Erase-Suspend/Erase-Resume Capabilities
Hardware Reset Pin (RST#)
Security-ID Feature
SST: 128 bits; User: 128 bits
Fast Read Access Time:
70 ns
90 ns
Latched Address and Data
Fast Erase and Word-Program:
Sector-Erase Time: 18 ms (typical)
Block-Erase Time: 18 ms (typical)
Chip-Erase Time: 40 ms (typical)
Word-Program Time: 7 µs (typical)
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bits
Data# Polling
CMOS I/O Compatibility
JEDEC Standard
Flash EEPROM Pin Assignments
Software command sequence compatibility
- Address format is 11 bits, A10-A0
- Block-Erase 6th Bus Write Cycle is 30H
- Sector-Erase 6th Bus Write Cycle is 50H
Packages Available
48-lead TSOP (12mm x 20mm)
48-ball TFBGA (8mm x 10mm)
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39VF640xB devices are 4M x16 CMOS Multi-
Purpose Flash Plus (MPF+) manufactured with SST’s pro-
prietary, high-performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39VF640xB write (Pro-
gram or Erase) with a 2.7-3.6V power supply. These
devices conform to JEDEC standard pin assignments for
x16 memories.
Featuring high performance Word-Program, the
SST39VF640xB devices provide a typical Word-Program
time of 7 µsec. These devices use Toggle Bit or Data# Poll-
ing to indicate the completion of Program operation. To pro-
tect against inadvertent write, they have on-chip hardware
and Software Data Protection schemes. Designed, manu-
factured, and tested for a wide spectrum of applications,
these devices are offered with a guaranteed typical endur-
ance of 100,000 cycles. Data retention is rated at greater
than 100 years.
The SST39VF640xB devices are suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
they significantly improve performance and reliability, while
lowering power consumption. They inherently use less
energy during Erase and Program than alternative flash
technologies. The total energy consumed is a function of
the applied voltage, current, and time of application. Since
for any given voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time,
the total energy consumed during any Erase or Program
operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high-density, surface mount requirements, the
SST39VF640xB devices are offered in 48-lead TSOP and
48-ball TFBGA packages. See Figures 1 and 2 for pin
assignments.
SST39VF640xB2.7V 64Mb (x16) MPF+ memories
2
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST39VF640xB also have the Auto Low Power
mode which puts the device in a near standby mode after
data has been accessed with a valid Read operation. This
reduces the IDD active read current from typically 9 mA to
typically 3 µA. The Auto Low Power mode reduces the typi-
cal IDD active read current to the range of 2 mA/MHz of
Read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto-Low
Power mode after power-up with CE# held steadily low,
until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF640xB is controlled
by CE# and OE#, both have to be low for the system to
obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
only standby power is consumed. OE# is the output con-
trol and is used to gate data from the output pins. The
data bus is in high impedance state when either CE# or
OE# is high. Refer to the Read cycle timing diagram for
further details (Figure 3).
Word-Program Operation
The SST39VF640xB are programmed on a word-by-word
basis. Before programming, the sector where the word
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed within 10
µs. See Figures 4 and 5 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 19 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during the internal Program opera-
tion are ignored. During the command sequence, WP#
should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF640xB offer both Sector-Erase
and Block-Erase mode. The sector architecture is based
on uniform sector size of 2 KWord. The Block-Erase mode
is based on uniform block size of 32 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (50H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (30H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (50H or 30H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
ing waveforms and Figure 23 for the flowchart. Any com-
mands issued during the Sector- or Block-Erase operation
are ignored. When WP# is low, any attempt to Sector-
(Block-) Erase the protected block will be ignored. During
the command sequence, WP# should be statically held
high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing one byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode typically within 20
µs after the Erase-Suspend command had been issued.
Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address
location within erase-suspended sectors/blocks will output
DQ2 toggling and DQ6 at “1”. While in Erase-Suspend
mode, a Word-Program operation is allowed except for the
sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has
been suspended the system must issue Erase Resume
command. The operation is executed by issuing one byte
command sequence with Erase Resume command (30H)
at any address in the last Byte sequence.
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
3
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
Chip-Erase Operation
The SST39VF640xB provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 6 for the command sequence, Figure 9 for tim-
ing diagram, and Figure 23 for the flowchart. Any com-
mands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will
be ignored. During the command sequence, WP# should
be statically held high or low.
Write Operation Status Detection
The SST39VF640xB provide two software means to detect
the completion of a Write (Program or Erase) cycle, in
order to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ7) and
Toggle Bit (DQ6). The End-of-Write detection mode is
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the SST39VF640xB are in the internal Program
operation, any attempt to read DQ7 will produce the com-
plement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase oper-
ation, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
Data# Polling timing diagram and Figure 20 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)
is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to “1” if a Read operation is attempted on an
Erase-Suspended Sector/Block. If Program operation is ini-
tiated in a sector/block not selected in Erase-Suspend
mode, DQ6 will toggle.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bits information. The Toggle Bit
(DQ2) is valid after the rising edge of the last WE# (or CE#)
pulse of Write operation. See Figure 7 for Toggle Bit timing
diagram and Figure 20 for a flowchart.
Note: DQ7 and DQ2 require a valid address when reading
status information.
TABLE 1: WRITE OPERATION STATUS
Status DQ7DQ6DQ2
Normal
Operation
Standard
Program
DQ7# Toggle No Toggle
Standard
Erase
0 Toggle Toggle
Erase-
Suspend
Mode
Read from
Erase-Suspended
Sector/Block
1 1 Toggle
Read from
Non- Erase-Suspended
Sector/Block
Data Data Data
Program DQ7# Toggle N/A
T1.0 1288
4
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
Data Protection
The SST39VF640xB provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST39VF6402B support top hardware block protec-
tion, which protects the top 32 KWord block of the device.
The SST39VF6401B support bottom hardware block pro-
tection, which protects the bottom 32 KWord block of the
device. The Boot Block address ranges are described in
Table 2. Program and Erase operations are prevented on
the 32 KWord when WP# is low. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera-
tions on that block.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of TRHR is
required after RST# is driven high before a valid Read can
take place (see Figure 15).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39VF640xB provide the JEDEC approved Soft-
ware Data Protection scheme for all data alteration opera-
tions, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
6 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to read mode within TRC. The contents of DQ15-DQ8
can be VIL or VIH, but no other value, during any SDP com-
mand sequence.
Common Flash Memory Interface (CFI)
The SST39VF640xB also contain the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must write three-byte
sequence, same as product ID entry command with 98H
(CFI Query command) to address 555H in the last byte
sequence. Once the device enters the CFI Query mode,
the system can read CFI data at the addresses given in
Tables 7 through 9. The system must write the CFI Exit
command to return to Read mode from the CFI Query
mode.
TABLE 2: BOOT BLOCK ADDRESS RANGES
Product Address Range
Bottom Boot Block
SST39VF6401B 000000H-007FFFH
Top Boot Block
SST39VF6402B 3F8000H-3FFFFFH
T2.0 1288
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
5
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
Product Identification
The Product Identification mode identifies the devices as
the SST39VF6401B and SST39VF6402B, and the manu-
facturer as SST. This mode may be accessed through
software operations. Users may use the Software Product
Identification operation to identify the part (i.e., using the
device ID) when using multiple manufacturers in the same
socket. For details, see Table 6 for software operation,
Figure 11 for the Software ID Entry and Read timing dia-
gram and Figure 21 for the Software ID Entry command
sequence flowchart.
Product Identification Mode Exit/
CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 6 for software command
codes, Figure 13 for timing waveform, and Figures 21 and
22 for flowcharts.
Security ID
The SST39VF640xB devices offer a 256-bit Security ID
space. The Secure ID space is divided into two 128-bit seg-
ments - one factory programmed segment and one user
programmed segment. The first segment is programmed
and locked at SST with a random 128-bit number. The user
segment is left un-programmed for the customer to pro-
gram as desired.
To program the user segment of the Security ID, the user
must use the Security ID Word-Program command. To
detect end-of-write for the SEC ID, read the toggle bits. Do
not use Data# Polling. Once this is complete, the Sec ID
should be locked using the User Sec ID Program Lock-Out.
This disables any future corruption of this space. Note that
regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
The Secure ID space can be queried by executing a three-
byte command sequence with Enter Sec ID command
(88H) at address 555H in the last byte sequence. To exit
this mode, the Exit Sec ID command should be executed.
Refer to Table 6 for more details.
TABLE 3: PRODUCT IDENTIFICATION
Address Data
Manufacturer’s ID 0000H BFH
Device ID
SST39VF6401B 0001H 236DH
SST39VF6402B 0001H 236CH
T3.0 1288
6
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP
Y-Decoder
I/O Buffers and Data Latches
1288 B1.0
Address Buffer & Latches
X-Decoder
DQ15 - DQ0
Memory Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
WP#
RESET#
FUNCTIONAL BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RST#
A21
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1288 48-tsop P1.0
Standard Pinout
Top View
Die Up
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
7
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA
TABLE 4: PIN DESCRIPTION
Symbol Pin Name Functions
AMS1-A0
1. AMS = Most significant address
AMS = A21 for SST39VF640xB
Address Inputs To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded.
RST# Reset To reset and return the device to Read mode.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
VDD Power Supply To provide power supply voltage: 2.7-3.6V
VSS Ground
NC No Connection Unconnected pins.
T4.0 1288
1288 4-tfbga B1K P2.0
A B C D E F G H
6
5
4
3
2
1
TOP VIEW (balls facing down)
A13
A9
WE#
NC
A7
A3
A12
A8
RST#
WP#
A17
A4
A14
A10
A21
A18
A6
A2
A15
A11
A19
A20
A5
A1
A16
DQ7
DQ5
DQ2
DQ0
A0
NC
DQ14
DQ12
DQ10
DQ8
CE#
DQ15
DQ13
VDD
DQ11
DQ9
OE#
VSS
DQ6
DQ4
DQ3
DQ1
VSS
8
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
TABLE 5: OPERATION MODES SELECTION
Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Program VIL VIH VIL DIN AIN
Erase VIL VIH VIL X1Sector or block address,
XXH for Chip-Erase
Standby VIH X X High Z X
Write Inhibit X VIL X High Z/ DOUT X
XXV
IH High Z/ DOUT X
Product Identification
Software Mode VIL VIL VIH See Table 6
T5.0 1288
1. X can be VIL or VIH, but no other value.
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
9
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
TABLE 6: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2
Word-Program 555H AAH 2AAH 55H 555H A0H WA3Data
Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX450H
Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX430H
Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Erase-Suspend XXXXH B0H
Erase-Resume XXXXH 30H
Query Sec ID5555H AAH 2AAH 55H 555H 88H
User Security ID
Word-Program
555H AAH 2AAH 55H 555H A5H WA6Data
User Security ID
Program Lock-Out
555H AAH 2AAH 55H 555H 85H XXH60000H
Software ID Entry7,8 555H AAH 2AAH 55H 555H 90H
CFI Query Entry 555H AAH 2AAH 55H 555H 98H
Software ID Exit9,10
/CFI Exit/Sec ID Exit
555H AAH 2AAH 55H 555H F0H
Software ID Exit9,10
/CFI Exit/Sec ID Exit
XXH F0H
T6.0 1288
1. Address format A10-A0 (Hex).
Addresses A11- A21 can be VIL or VIH, but no other value, for Command sequence for SST39VF640xB.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address
AMS = A21 for SST39VF640xB
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000010H to 000017H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39VF6401B Device ID = 236DH, is read with A0 = 1,
SST39VF6402B Device ID = 236CH, is read with A0 = 1.
AMS = Most significant address
AMS = A21 for SST39VF640xB
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID
mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and
000010H-000017H.
10
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
TABLE 7: CFI QUERY IDENTIFICATION STRING1 FOR SST39VF640XB
Address Data Data
10H 0051H Query Unique ASCII string “QRY”
11H 0052H
12H 0059H
13H 0002H Primary OEM command set
14H 0000H
15H 0000H Address for Primary Extended Table
16H 0000H
17H 0000H Alternate OEM command set (00H = none exists)
18H 0000H
19H 0000H Address for Alternate OEM extended Table (00H = none exits)
1AH 0000H
T7.0 1288
1. Refer to CFI publication 100 for more details.
TABLE 8: SYSTEM INTERFACE INFORMATION FOR SST39VF640XB
Address Data Data
1BH 0027H VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH 0036H VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH 0000H VPP min. (00H = no VPP pin)
1EH 0000H VPP max. (00H = no VPP pin)
1FH 0003H Typical time out for Word-Program 2N µs (23 = 8 µs)
20H 0000H Typical time out for min. size buffer program 2N µs (00H = not supported)
21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms)
23H 0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)
24H 0000H Maximum time out for buffer program 2N times typical
25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
T8.0 1288
TABLE 9: DEVICE GEOMETRY INFORMATION FOR SST39VF640XB
Address Data Data
27H 0017H Device size = 2N Bytes (17H = 23; 223 = 8 MByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of bytes in multi-byte write = 2N (00H = not supported)
2BH 0000H
2CH 0002H Number of Erase Sector/Block sizes supported by device
2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 0007H y = 2047 + 1 = 2048 sectors (07FFH = 2047)
2FH 0010H
30H 0000H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H 007FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 0000H y =127 + 1 = 128 blocks (007FH = 127)
33H 0000H
34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
T9.0 1288
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
11
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range Ambient Temp VDD
Commercial
Industrial
0°C to +70°C
-40°C to +85°C
2.7-3.6V
2.7-3.6V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 17 and 18
12
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
TABLE 10: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD Power Supply Current Address input=VILT/VIHT2, at f=5 MHz,
VDD=VDD Max
Read318 mA CE#=VIL, OE#=WE#=VIH, all I/Os open
Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH
ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max
IALP Auto Low Power 20 µA CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILIW Input Leakage Current
on WP# pin and RST#
10 µA WP#=GND to VDD or RST#=GND to VDD
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max
VIH Input High Voltage 0.7VDD VV
DD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
T10.0 1288
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 17
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Ty pi c a l VDD is 3V.
TABLE 11: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol Parameter Minimum Units
TPU-READ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Power-up to Read Operation 100 µs
TPU-WRITE1Power-up to Program/Erase Operation 100 µs
T11.0 1288
TABLE 12: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum
CI/O1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
I/O Pin Capacitance VI/O = 0V 12 pF
CIN1Input Capacitance VIN = 0V 6 pF
T12.0 1288
TABLE 13: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
NEND1,2
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
Endurance 10,000 Cycles JEDEC Standard A117
TDR1Data Retention 100 Years JEDEC Standard A103
ILTH1Latch Up 100 + IDD mA JEDEC Standard 78
T13.0 1288
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
13
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
AC CHARACTERISTICS
TABLE 14: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
Symbol Parameter
SST39VF640xB-70 SST39VF640xB-90
UnitsMin Max Min Max
TRC Read Cycle Time 70 90 ns
TCE Chip Enable Access Time 70 90 ns
TAA Address Access Time 70 90 ns
TOE Output Enable Access Time 35 45 ns
TCLZ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
CE# Low to Active Output 0 0 ns
TOLZ1OE# Low to Active Output 0 0 ns
TCHZ1CE# High to High-Z Output 20 30 ns
TOHZ1OE# High to High-Z Output 20 30 ns
TOH1Output Hold from Address Change 0 0 ns
TRP1RST# Pulse Width 500 500 ns
TRHR1RST# High before Read 50 50 ns
TRY1,2
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
RST# Pin Low to Read Mode 20 20 µs
T14.0 1288
TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter Min Max Units
TBP Word-Program Time 10 µs
TAS Address Setup Time 0 ns
TAH Address Hold Time 30 ns
TCS WE# and CE# Setup Time 0 ns
TCH WE# and CE# Hold Time 0 ns
TOES OE# High Setup Time 0 ns
TOEH OE# High Hold Time 10 ns
TCP CE# Pulse Width 40 ns
TWP WE# Pulse Width 40 ns
TWPH1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
WE# Pulse Width High 30 ns
TCPH1CE# Pulse Width High 30 ns
TDS Data Setup Time 30 ns
TDH1Data Hold Time 0 ns
TIDA1Software ID Access and Exit Time 150 ns
TSE Sector-Erase 25 ms
TBE Block-Erase 25 ms
TSCE Chip-Erase 50 ms
T15.0 1288
14
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 3: READ CYCLE TIMING DIAGRAM
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
1288 F03.0
ADDRESS AMS-0
DQ15-0
WE#
OE#
CE# TCE
TRC TAA
TOE
TOLZVIH
HIGH-Z TCLZ TOH
TCHZ
HIGH-Z
DATA VALIDDATA VALID
TOHZ
Note: AMS = Most significant address
AMS = A21 for SST39VF640xB
1288 F04.0
ADDRESS AMS-0
DQ15-0
TDH
TWPH
TDS
TWP
TAH
TAS
TCH
TCS
CE#
SW0 SW1 SW2
555 2AA 555 ADDR
XXAA XX55 XXA0 DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
OE#
WE#
TBP
Note: AMS = Most significant address
AMS = A21 for SST39VF640xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
15
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
FIGURE 6: DATA# POLLING TIMING DIAGRAM
1288 F05.0
ADDRESS AMS-0
DQ15-0
TDH
TCPH
TDS
TCP
TAH
TAS
TCH
TCS
WE#
SW0 SW1 SW2
555 2AA 555 ADDR
XXAA XX55 XXA0 DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
OE#
CE#
TBP
Note: AMS = Most significant address
AMS = A21 for SST39VF640xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
1288 F06.0
ADDRESS AMS-0
DQ7DATA DATA# DATA# DATA
WE#
OE#
CE#
TOEH
TOE
TCE
TOES
Note: AMS = Most significant address
AMS = A21 for SST39VF640xB
16
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 7: TOGGLE BITS TIMING DIAGRAM
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
1288 F07.0
ADDRESS AMS-0
DQ6 and DQ2
WE#
OE#
CE#
TOETOEH
TCE
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: AMS = Most significant address
AMS = A21 for SST39VF640xB
1288 F08.0
ADDRESS AMS-0
DQ15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
555 2AA 2AA555 555
XX55 XX10XX55XXAA XX80 XXAA
555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
TSCE
TWP
Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
AMS = Most significant address
AMS = A21 for SST39VF640xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
17
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
1288 F09.0
ADDRESS AMS-0
DQ15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
555 2AA 2AA555 555
XX55 XX30XX55XXAA XX80 XXAA
BAX
OE#
CE#
SIX-BYTE CODE FOR BLOCK-ERASE
TBE
TWP
Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
BAX = Block Address
AMS = Most significant address
AMS = A21 for SST39VF640xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
1288 F10.0
ADDRESS AMS-0
DQ15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
555 2AA 2AA555 555
XX55 XX50XX55XXAA XX80 XXAA
SAX
OE#
CE#
SIX-BYTE CODE FOR SECTOR-ERASE
TSE
TWP
Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
SAX = Sector Address
AMS = Most significant address
AMS = A21 for SST39VF640xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
18
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 11: SOFTWARE ID ENTRY AND READ
FIGURE 12: CFI QUERY ENTRY AND READ
1288 F11.0
ADDRESS A14-0
TIDA
DQ15-0
WE#
SW0 SW1 SW2
555 2AA 555 0000 0001
OE#
CE#
Three-Byte Sequence for Software ID Entry
TWP
TWPH TAA
00BF
Device ID
XX55XXAA XX90
Note: Device ID = 236DH for SST39VF6401B and 236CH for SST39VF6402B
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
1288 F12.0
ADDRESS A14-0
TIDA
DQ15-0
WE#
SW0 SW1 SW2
555 2AA 555
OE#
CE#
Three-Byte Sequence for CFI Query Entry
TWP
TWPH TAA
XX55XXAA XX98
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
19
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 13: SOFTWARE ID EXIT/CFI EXIT
FIGURE 14: SEC ID ENTRY
1288 F13.0
ADDRESS A14-0
DQ15-0
TIDA
TWP
TWHP
WE#
SW0 SW1 SW2
555 2AA 555
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
OE#
CE#
XXAA XX55 XXF0
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
1288 F14.0
ADDRESS AMS-0
TIDA
DQ15-0
WE#
SW0 SW1 SW2
555 2AA 555
OE#
CE#
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
TWP
TWPH TAA
XX55XXAA XX88
Note: AMS = Most significant address
AMS = A21 for SST39VF640xB
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
20
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 15: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)
FIGURE 16: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION)
1288 F15.0
RST#
CE#/OE#
TRP
TRHR
1288 F16.0
RST#
CE#/OE#
TRP
TRY
End-of-Write Detection
(Toggle-Bit)
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
21
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS
FIGURE 18: A TEST LOAD EXAMPLE
1288 F17.0
REFERENCE POINTS OUTPUTINPUT VIT
VIHT
VILT
VOT
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Te s t
VOT - VOUTPUT Tes t
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
1288 F18.0
TO TESTER
TO DUT
CL
22
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 19: WORD-PROGRAM ALGORITHM
1288 F19.0
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load Word
Address/Word
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
X can be VIL or VIH, but no other value
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
23
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 20: WAIT OPTIONS
1288 F20.0
Wait TBP,
TSCE, TSE
or TBE
Program/Erase
Initiated
Internal Timer Toggle Bit
Ye s
Ye s
No
No
Program/Erase
Completed
Does DQ6
match?
Read same
word
Data# Polling
Program/Erase
Completed
Program/Erase
Completed
Read word
Is DQ7 =
true data?
Read DQ7
Program/Erase
Initiated
Program/Erase
Initiated
24
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 21: SOFTWARE ID/CFI ENTRY COMMAND FLOWCHARTS
1288 F21.0
Load data: XXAAH
Address: 555H
Software Product ID Entry
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XX90H
Address: 555H
Wait TIDA
Read Software ID
Load data: XXAAH
Address: 555H
CFI Query Entry
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XX98H
Address: 555H
Wait TIDA
Read CFI data
Load data: XXAAH
Address: 555H
Sec ID Query Entry
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XX88H
Address: 555H
Wait TIDA
Read Sec ID
X can be VIL or VIH, but no other value
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
25
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 22: SOFTWARE ID/CFI EXIT COMMAND FLOWCHARTS
1288 F22.0
Load data: XXAAH
Address: 555H
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XXF0H
Address: 555H
Load data: XXF0H
Address: XXH
Return to normal
operation
Wait TIDA
Wait TIDA
Return to normal
operation
X can be VIL or VIH, but no other value
26
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
FIGURE 23: ERASE COMMAND SEQUENCE
1288 F23.0
Load data: XXAAH
Address: 555H
Chip-Erase
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XXAAH
Address: 555H
Wait TSCE
Chip erased
to FFFFH
Load data: XXAAH
Address: 555H
Sector-Erase
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX50H
Address: SAX
Load data: XXAAH
Address: 555H
Wait TSE
Sector erased
to FFFFH
Load data: XXAAH
Address: 555H
Block-Erase
Command Sequence
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX30H
Address: BAX
Load data: XXAAH
Address: 555H
Wait TBE
Block erased
to FFFFH
X can be VIL or VIH, but no other value
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
27
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
PRODUCT ORDERING INFORMATION
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Package Type
E = TSOP (type1, die up, 12mm x 20mm)
B1 = TFBGA (8mm x 10mm, 0.8mm pitch)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
90 = 90 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
640 = 64 Mbit
Voltage
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash Plus
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
SST 39 VF 6402B - 70 - 4C - EK E
XX XX XXXXB - XXX -XX-XXX X
28
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
Valid Combinations for SST39VF6401B
SST39VF6401B-70-4C-EK SST39VF6401B-70-4C-B1K
SST39VF6401B-70-4C-EKE SST39VF6401B-70-4C-B1KE
SST39VF6401B-90-4C-EK SST39VF6401B-90-4C-B1K
SST39VF6401B-90-4C-EKE SST39VF6401B-90-4C-B1KE
SST39VF6401B-70-4I-EK SST39VF6401B-70-4I-B1K
SST39VF6401B-70-4I-EKE SST39VF6401B-70-4I-B1KE
SST39VF6401B-90-4I-EK SST39VF6401B-90-4I-B1K
SST39VF6401B-90-4I-EKE SST39VF6401B-90-4I-B1KE
Valid Combinations for SST39VF6402B
SST39VF6402B-70-4C-EK SST39VF6402B-70-4C-B1K
SST39VF6402B-70-4C-EKE SST39VF6402B-70-4C-B1KE
SST39VF6402B-90-4C-EK SST39VF6402B-90-4C-B1K
SST39VF6402B-90-4C-EKE SST39VF6402B-90-4C-B1KE
SST39VF6402B-70-4I-EK SST39VF6402B-70-4I-B1K
SST39VF6402B-70-4I-EKE SST39VF6402B-70-4I-B1KE
SST39VF6402B-90-4I-EK SST39VF6402B-90-4I-B1K
SST39VF6402B-90-4I-EKE SST39VF6402B-90-4I-B1KE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
29
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
PACKAGING DIAGRAMS
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM
SST PACKAGE CODE: EK
1.05
0.95
0.70
0.50
18.50
18.30
20.20
19.80
0.70
0.50
12.20
11.80
0.27
0.17
0.15
0.05
48-tsop-EK-8
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
1.20
max.
1mm
0˚- 5˚
DETAIL
Pin # 1 Identifier
0.50
BSC
30
Data Sheet
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
©2006 Silicon Storage Technology, Inc. S71288-02-000 7/06
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM
SST PACKAGE CODE: B1K
TABLE 16: REVISION HISTORY
Number Description Date
00 Initial release Mar 2005
01 Clarified JEDEC software command compatibility on page 1 May 2005
02 Changed document phase from Preliminary Information to Data Sheet Jul 2006
A1 CORNER
BOTTOM VIEWTOP VIEW
8.00 ± 0.20
A1 CORNER
10.00 ± 0.20
H G F E D C B A
A B C D E F G H
6
5
4
3
2
1
0.45 ± 0.05
(48X)
0.80
4.00
0.80
5.60
48-tfbga-B1K-8x10-450mic-4
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm)
6
5
4
3
2
1
1mm
SIDE VIEW
SEATING PLANE 0.35 ± 0.05
1.10 ± 0.10
0.12
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com