74VHC541MTCX - FAIRCHILD SEMICONDUCTOR

August 1993

Revised May 2005

74VHC541 Octal Buffer/Line Driver with 3-STATE Outputs

74VHC541

Octal Buffer/Line Driver with 3-STATE Outputs

General Descript ion

The VHC541 is an advanced high-speed CMOS device

fabricated with silicon gate CMOS technology. It achieves

the high-speed operation similar to equivalent Bipolar

Schottky TTL while maintaining the CMOS low power dissi-

pation.

The VHC541 is an octal buffer/line driver designed to be

employed as memory and address drivers, clock drivers

and bus oriented transmitter/receivers.

This device is similar in fu nction to the VHC244 while pro-

viding flow-through architecture (inputs on opposite side

from outputs). This pinout arrangement makes this device

especially useful as an output port for microprocessors,

allowing ease of layout and greater PC board density.

An input protection circuit insures that 0V to 7V can be

applied to the inp ut pins wi thout rega rd to the supply volt-

age. This device can be used to interface 5V to 3V systems

and two supply systems suc h as battery backup . This cir-

cuit pr eve nts d evice de stru ction d ue to m ismat che d supply

and input voltages.

Features

■High Speed: tPD

3.5 ns (typ) at VCC

■Low power dissipation: ICC

A (max) at TA

■High noise immunity: VNIH

VNIL

28% VCC (min)

■Power down protection is provided on all inputs

■Low noise: VOLP

0.9V (typ)

■Pin and function compatible with 74HC541

Ordering Code:

Surface m ount pack ages are also avai lable on Tape and R eel. Specify by ap pending th e s uffix let t er “X” to the o rdering c ode.

Pb-Free package per JEDEC J-STD-020B.

Connection Diagram

Pin Descriptions

Logic Symbol

IEEE/IEC

Truth Table

HIGH Voltage Leve l X

Immaterial

LOW Voltage Lev el Z

High Impedance

Order Number Package Number Package Description

74VHC541M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74VHC541SJ M20D Pb-Free 20-Lead Small Outlin e Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC541N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pin Names Descriptions

OE1, OE23-STATE Output Enable Input s

I0 - I7Inputs

O0 - O73-STATE Outp uts

Inputs Outputs

OE1OE2I

LLHH

HXXZ

XHXZ

LLLL

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74VHC541

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: Absolute Maximum Ratings are values beyond which the device

may be damaged or have its useful life impaired. The databook specifica-

tions should be met, without exception, to ensure that the system design is

reliable over its power supply, temperature, and output/input loading vari-

ables. Fairchild does not recommend operation outside databook specifica-

tions.

Note 2: Unu s ed inputs m us t be held HIG H or LOW. They may no t float

DC Electrical Characteristics

Noise Characteristics

Note 3: Parameter guaranteed by design.

Supply Voltag e (VCC)



0.5V to



7.0V

DC Input Voltage (VIN)



0.5V to



7.0V

DC Output Voltage (VOUT)



0.5V to VCC



0.5V

Input Diode Current (IIK)



20 mA

Output Diode Current (IOK)

20 mA

DC Output Curren t (IOUT)

25 mA

DC VCC/GND Current (ICC)

75 mA

Stora ge Temperature (TSTG)



C to



150

Lead Temperature (TL)

(Soldering, 10 seconds) 260

Supply Voltage (VCC) 2.0V to



5.5V

Input Voltage (VIN)0V to



5.5V

Output Vo ltage (VOUT) 0V to VCC

Operating Temp erature (TOPR)



C to



Input Rise and Fall Time (tr, tf)

VCC

3.3V

0.3V 0

100 ns/V

VCC

5.0V

0.5V 0

20 ns/V

Symbol Parameter VCC

(V)



C to



CUnits Conditions

Min Typ Max Min Max

VIH HIGH Level Input 2.0 1.50 1.50 V

Voltage 3.0



5.5 0.7 VCC 0.7 VCC

VIL LOW Level Input 2.0 0.50 0.50 V

Voltage 3.0



5.5 0.3 VCC 0.3 VCC

VOH HIGH Level Output 2.0 1.9 2.0 1.9 VIN

VIH IOH



Voltage 3.0 2.9 3.0 2.9 V or VIL

4.5 4.4 4.5 4.4

3.0 2.58 2.48 VIOH



4 mA

4.5 3.94 3.80 IOH



8 mA

VOL LOW Level Output 2.0 0.0 0.1 0.1 VIN

VIH IOL

Voltage 3.0 0.0 0.1 0.1 V or VIL

4.5 0.0 0.1 0.1

3.0 0.36 0.44 VIOL

4 mA

4.5 0.36 0.44 IOL

8 mA

IOZ 3-STATE Output 5.5

0.25

2.5

AVIN

VIH or VIL

Off-State Current VOUT

VCC or GND

IIN Input Leakage Current 0



5.5

0.1

1.0

5.5V or GND

ICC Quiescent Supply Current 5.5 4.0 40.0

VCC or GND

Symbol Parameter VCC

(V)

CUnits Conditions

Typ Limits

VOLP Quiet Output Maximum Dynamic 5.0 0.9 1.2 V CL

50 pF

(Note 3) VOL

VOLV Quiet Output Minimum Dynamic 5.0



0.8



1.0 V CL

50 pF

(Note 3) VOL

VIHD Minimum HIGH Level Dynamic 5.0 3.5 V CL

50 pF

(Note 3) Input Voltage

VILD Maximum HIGH Level Dynamic 5.0 1.5 V CL

50 pF

(Note 3) Input Voltage

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74VHC541

AC Electrical Characteristics

Note 4: Parameter guaranteed by design. tOSLH

|tPLHmax



tPLHmin|; tOSHL

|tPHLmax



tPHLmin|.

Note 5: CPD is defined as the value of t he internal equivalent ca pac ita nc e w hich is c alculate d f rom the o perating c urrent consum pt ion without load. Average

operati ng c urrent ca n be obtained by the eq uat ion: ICC (OPR.)

CPD * VCC * fIN



ICC/8 (per bit).

Symbol Parameter VCC

(V)



C to



CUnits Conditions

Min Typ Max Min Max

tPLH Propagation Delay 3.3

0.3 5.0 7.0 1.0 8.5 ns CL

15 pF

tPHL Time 7.5 10.5 1.0 12.0 CL

50 pF

5.0

0.5 3.5 5.0 1.0 6.0 ns CL

15 pF

5.07.01.08.0 C

50 pF

tPZL 3-STATE Output 3.3

0.3 6.8 10.5 1.0 12.5 ns RL

1 k

15 pF

tPZH Enable Time 9.3 14.0 1.0 16.0 CL

50 pF

5.0

0.5 4.7 7.2 1.0 8.5 ns CL

15 pF

6.2 9.2 1.0 10.5 CL

50 pF

tPLZ 3-STATE 3.3

0.3 11.2 15.4 1.0 17.5 ns RL

1 k

50 pF

tPHZ Output 5.0

0.5 6.0 8.8 1.0 10.0 CL

50 pF

Disable Time

tOSLH Output to Output Skew 3.3

0.3 1.5 1.5 ns (Note 4) CL

50 pF

tOSHL 5.0

0.5 1.0 1.0 CL

50 pF

CIN Input Capacitance 4 10 10 pF VCC

Open

COUT Output Capacitance 6 pF VCC

5.0V

CPD Power Dissipation Capacitance 18 pF (Note 5)

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74VHC541

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

Package Number M20B

5 www.fairchildsemi.com

74VHC541

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74VHC541

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

7 www.fairchildsemi.com

74VHC541 Octal Buffer/Line Driver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N20A

Fairchild does not assum e any responsibility for use of any circuitry described, n o circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use provided in the l abe li ng, can be re a-

sonably expected to result in a significant injury to the

user.

2. A crit ical com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.