SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
D
LVTTL Interfaces Are 5-V Tolerant
D
High-Drive GTLP Outputs (100 mA)
D
LVTTL Outputs (–24 mA/24 mA)
D
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D
Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
D
Polarity Control Selects True or
Complementary Outputs
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D, DGV, OR PW PACKAGE
(TOP VIEW) RGY PACKAGE
(TOP VIEW)
116
89
2
3
4
5
6
7
15
14
13
12
11
10
GND
B1
GND
B2
GND
VREF
Y1
Y2
VCC
A1
A2
OEAB
OEBY
T/C BIAS V
ERC
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OEBY
Y1
Y2
VCC
A1
A2
OEAB
ERC
BIAS VCC
GND
B1
GND
B2
GND
VREF
T/C
description/ordering information
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
QFN – RGY Tape and reel SN74GTLP1394RGYR GP1394
SOIC D
Tube SN74GTLP1394D
GTLP1394
–40°C to 85°C
SOIC
–
D
Tape and reel SN74GTLP1394DR
GTLP1394
TSSOP – PW Tape and reel SN74GTLP1394PWR GP394
TVSOP – DGV Tape and reel SN74GTLP1394DGVR GP394
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OEC, TI, and TI-OPC are trademarks of Texas Instruments.
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
The SN74GTLP1394 is a high-drive, 2-bit, 3-wire bus transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent and inverted transparent modes of data
transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and
diagnostics monitoring. The device provides a high-speed interface between cards operating at LVTTL logic
levels and a backplane operating at GTLP signal levels, and is especially designed to work with the
Texas Instruments (TI) 1394 backplane physical-layer controllers. High-speed (about three times faster than
standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced
input threshold levels, improved differential input, OECcircuitry , and TI-OPC circuitry . Improved GTLP OEC
and TI-OPC circuitry minimizes bus-settling time and have been designed and tested using several backplane
models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load
impedance down to 11 Ω.
GTLP is the TI derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac
specification of the SN74GTLP1394 is given only at the preferred higher noise margin GTLP, but the user has
the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF
= 1 V) signal levels.
Normally , the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS V CC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly
terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This
improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
functional description
The output-enable (OEAB) input controls the activity of the B port. When OEAB is low, the B-port outputs are
active. When OEAB is high, the B-port outputs are disabled.
Separate LVTTL input and output pins provide a feedback path for control and diagnostics monitoring. The
OEBY input controls the Y outputs. When OEBY is low, the Y outputs are active. When OEBY is high, the
Y outputs are disabled.
The polarity-control (T/C) input is provided to select polarity of data transmission in both directions. When T/C
is high, data transmission is true, and A data goes to the B bus and B data goes to the Y bus. When T/C is low ,
data transmission is complementary, and inverted A data goes to the B bus and inverted B data goes to the
Y bus.
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
OUTPUT CONTROL
INPUTS
OUTPUT
MODE
T/C OEAB OEBY
OUTPUT
MODE
X H H Z Isolation
H L H A data to B bus
True trans
p
arent
HH L B data to Y bus
True
transparent
H L L A data to B bus, B data to Y bus T rue transparent with
feedback path
L L H Inverted A data to B bus
Inverted trans
p
arent
LH L Inverted B data to Y bus
Inverted
transparent
L L L Inverted A data to B bus,
Inverted B data to Y bus Inverted transparent
with feedback path
OUTPUT EDGE-RATE CONTROL (ERC)
INPUT ERC OUTPUT
LOGIC
LEVEL NOMINAL
VOLTAGE B-PORT
EDGE RATE
L GND Slow
HVCC Fast
logic diagram (positive logic)
OEAB
T/C
OEBY
7
9
1
ERC 8
A1 5
Y1 2
VREF 10
A2 6
Y2 3
B1
14
B2
12
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC and BIAS VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1): A inputs, ERC, and control inputs –0.5 V to 7 V. . . . . . . . . . . . . . . . . . .
B port and VREF –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1):Y outputs –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: Y outputs 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, IO (see Note 2) 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4): RGY package 39°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Notes 5 through 8)
MIN NOM MAX UNIT
VCC,
BIAS VCC Supply voltage 3.15 3.3 3.45 V
VTT
Termination voltage
GTL 1.14 1.2 1.26
V
V
TT
Termination
voltage
GTLP 1.35 1.5 1.65
V
VREF
Reference voltage
GTL 0.74 0.8 0.87
V
V
REF
Reference
voltage
GTLP 0.87 1 1.1
V
VI
In
p
ut voltage
B port VTT
V
V
I
Input
voltage
Except B port VCC 5.5
V
B port VREF+0.05
VIH High-level input voltage ERC VCC–0.6 VCC 5.5 V
Except B port and ERC 2
B port VREF–0.05
VIL Low-level input voltage ERC GND 0.6 V
Except B port and ERC 0.8
IIK Input clamp current –18 mA
IOH High-level output current Y outputs –24 mA
IOL
Low level out
p
ut current
Y outputs 24
mA
I
OL
Low
-
level
output
current
B port 100
mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 ns/V
∆t/∆VCC Power-up ramp rate 20 µs/V
TAOperating free-air temperature –40 85 °C
NOTES: 5. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable, but generally, GND is connected first.
7. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
8. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction
and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to
minimize current drain.
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 3.15 V, II = –18 mA –1.2 V
VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC–0.2
VOH Y outputs
VCC 315V
IOH = –12 mA 2.4 V
V
CC = 3.15 VIOH = –24 mA 2
VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2
Y outputs
VCC = 3 15 V
IOL = 12 mA 0.4
V
CC =
3
.
15
V
IOL = 24 mA 0.5
V
OL IOL = 10 mA 0.2
V
B port VCC = 3.15 V IOL = 64 mA 0.4
IOL = 100 mA 0.55
IIA-port and
control inputs VCC = 3.45 V VI = 0 to 5.5 V ±10 µA
Y outputs
VCC = 3 45 V
VO = VCC 10
µA
OZH
B port
V
CC =
3
.
45
V
VO = 1.5 V 10 µ
A
IOZL‡Y outputs and
B port VCC = 3.45 V, VO = GND –10 µA
Ytt d
VCC
=
3.45 V, IO
=
0,
Outputs high 20
ICC Y outputs and
B
p
ort
VCC
=
3
.
45
V
,
IO
=
0
,
VI (A-port or control inputs) = VCC or GND, Outputs low 20 mA
B
ort
VI (B port) = VTT or GND Outputs disabled 20
∆ICC§VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND 1.5 mA
A-port inputs
VI=315Vor0
3.5 4.5 p
F
iControl inputs
V
I =
3
.
15
V
or
0
4 5
pF
CoY outputs VO = 3.15 V or 0 4.5 5 pF
Cio B port VO = 1.5 V or 0 9 10.5 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡For I/O ports, the parameters IOZH and IOZL include the input leakage current.
§This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
hot-insertion specifications for A inputs and Y outputs over recommended operating free-air
temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 5.5 V 10 µA
IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = 0 ±30 µA
IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = 0 ±30 µA
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 1.5 V 10 µA
IOZPU VCC = 0 to 1.5 V, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA
IOZPD VCC = 1.5 V to 0, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA
ICC (BIAS VCC)
VCC = 0 to 3.15 V
BIAS VCC =315Vto345V
VO(B
p
ort)=0to15V
5 mA
I
CC
(BIAS
V
CC
)
VCC = 3.15 V to 3.45 V
BIAS
V
CC =
3
.
15
V
to
3
.
45
V
,
V
O
(B
port)
=
0
to
1
.
5
V
10 µA
VOVCC = 0, BIAS VCC = 3.3 V, IO = 0 0.95 1.05 V
IOVCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V –1µA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT) EDGE RATE†MIN TYP‡MAX UNIT
tPLH
A
B
Slow
3.3 5.9
ns
tPHL
A
B
Slow
3 6.6
ns
tPLH
A
B
Fast
2.5 5.2
ns
tPHL
A
B
Fast
1.9 4.8
ns
tPLH
A
Y
Slow
5.4 9
ns
tPHL
A
Y
Slow
4.9 8.6
ns
tPLH
A
Y
Fast
4.3 7.9
ns
tPHL
A
Y
Fast
3.9 7.5
ns
tPLH
T/C
B
Slow
3 6.5
ns
tPHL
T/C
B
Slow
3.1 6.6
ns
tPLH
T/C
B
Fast
2.3 5.6
ns
tPHL
T/C
B
Fast
1.7 4.9
ns
ten
OEAB
B
Slow
3.2 6.2
ns
tdis
OEAB
B
Slow
3.2 6.4
ns
ten
OEAB
B
Fast
1.9 5.3
ns
tdis
OEAB
B
Fast
2.4 5.7
ns
t
Rise time B out
p
uts (20% to 80%)
Slow 2.7
ns
t
r
Rise
time
,
B
outputs
(20%
to
80%)
Fast 1.5
ns
tf
Fall time B out
p
uts (80% to 20%)
Slow 3.2
ns
t
f
Fall
time
,
B
outputs
(80%
to
20%)
Fast 2.1
ns
tPLH
B
Y
1.6 4.6
ns
tPHL
B
Y
–1.4 3.9
ns
tPLH
T/C
Y
1 4.5
ns
tPHL
T/C
Y
–1.2 4.1
ns
ten
OEBY
Y
1 4.1
ns
tdis
OEBY
Y
–1.3 4.6
ns
†Slow (ERC = GND) and Fast (ERC = VCC)
‡All typical values are at VCC = 3.3 V, TA = 25°C.
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR Y OUTPUTS
S1 Open
GND
500 Ω
500 Ω
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6 V
GND
tPLH tPHL
Output
Control
Output
W aveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH – 0.3 V
≈0 V
Input
3 V
3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A input to B port)
Output
1.5 V
Test
Point
CL = 30 pF
(see Note A)
From Output
Under Test
12.5 Ω
LOAD CIRCUIT FOR B OUTPUTS
0 V
VOH
VOL
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to Y output)
Output
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
tPLH tPHL
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1 V 1 V
1 V 1 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A input)
Figure 1. Load Circuits and Voltage Waveforms
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
Drvr
1.5 V
.25”1”
1”1”
1.5 V
1”1”
1”.25”
Rcvr Rcvr Rcvr
Figure 2. High-Drive Test Backplane
Slot 1 Slot 2 Slot 19 Slot 20
Conn. Conn. Conn. Conn.
ZO = 50 Ω
22Ω
22Ω
Figure 3. High-Drive RLC Network
From Output
Under Test Test
Point
1.5 V
CL = 18 pF
11 Ω
LL = 14 nH
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT) EDGE RATE†TYP‡UNIT
tPLH
A
B
Slow
4.2
tPHL
A
B
Slow
4.2
tPLH
A
B
Fast
3.6
tPHL
A
B
Fast
3.6
tPLH
A
Y
Slow
5.8
tPHL
A
Y
Slow
5.8
tPLH
A
Y
Fast
5.2
tPHL
A
Y
Fast
5.2
tPLH
T/C
B
Slow
4.4
tPHL
T/C
B
Slow
4.4
tPLH
T/C
B
Fast
3.8
tPHL
T/C
B
Fast
3.8
ten
OEAB
B
Slow
4.2
tdis
OEAB
B
Slow
4.3
ten
OEAB
B
Fast
3.6
tdis
OEAB
B
Fast
3.3
t
Rise time B out
p
uts (20% to 80%)
Slow 2
t
r
Rise
time
,
B
outputs
(20%
to
80%)
Fast 1.2
tf
Fall time B out
p
uts (80% to 20%)
Slow 2.5
t
f
Fall
time
,
B
outputs
(80%
to
20%)
Fast 1.8
†Slow (ERC = GND) and Fast (ERC = VCC)
‡All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
operational description
The GTLP1394 is designed specifically for use with the TI 1394 backplane layer controller family to transmit
the 1394 backplane serial bus across parallel backplanes. But, it is a versatile 2-bit device that also is being used
to provide multiple single-bit clocks or ATM read and write clock in multislot parallel backplane applications.
The 1394–1995 is an IEEE designation for a high-performance serial bus. This serial bus defines both a
backplane (e.g., GTLP, VME, FB+, CPCI, etc.) physical layer and a point-to-point cable-connected virtual bus.
The backplane version operates at 25, 50, or 100 Mbps, whereas the cable version supports data rates of 100,
200, and 400 Mbps. Both versions are compatible at the link layer and above. The interface standard defines
the transmission method, media in the cable version, and protocol. The primary application of the cable version
is the interconnection of digital A/V equipment and integration of I/O connectivity at the back panel of personal
computers using a low-cost, scalable, high-speed serial interface. The primary application of the backplane
version is to provide a robust control interface to each daughter card. The 1394 standard also provides new
services, such as real-time I/O and live connect/disconnect capability for external devices.
electrical
The 1394 standard is a transaction-based packet technology for cable- or backplane-based environments. Both
chassis and peripheral devices can use this technology. The 1394 serial bus is organized as if it were memory
space interconnected between devices, or as if devices resided in slots on the main backplane. Device
addressing is 64 bits wide, partitioned as ten bits for bus ID, six bits for node ID, and 48 bits for memory
addresses. The result is the capability to address up to 1023 buses, with each having up to 63 nodes, each with
281 terabytes of memory. Memory-based addressing, rather than channel addressing, views resources as
registers or memory that can be accessed with processor-to-memory transactions. Each bus entity is termed
a unit, to be individually addressed, reset, and identified. Multiple nodes can reside physically in a single module,
and multiple ports can reside in a single node.
Some key features of the 1394 topology are multimaster capabilities, live connect/disconnect (hot plugging)
capability, genderless cabling connectors on interconnect cabling, and dynamic node address allocation as
nodes are added to the bus. A maximum of 63 nodes can be connected to one network.
The cable-based physical interface uses dc-level line states for signaling during initialization and arbitration.
Both environments use dominant mode addresses for arbitration. The backplane environment does not have
the initialization requirements of the cable environment because it is a physical bus and does not contain
repeaters. Due to the differences, a backplane-to-cable bridge is required to connect these two environments.
The signals transmitted on both the cable and backplane environments are NRZ with data-strobe (DS)
encoding. DS encoding allows only one of the two signal lines to change each data bit-period, essentially
doubling the jitter tolerance, with very little additional circuitry overhead in the hardware.
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
protocol
Both asynchronous and isochronous data transfers are supported. The asynchronous format transfers data and
transaction-layer information to an explicit address. The isochronous format broadcasts data based on channel
numbers rather than specific addressing. Isochronous packets are issued on the average of each 125 µs in
support of time-sensitive applications. Providing both asynchronous and isochronous formats on the same
interface allows both non-real-time and real-time critical applications on the same bus. The cable environment’s
tree topology is resolved during a sequence of events, triggered each time a new node is added or removed
from the network. This sequence starts with a bus reset phase, where previous information about a topology
is cleared. The tree ID sequence determines the actual tree structure, and a root node is dynamically assigned,
or it is possible to force a particular node to become the root. After the tree is formed, a self-ID phase allows
each node on the network to identify itself to all other nodes. During the self-ID process, each node is assigned
an address. After all the information has been gathered on each node, the bus goes into an idle state, waiting
for the beginning of the standard arbitration process.
The backplane physical layer shares some commonality with the cable physical layer. Common functions
include: bus state determination, bus access protocols, encoding and decoding functions, and synchronization
of received data to a local clock.
backplane features
D
25-, 50-, and 100-Mbps data rates for backplane environments
D
Live connection/disconnection possible without data loss or interruption.
D
Configuration ROM and status registers supporting plug and play
D
Multidrop or point-to-point topologies supported.
D
Specified bandwidth assignments for real-time applications
applicability and typical application for IEEE 1394 backplane
The 1394 backplane serial bus (BPSB) plays a supportive role in backplane systems, specifically GTLP,
FutureBus+, VME64, and proprietary backplane bus systems. This supportive role can be grouped into three
categories:
D
Diagnostics
–Alternate control path to the parallel backplane bus
–Test, maintenance, and troubleshooting
–Software debug and support interface
D
System enhancement
–Fault tolerance
–Live insertion
–CSR access
–Auxiliary 2-bit bus with a 64-bit address space to the parallel backplane bus
D
Peripheral monitoring
–Monitoring of peripherals (disk drives, fans, power supplies, etc.) in conjunction with another externally
wired monitor bus, such as defined by the Intelligent Platform Management Interface (IPMI).
The 1394 backplane physical layer (PHY) and the SN74GTLP1394 provide a cost-effective way to add
high-speed 1394 connections to every daughter card in almost any backplane. More information on the
backplane physical layer devices and how to implement the 1394 standard in backplane and cable applications
can be found at: www.ti.com/sc/1394.
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
SN74GTLP1394 interface with the TSB14AA1 1394 backplane PHY
D
A1, B1, and Y1 are used for the PHY data signals.
D
A2, B2, and Y2 are used for the PHY strobe signals.
D
PHY N_OEB_D or OCDOE connects to OEAB, which controls the PHY transmit signals.
D
OEBY is connected to GND since the transceiver always must be able to receive signals from the backplane
and relay them to the PHY.
D
T/C is connected to GND for inverted signals.
D
VCC is nominal 3.3 V.
D
BIAS VCC is connected to nominal 3.3 V to support live insertion.
D
VREF normally is 2/3 of VTT.
D
ERC normally is connected to GND for slow edge-rate operation because frequencies of only 50 MHz
(S100) and 25 MHz (S50) are required.
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
logical representation
1394
Link-
Layer
Controller
Host
Interface
D0 – D1
CTL0 – CTL1
LREQ
SCLK
1394
Backplane
Physical-
Layer
Controller
TSB14AA1
3.3-V VCC
BPdata
BPstrb
Tdata
Rdata
Rstrb
Tstrb
OCDOE
A1
Y1
A2
Y2
GND OEBY
OEAB
GNDT/C
B1
B2
SN74GTLP1394
2
2
1 kΩ
TDOE
VCC
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2003
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
physical representation
PHY
Node
Module
PHY
Node
Module
STRB
DATA
GTLP1394 Transceiver
1394 Backplane PHY
1394 Link-Layer Controller
Host Microprocessor
Terminators
Backplane Trace
Connectors
VME/FB+/CPCI or
GTLP Transceivers
PHY
Node
Module
RTT
VTT VTT
RTT
B2
B1
A2 Y2 A1 Y1
STRB DATA
64-Bit Data Bus 32- to 64-Bit Address Bus
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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