For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
+1 978-250-3343 tel • +1 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: adcsupport@hittite.com
A / D Converters - sMt
0
0 - 23
HMCAD1101
v0 4.0114
OCTAL 13/12-BIT 65 MSPS
A/D CONVERTER
pass pole with these resistors, and the values must
thereforebedeterminedbasedontherequirementto
thehigh-passcut-offfrequency.
NotethatStartUpTimefromSleepModeandPower
Down Mode will beaffectedby thislterasthe time
requiredtochargetheseriescapacitorsisdependent
ontheltercut-offfrequency.
Iftheinputsignalhasalongtravelingdistance,andthe
kick-backsfromtheADCarenoteffectivelyterminated
atthesignalsource,theinputnetworkofgure16can
beused.Thecongurationingure16isdesignedto
attenuatethe kickback fromtheADC andtoprovide
aninputimpedancethatlooksasresistiveaspossible
forfrequenciesbelowNyquist.
Figure 15. Alternative input network
Valuesoftheseriesinductorwillhoweverdependon
boarddesignandconversionrate.Insomeinstances
a shunt capacitor in parallel with the termination
resistor (e.g. 33pF) may improve ADC performance
further. This capacitor attenuate the ADC kick-back
evenmore,andminimizethekickstravelingtowards
thesource.However,theimpedancematchseeninto
thetransformerbecomesworse.
ClockInputandJitterConsiderations
Typically high-speed ADCs use both clock edges to
generateinternaltimingsignals.InHMCAD1101only
therisingedgeoftheclockisused.Hence,inputclock
dutycyclesbetween20%and80%areacceptable.
Theinputclockcanbesuppliedinavarietyofformats.
TheclockpinsareAC-coupledinternally,henceawide
commonmodevoltagerangeisaccepted.Differential
clock sources such as LVDS, LVPECLordifferential
sinewavecanbeconnecteddirectlytotheinputpins.
ForCMOSinputs,theCLKNpinshouldbeconnected
to ground, and the CMOS clock signal should be
connected to CLKP. For differential sine wave clock
input the amplitude must be at least ± 0.8 Vpp. No
additionalcongurationisneededtosetuptheclock
sourceformat.
Thequalityoftheinputclockisextremelyimportantfor
high-speed,high-resolutionADCs.Thecontributionto
SNRfromclockjitterwithafullscalesignalatagiven
frequencyisshowninequation1.
SNRjitter=20·log(2·π·ƒIN·єt)(1)
wherefINis thesignal frequency, and εtis thetotal
rms jitter measured inseconds. The rms jitter is the
totalofalljittersourcesincludingtheclockgeneration
circuitry,clockdistributionandinternalADCcircuitry.
Forapplications wherejittermaylimittheobtainable
performance,itisofutmostimportancetolimittheclock
jitter.Thiscanbeobtainedbyusingpreciseandstable
clockreferences(e.g.crystaloscillatorswithgoodjitter
specications) and make sure the clock distribution
is well controlled. It might be advantageous to use
analogpowerandgroundplanestoensurelownoise
onthesuppliestoallcircuitryintheclockdistribution.
Itisofutmostimportancetoavoidcrosstalkbetween
the ADC output bits and the clock and between the
analoginputsignalandtheclocksincesuchcrosstalk
oftenresultsinharmonicdistortion.
Thejitterperformanceisimprovedwithreducedrise
andfalltimesoftheinputclock.Hence,optimumjitter
performanceisobtainedwithLVDSorLVPECLclock
withfastedges.CMOSandsinewaveclockinputswill
resultinslightlydegradedjitterperformance.
If the clock is generated by other circuitry, it should
bere-timed withalow jittermasterclockas the last
operationbeforeitisappliedtotheADCclockinput.
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