Timing Generator for Frame Readout CCD Image Sensor
Description
The CXD2470R is a timing generator IC which
generates the timing pulses for performing frame
readout using the ICX224,ICX284,ICX202 and ICX232
CCD image sensor.
Features
•Base oscillation frequency 24.00 to 36.00MHz (max.)
•High-speed/low-speed shutter function
•Supports quadruple-speed readout drive
•Horizontal driver for CCD image sensor
•Vertical driver for CCD image sensor
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX224 (Type 1/2, 2020K pixels)
ICX284 (Type 1/2.7, 2020K pixels)
ICX202 (Type 1/3, 1250K pixels)
ICX232 (Type 1/3.6, 1250K pixels)
Pin Configuration
Absolute Maximum Ratings
•Supply voltage VDD VSS – 0.3 to +7.0 V
VL–10.0 to VSS V
VHVL– 0.3 to +26.0 V
•Input voltage VIVSS – 0.3 to VDD + 0.3 V
•Output voltage VO1 VSS – 0.3 to VDD + 0.3 V
VO2 VL– 0.3 to VSS + 0.3 V
VO3 VL– 0.3 to VH+ 0.3 V
•Operating temperature
Topr –20 to +75 °C
•Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
•Supply voltage VDDb 3.0 to 5.5 V
VDDa, VDDc, VDDd
3.0 to 3.6 V
VM0.0 V
VH14.5 to 15.5 V
VL–7.0 to –8.0 V
•Operating temperature
Topr –20 to +75 °C
– 1 – E98Y31E1Z
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXD2470R
48 pin LQFP (Plastic)
∗Groups of pins enclosed in the figure indicate
sections for which power supply separation is
possible.
123 4 5 6 7 8 9 10 11 12
13
14
15
16
17
18
19
20
21
22
23
24
25
262728
29
30
31
323334
35
36
37
38
39
40
41
42
43
44
45
46
47
48 H2
VDD3
VDD4
XSHP
XSHD
XRS
PBLK
CLPDM
VSS4
OBCLP
ADCLK
VSS5
CKO
CKI
OSCO
OSCI
VDD5
MCKO
SSI
SCK
SEN
VDI
HDI
VSS6
H1
VSS3
VSS2
RG
VDD2
EBCKSM
VDD1
WEN
ID
DSGAT
RST
VSS1
TEST2
SUB
V3B
VL
V3A
V1B
VH
V1A
V4
V2
VM
TEST1
– 2 –
CXD2470R
Block Diagram
3 2 37 48 35 34
39
44
43
41
5
4
24
23
22
20
19
21
181716
15
10
9
81113
12
14
28
27
26
25
30
7
29
1
V1B
V2
V3A
V1A
WEN
ID
VSS5
ADCLK
OBCLP
CLPDM
PBLK
VSS4
XRS
XSHD
XSHP
VDD4
VSS2
RG
VDD2
VSS3
H2
H1
VDD3
VDI
HDI
TEST2
TEST1
RST
DSGAT
VSS1
36
VSS6
VDD5
VDD1
MCKO
CKO
CKI
OSCO
OSCI
Pulse Generator
45
38
42
47
40
46
VL
VM
VH
SUB
V4
V3B
31
32
33
SEN
SCK
SSI
Register
V Driver
6
EBCKSM
1/2
– 3 –
CXD2470R
Pin Description
GND
Internal system reset input. High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input/No protective diode on power supply side
Control input used to stop pulse generation.
High: Normal operation, Low: Stop control
Schmitt trigger input/No protective diode on power supply side
Vertical direction line identification pulse output.
Memory write timing pulse output.
CHKSUM enable. High: Sum check invalid, Low: Sum check valid
With pull-down resistor
3.3V power supply. (Power supply for common logic block)
3.3V power supply. (Power supply for RG)
CCD reset gate pulse output.
GND
GND
CCD horizontal register clock output.
CCD horizontal register clock output.
3.3 to 5.0V power supply. (Power supply for H1/H2)
3.3V power supply. (Power supply for CDS block)
CCD precharge level sample-and-hold pulse output.
CCD data level sample-and-hold pulse output.
Sample-and-hold pulse output for analog/digital conversion phase alignment.
Pulse output for horizontal and vertical blanking period pulse cleaning.
CCD dummy signal clamp pulse output.
GND
CCD optical black signal clamp pulse output.
Clock output for analog/digital conversion IC.
Logical phase adjustment possible using the serial interface data.
GND
Inverter output.
Inverter input.
Inverter output for oscillation. When not used, leave open or connect a capacitor.
Inverter input for oscillation. When not used, fix low.
3.3V power supply. (Power supply for common logic block)
System clock output for signal processing IC.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS1
RST
DSGAT
ID
WEN
EBCKSM
VDD1
VDD2
RG
VSS2
VSS3
H1
H2
VDD3
VDD4
XSHP
XSHD
XRS
PBLK
CLPDM
VSS4
OBCLP
ADCLK
VSS5
CKO
CKI
OSCO
OSCI
VDD5
MCKO
—
I
I
O
O
I
—
—
O
—
—
O
O
—
—
O
O
O
O
O
—
O
O
—
O
I
O
I
—
O
Pin
No. Symbol I/O Description
– 4 –
CXD2470R
Serial interface data input for internal mode settings.
Schmitt trigger input/No protective diode on power supply side
Serial interface clock input for internal mode settings.
Schmitt trigger input/No protective diode on power supply side
Serial interface strobe input for internal mode settings.
Schmitt trigger input/No protective diode on power supply side
Vertical sync signal input. Schmitt trigger input
Horizontal sync signal input. Schmitt trigger input
GND
IC test pin 1; normally fixed to GND. With pull-down resistor
GND (GND for vertical driver)
CCD vertical register clock output.
CCD vertical register clock output.
CCD vertical register clock output.
15.0V power supply. (Power supply for vertical driver)
CCD vertical register clock output.
CCD vertical register clock output.
–7.5V power supply. (Power supply for vertical driver)
CCD vertical register clock output.
CCD electronic shutter pulse output.
IC test pin 2; normally fixed to GND. With pull-down resistor
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SSI
SCK
SEN
VDI
HDI
VSS6
TEST1
VM
V2
V4
V1A
VH
V1B
V3A
VL
V3B
SUB
TEST2
I
I
I
I
I
—
I
—
O
O
O
—
O
O
—
O
O
I
Pin
No. Symbol I/O Description
– 5 –
CXD2470R
Electrical Characteristics
DC Characteristics (Within the recommended operating conditions)
VDD2
VDD3
VDD4
VDD1, VDD5
RST, DSGAT,
SSI, SCK,
SEN,
EBCKSM
TEST1,
TEST2
VDI, HDI
H1, H2
RG
XSHP, XSHD,
XRS, PBLK,
OBCLP,
CLPDM,
ADCLK
CKO, MCKO
V1A, V1B,
V3A, V3B,
V2, V4
SUB
VDDa
VDDb
VDDc
VDDd
Vt+
Vt–
VIH1
VIL1
VIH2
VIL2
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
IOL
IOM1
IOM2
IOH
IOSL
IOSH
3.0
3.0
3.0
3.0
0.8VDDd
0.7VDDd
0.7VDDd
VDDb – 0.8
VDDb – 0.8
VDDc – 0.8
VDDd – 0.8
10.0
5.0
5.4
3.3
3.3
3.3
3.3
3.6
5.5
3.6
3.6
0.2VDDd
0.3VDDd
0.3VDDd
0.4
0.4
0.4
0.4
–5.0
–7.2
–4.0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
Feed current where IOH = –22.0mA
Pull-in current where IOL = 14.4mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –10.4mA
Pull-in current where IOL = 7.2mA
V1A/B, V2, V3A/B, V4 = –8.25V
V1A/B, V2, V3A/B, V4 = –0.25V
V1A/B, V3A/B = 0.25V
V1A/B, V3A/B = 14.75V
SUB = –8.25V
SUB = 14.75V
Supply voltage 1
Supply voltage 2
Supply voltage 3
Supply voltage 4
Input voltage 1∗1
Input voltage 2∗2
Input voltage 3
Output voltage 1
Output voltage 2
Output voltage 3
Output voltage 4
Output current 1
Output current 2
Item Pins
Symbol
Conditions Min. Typ. Max. Unit
∗1These input pins are Schmitt trigger inputs and do not have protective diodes on the internal power supply
side.
∗2These input pins have internal pull-down resistors.
Note) The above table indicates the condition for 3.3V drive.
– 6 –
CXD2470R
Inverter I/O Characteristics for Oscillation (Within the recommended operating conditions)
Item
Logical Vth
Input
voltage
Output
voltage
Feedback
resistor
Oscillation
frequency
Pins
OSCI
OSCI
OSCO
OSCI,
OSCO
OSCI,
OSCO
Symbol
LVth
VIH
VIL
VOH
VOL
RFB
f
Conditions
Feed current where IOH = –3.6mA
Pull-in current where IOL = 2.4mA
VIN = VDDd or VSS
Min.
0.7VDDd
VDDd – 0.8
500k
20
Typ.
VDDd/2
2M
Max.
0.3VDDd
0.4
5M
50
Unit
V
V
V
V
V
Ω
MHz
Item
Logical Vth
Input
voltage
Input
amplitude
Pins
CKI
Symbol
LVth
VIH
VIL
VIN
Conditions
fmax 50MHz sine wave
Min.
0.7VDDd
0.3
Typ.
VDDd/2
Max.
0.3VDDd
Unit
V
V
V
Vp-p
Item
Rise time
Fall time
Output noise voltage
Symbol
TTLM
TTMH
TTLH
TTML
TTHM
TTHL
VCLH
VCLL
VCMH
VCML
Conditions
VL to VM
VM to VH
VL to VH
VM to VL
VH to VM
VH to VL
Min.
200
200
30
200
200
30
Typ.
350
350
60
350
350
60
Max.
500
500
90
500
500
90
1.0
1.0
1.0
1.0
Unit
ns
ns
ns
ns
ns
ns
V
V
V
V
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude
is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics (VH= 15.0V, VM= GND, VL= –7.5V)
Notes) 1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more)
between each power supply pin (VH, VL) and GND.
3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image
sensor.
– 7 –
CXD2470R
Switching Waveforms
V1A (V1B, V3A, V3B)
V2 (V4)
SUB
TTMH TTHM VH
VM
VL
VM
VL
VH
VL
90%
10%
90%
10%
TTLM
TTLM
90%
10%
90%
10%
TTLH TTHL
90%90%
10% 10%
TTML
90%
10%
TTML
90%
10%
Waveform Noise
VCMH
VCML
VH
VL
VCLH VCLL
– 8 –
CXD2470R
Measurement Circuit
1 2 3 4 5 6 7 8 9 10 11 12
13
14
15
16
17
18
19
20
21
22
23
24
25
262728
29
30
31
323334
35
36
37
38
39
40
41
42
43
44
45
46
47
48
VDI CKI
C6
C6
C6
C6
C6
C6
C6
C6
C6
C5
C5C4
C3
CXD2470R
Serial interface data
HDI
+3.3V
–7.5V
+15.0V
C2
C2 C2
C2
C2
R1
R1
R1
R2
R1
R1 R1
C2
C2
C2
C2
C2
C2
C2
C2
C2
C1
C1
C1
C1 C1
C1
C2
C1 3300pF C2 560pF C3 820pF C4 30pF C5 180pF C6 10pF
R1 30ΩR2 10Ω
– 9 –
CXD2470R
AC Characteristics
AC characteristics between the serial interface clocks
SSI 0.2VDDd
0.2VDDd
0.8VDDd
ts2
th1ts1
ts3
0.8VDDd
0.8VDDd
SCK
SEN
SEN
Symbol
ts1
th1
ts2
ts3
Definition
SSI setup time, activated by the rising edge of SCK
SSI hold time, activated by the rising edge of SCK
SCK setup time, activated by the rising edge of SEN
SEN setup time, activated by the rising edge of SCK
Min. Typ. Max.
20
20
80
20
Unit
ns
ns
ns
ns
Serial interface clock internal loading characteristics (1)
(Within the recommended operating conditions)
th1
Enlarged view
Example: During frame mode
0.2VDDd
ts1
0.2VDDd
V1A
VDI
HDI
HDI
V1A
SEN 0.8VDDd
Symbol
ts1
th1
Definition
SEN setup time, activated by the falling edge of HDI
SEN hold time, activated by the falling edge of HDI
Min. Typ. Max.
0
102
Unit
ns
µs
∗Be sure to maintain a constantly high SEN logic level near the falling edge of the HDI in the horizontal period
during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
– 10 –
CXD2470R
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD2470R at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD2470R and controlled at the rising edge of SEN. See "Description of Operation".
0.8VDDd
SEN
Output signal tpdPULSE
Symbol
tpdPULSE
Definition
Output signal delay, activated by the rising edge of SEN
Min. Typ. Max.
1005
Unit
ns
(Within the recommended operating conditions)
Serial interface clock internal loading characteristics (2)
th1
Enlarged view
0.2VDDd
ts1
0.2VDDd
VDI
HDI
VDI
HDI
SEN 0.8VDDd
Example: During frame mode
Symbol
ts1
th1
Definition
SEN setup time, activated by the falling edge of VDI
SEN hold time, activated by the falling edge of VDI
Min. Typ. Max.
0
200
Unit
ns
ns
∗Be sure to maintain a constantly high SEN logic level near the falling edge of VDI.
(Within the recommended operating conditions)
– 11 –
CXD2470R
RST 0.2VDDd tw1
0.8VDDd
VDI, HDI
MCKO
ts1 th1
0.2VDDd
0.8VDDd
0.2VDDd
RST loading characteristics
Symbol
tw1
Definition
RST pulse width
Min. Typ. Max.
35
Unit
ns
(Within the recommended operating conditions)
VDI and HDI loading characteristics
Symbol
ts1
th1
Definition
VDI and HDI setup time, activated by the rising edge of MCKO
VDI and HDI hold time, activated by the rising edge of MCKO
Min. Typ. Max.
20
5
Unit
ns
ns
MCKO load capacitance = 10pF∗1
(Within the recommended operating conditions)
DSGAT
H1, H2, RG, XSHP, XSHD, XRS,
ADCLK, PBLK, CLPDM, OBCLP
tpDSGAT
0.2VDDd
0.2VDDd
Output timing characteristics using DSGAT
H1 and H2 load capacitance = 180pF, RG load capacitance = 30pF,
XSHP, XSHD, XRS, PBLK, CLPDM, OBCLP and ADCLK load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpDSGAT
Definition
Time until the above outputs go low after the fall of DSGAT
Min. Typ. Max.
100
Unit
ns
– 12 –
CXD2470R
0.8VDDd
MCKO
WEN, ID tpd1
WEN and ID load capacitance = 10pF (Within the recommended operating conditions)
Symbol
tpd1
Definition
Time until the above outputs change after the rise of MCKO
Min. Typ. Max.
6020
Unit
ns
Output variation characteristics
– 13 –
CXD2470R
Description of Operation
Pulses output from the CXD2470R are controlled mainly by the RST and DSGAT pins and by the serial
interface data. The Pin Status Table is shown below, and the details of serial interface control are described on
the following pages.
Pin Status Table
Note) ACT means that the circuit is operating, and DIS means that loading is stopped.
L indicates a low output level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 42), VM (Pin 38) and VL (Pin 45),
respectively, in the controlled status.
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS1
RST
DSGAT
ID
WEN
EBCKSM
VDD1
VDD2
RG
VSS2
VSS3
H1
H2
VDD3
VDD4
XSHP
XSHD
XRS
PBLK
CLPDM
VSS4
OBCLP
ADCLK
VSS5
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
L
L
ACT
L
L
L
L
L
L
L
L
L
L
ACT
ACT
L
L
ACT
L
L
L
L
L
L
L
L
L
L
ACT
L
ACT
ACT
ACT
L
L
L
L
L
L
L
L
L
L
L
ACT
L
L
ACT
ACT
ACT
ACT
ACT
ACT
ACT
H
H
H
ACT
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
CKO
CKI
OSCO
OSCI
VDD5
MCKO
SSI
SCK
SEN
VDI
HDI
VSS6
TEST1
VM
V2
V4
V1A
VH
V1B
V3A
VL
V3B
SUB
TEST2
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
VM
VM
VH
VH
VH
VH
VH
L
ACT
ACT
ACT
L
ACT
ACT
ACT
ACT
ACT
VM
VM
VH
VH
VH
VH
VH
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
VM
VM
VH
VH
VH
VH
VH
ACT
ACT
ACT
ACT
ACT
DIS
DIS
DIS
ACT
ACT
VM
VL
VM
VM
VL
VL
VL
Symbol CAM SLP STB
DSGAT
RST Pin
No. Symbol CAM SLP STB
DSGAT
RST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
– 14 –
CXD2470R
Serial Interface Control
The CXD2470R basically loads and reflects the serial interface data sent in the following format in the readout
portion at the falling edge of HDI. Here, readout portion specifies the horizontal period during which V1A/B and
V3A/B, etc. take the ternary value.
Note that some items reflect the serial interface data at the falling edge of VDI or the rising edge of SEN.
SSI
SCK
SEN
00 01 02 03 04 05 06 07 41 42 43 44 45 46 47
There are two categories of serial interface data: CXD2470R drive control data (hereafter "control data") and
electronic shutter data (hereafter "shutter data").
The details of each data are described below.
– 15 –
CXD2470R
Control Data
Data
D00
to
D07
D08
to
D09
D10
to
D11
D12
D13
to
D14
D15
to
D35
D36
to
D37
D38
to
D39
D40
to
D47
Symbol
CHIP
CTG
MODE
CCD
SMD
—
LDAD
STB
CKSM
Function
Chip enable
Category switching
Drive mode switching
CCD switching
Electronic shutter mode switching
—
ADCLK logic phase switching
Standby control
Check sum bit
Data = 0 Data = 1
10000001 →Enabled
Other values →Disabled
See D08 to D09 CTG.
See D10 to D11 MODE.
ICX224/ICX284 ICX202/ICX232
See D13 to D14 SMD.
——
See D36 to D37 LDAD.
See D38 to D39 STB.
See D40 to D47 CKSM.
RST
All
0
All
0
All
0
0
All
0
All
0
1
0
All
0
All
0
– 16 –
CXD2470R
Shutter Data
Data
D00
to
D07
D08
to
D09
D10
to
D17
D18
to
D27
D28
to
D35
D36
to
D39
D40
to
D47
Symbol
CHIP
CTG
SVD
SHD
SPL
—
CKSM
Function
Chip enable
Category switching
Electronic shutter vertical period
specification
Electronic shutter horizontal period
specification
High-speed shutter position
specification
—
Check sum bit
Data = 0 Data = 1
10000001 →Enabled
Other values →Disabled
See D08 to D09 CTG.
See D10 to D17 SVD.
See D18 to D27 SHD.
See D28 to D35 SPL.
——
See D40 to D47 CKSM.
RST
All
0
All
0
All
0
All
0
All
0
All
0
All
0
– 17 –
CXD2470R
Detailed Description of Each Data
Shared data: D08 to D09 CTG [Category]
Of the data provided to the CXD2470R by the serial interface, the CXD2470R loads D10 and subsequent data
to each data register as shown in the table below according to the combination of D08 and D09 .
D09
0
0
1
1
D08
0
1
0
1
Description of operation
Loading to control data register
Loading to shutter data register
Test mode
D11
0
0
1
1
D10
0
1
0
1
Description of operation
Quadruple-speed mode (default)
Frame mode (A field readout)
Frame mode (B field readout)
Frame mode
Note that the CXD2470R can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Shared data: D40 to D47 CKSM [Check sum]
These are the check sum bits. Apply the data shown below. This function is valid when EBCKSM (Pin 6) is low.
MSB LSB
D07 D06 D05 D04 D03 D02 D01 D00
D15 D14 D13 D12 D11 D10 D09 D08
D23 D22 D21 D20 D19 D18 D17 D16
D31 D30 D29 D28 D27 D26 D25 D24
D39 D38 D37 D36 D35 D34 D33 D32
+) D47 D46 D45 D44 D43 D42 D41 D40 →CKSM
00000000→Reflected when the total is "0".
Control data: D10 to D11 MODE [Drive mode]
The CXD2470R drive mode can be switched as follows. However, the drive mode bits are loaded to the
CXD2470R and reflected at the falling edge of VDI.
– 18 –
CXD2470R
Control data: D36 to D37 LDAD [ADCLK logic phase adjustment]
This indicates the ADCLK logic phase adjustment data. The default is 90°relative to MCKO.
Control data: D38 to D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD2470R and
control is applied immediately at the rising edge of SEN.
D37
0
0
1
1
D36
0
1
0
1
Degree of adjustment (°)
0
90
180
270
D39
X
0
1
D38
0
1
1
Symbol
CAM
SLP
STB
Operating mode
Normal operating mode
Sleep mode
Standby mode
See the Pin Status Table for the pin status in each mode.
Control data: D12 CCD [CCD switching]
Specifies CCD image sensor to be used. However, the CCD image sensor switching bit is loaded to the
CXD2470R and reflected at the falling edge of VDI. The default is "ICX224/ICX284".
D12
0
1
CCD
ICX224/ICX284
ICX202/ICX232
– 19 –
CXD2470R
Control data/shutter data: [Electronic shutter]
The CXD2470R realizes various electronic shutter functions by using control data D13 to D14 SMD and
shutter data D10 to D17 SVD, D18 to D27 SHD and D28 to D35 SPL.
These functions are described in detail below.
First, the various modes are shown below.
These modes are switched using control data D13 to D14 SMD.
D14
0
0
1
1
D13
0
1
0
1
Description of operation
Electronic shutter stopped mode
High-speed/low-speed shutter mode
HTSG control mode
The electronic shutter data is expressed as shown in the table below using D18 to D27 SHD as an example.
MSB LSB
D27 D26 D25 D24 D23 D22 D21 D20 D19 D18
01
↓
1
1100
↓
C
0011
↓
3→SHD is expressed as 1C3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[High-speed/low-speed shutter mode]
During this mode, the shutter data items have the following meanings.
The period during which SVD and SHD are specified together is the shutter speed. Concretely, when specifying
high-speed shutter, SVD is set to "00h". (See the figure.) During low-speed shutter, or in other words when
SVD is set to "01h" or higher, the serial interface data is not loaded until this period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHD can be considered as (number of SUB pulses – 1).
Note) The bit data definition area is assured in terms of the CXD2470R functions, and does not assure the
CCD characteristics.
Symbol
SVD
SHD
SPL
Data
D10 to D17
D18 to D27
D28 to D35
Description
Number of vertical periods specification (00h ≤SVD ≤FFh)
Number of horizontal periods specification (000h ≤SHD ≤3FFh)
Vertical period specification for high-speed shutter operation (00h ≤SPL ≤FFh)
– 20 –
CXD2470R
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
Incidentally, SPL is counted as "00h", "01h", "02h" and so on in conformance with SVD.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice-versa.
– 21 –
CXD2470R
VDI
V1A
SUB
WEN
01
11
Exposure time
01
SMD
Vck
[HTSG control mode]
During this mode, all shutter data items are invalid.
The V1A/B and V3A/B ternary level outputs are stopped, so the shutter speed is the value obtained by adding
the shutter speed specified in the preceding vertical period to the vertical period during which these readout
pulses are stopped as shown in the figure.
– 22 –
CXD2470R
Chart-1 Vertical Direction Timing Chart MODE
Frame mode
Applicable CCD image sensor
• ICX224/ICX284
A Field
VDI
HDI
SUB
V1A
V1B
V2
V3A
V3B
V4
CCD OUT
1225
1227
1228
1230
1232
1234
1236
1229
1231
1233
1235
3
157 246810 4
26 8 10 12 14 16 189
125
CC
31 1 24
B Field
31
13579111315171921
PBLK
ID
OBCLP
CLPDM
WEN
650
(1300) 650(651)
A B
∗The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period.
∗ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
– 23 –
CXD2470R
Chart-2 Vertical Direction Timing Chart MODE
Quadruple-speed mode
Applicable CCD image sensor
• ICX224/ICX284
VDI
HDI
SUB
V1A
V1B
V2
V3A
V3B
V4
CCD OUT
1210
1215
1215
1218
1223
1226
1231
1234
1218
1223
1226
1231
1234
94271015 2318 26 31 34 39 42 47 50 55
112
D D
16 11216
9
42 7 10 15 18 23 26 31 34 39 42 47 50 55 58
PBLK
ID
OBCLP
CLPDM
WEN
325 325
∗The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period.
∗ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
– 24 –
CXD2470R
Chart-3 Horizontal Direction Timing Chart MODE
Frame mode
Applicable CCD image sensor
• ICX224/ICX284
152
HDI
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
OBCLP
CLPDM
(1848)
050
56
100 150
120
72
104
56
51
13
104
190
88
56
152
88
200 250
ID
104
WEN
214
188
214
168
136
∗The HDI of this chart indicates the actual CXD2470R load timing.
∗The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗The HDI fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
∗SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ID and WEN are output at the timing shown above at the position shown in Chart-1.
– 25 –
CXD2470R
Chart-4 Horizontal Direction Timing Chart MODE
Quadruple-speed mode
Applicable CCD image sensor
• ICX224/ICX284
152
16813610472
16813610472
HDI
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
OBCLP
CLPDM
(1848)
050
56
100 150
120
120 152
8856
56
51
13
104
190
88
56
152
88
200 250
ID
104
WEN
214
188
214
∗The HDI of this chart indicates the actual CXD2470R load timing.
∗The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗The HDI fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
∗SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ID and WEN are output at the timing shown above at the position shown in Chart-2.
– 26 –
CXD2470R
Chart-5 Horizontal Direction Timing Chart
(High-speed sweep: C) MODE
Frame mode
Applicable CCD image sensor
• ICX224/ICX284
188
168 196 224 252 280
HDI
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
OBCLP
CLPDM
(1848)
050
56
100 150
112 1408456
182 210 238 266
1549870
51
13
56
15288
200 250
ID
WEN
126
168 196 224 252 2801408456
182 210 238 266
#1 #2 #3 #4
15470 126
112
98
∗The HDI of this chart indicates the actual CXD2470R load timing.
∗The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗The HDI fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
∗SUB is output at the timing shown above when output is controlled by the serial interface data.
∗High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 22H of 1848ck (#758).
– 27 –
CXD2470R
Chart-6 Horizontal Direction Timing Chart MODE
Frame mode
Applicable CCD image sensor
• ICX224/ICX284
HDI
[A Field]
[B Field]
[A]
[B]
V3B
V4
V3B
V4
Logic alignment portion
V1A
V1B
V2
V3A
V1A
V1B
V2
V3A
(1848)
056 72 12088 136104 152 184 200168 216 (1848)
056 72 12088 136104 152 168
1071
1091
1175
1029
1027
1133
1131
∗The HDI of this chart indicates the actual CXD2470R load timing.
∗The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗The HDI fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
– 28 –
CXD2470R
Chart-7 Horizontal Direction Timing Chart MODE
Quadruple-speed mode
Applicable CCD image sensor
• ICX224/ICX284
HDI
[D]
V3B
V4
V1A
V1B
V2
V3A
(1848)
056 72 12088 136104 152 168 (1848)
056 72 12088 136104 152 168
1071
1091
1111
1175
1029
1027
1133
1131
∗The HDI of this chart indicates the actual CXD2470R load timing.
∗The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗The HDI fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
– 29 –
CXD2470R
Chart-8 Vertical Direction Timing Chart MODE
Frame mode
Applicable CCD image sensor
• ICX/202/ICX232
A Field
VDI
HDI
SUB
V1A
V1B
V2
V3A
V3B
V4
CCD OUT
955
957
958
960
962
964
966
959
961
963
965
13 24246 10
812 14 16 18 20
1
137
EGFG
40 136
B Field
40
357911131517192123
PBLK
ID
OBCLP
CLPDM
WEN
525
(1050) 525(526)
∗The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
– 30 –
CXD2470R
Chart-9 Vertical Direction Timing Chart MODE
Quadruple-speed mode
Applicable CCD image sensor
• ICX202/ICX232
VDI
HDI
SUB
V1A
V1B
V2
V3A
V3B
V4
CCD OUT
944
949
949
952
957
960
965
952
957
960
965
41581316 2421 29 32 37 40
117
H H
20 11720
1 4 5 8 131621242932374045
PBLK
ID
OBCLP
CLPDM
WEN
262 262
∗The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
– 31 –
CXD2470R
Chart-10 Horizontal Direction Timing Chart MODE
Frame mode
Applicable CCD image sensor
• ICX202/ICX232
175
HDI
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
OBCLP
CLPDM
(1560)
050
55
100 150
135
75
115
55
50
10
115
244
95
55
155
95
200 250
ID 115
WEN
270
242
270
195
155
∗The HDI of this chart indicates the actual CXD2470R load timing.
∗The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗The HDI fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
∗SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ID and WEN are output at the timing shown above at the position shown in Chart-8.
– 32 –
CXD2470R
Chart-11 Horizontal Direction Timing Chart MODE
Quadruple-speed mode
Applicable CCD image sensor
• ICX202/ICX232
175
19515511575
19515511575
HDI
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
OBCLP
CLPDM
(1560)
050
55
100 150
135
135 175
9555
55
50
10
115
244
95
55
15595
200 250
ID 115
WEN
270
242
270
∗The HDI of this chart indicates the actual CXD2470R load timing.
∗The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗The HDI fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
∗SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ID and WEN are output at the timing shown above at the position shown in Chart-9.
– 33 –
CXD2470R
Chart-12 Horizontal Direction Timing Chart
(High-speed sweep: G) MODE
Frame mode
Applicable CCD image sensor
• ICX202/ICX232
242
175 215 255
HDI
MCKO
H1
H2
V1A/B
V2
V3A/B
V4
SUB
PBLK
OBCLP
CLPDM
(1560)
050
55
100 150
1359555
75 115 155 195 235 275
75 115 155 195 235 275
175 215 255
1359555
50
10
55
15595
200 250
ID
WEN
#1 #2 #3
∗The HDI of this chart indicates the actual CXD2470R load timing.
∗The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗The HDI fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
∗SUB is output at the timing shown above when output is controlled by the serial interface data.
∗High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 33H of 1295ck (#659).
– 34 –
CXD2470R
Chart-13 Horizontal Direction Timing Chart MODE
Frame mode
Applicable CCD image sensor
• ICX202/ICX232
HDI
[A Field]
[B Field]
[E]
[F]
V3B
V4
V3B
V4
V1A
V1B
V2
V3A
V1A
V1B
V2
V3A
(1560)
055 75 13595 155115 175 195 (1560)
055 75 13595 155115 175 195843 903 923 983
∗The HDI of this chart indicates the actual CXD2470R load timing.
∗The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗The HDI fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
– 35 –
CXD2470R
Chart-14 Horizontal Direction Timing Chart MODE
Quadruple-speed mode
Applicable CCD image sensor
• ICX202/ICX232
HDI
[H]
V3B
V4
V1A
V1B
V2
V3A
(1560)
055 75 13595 155115 175 195 (1560)
055 75 13595 155115 175 195
843 903 923 983
∗The HDI of this chart indicates the actual CXD2470R load timing.
∗The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗The HDI fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
– 36 –
CXD2470R
Chart-15 High-Speed Phase Timing Chart MODE Applicable CCD image sensor
• ICX224/ICX284/ICX202/ICX232
HDI
HDI'
CKI
CKO
ADCLK
MCKO
H1
H2
RG
XSHP
XSHD
XRS
55/56 188/242
1
∗HDI' indicates the HDI which is the actual CXD2470R load timing.
∗The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
∗The logical phase of ADCLK can be specified by the serial interface.
– 37 –
CXD2470R
Application Circuit Block Diagram
26 27 37 48 31 32
34
35
30
25
23
22
201918
17
16
MCKO
VDI
HDI
CKO
10
D0 to 9
ADCLK
OBCLP
CLPDM
PBLK
XRS
XSHD
XSHP
SCK
33
SEN
SSI
TEST2
TEST1
OSCO
CKI
28
OSCI
CCD OUT
V-Dr
VRT
DRVOUT
VRB
6
3
2
5
4
EBCKSM
DSGAT
RST
WEN
ID
12
13
9
RG
H2
H1
41
43
39
V2
V1B
V1A
44
46
40
V4
47
SUB
V3B
V3A
CCD
ICX224/ICX284
ICX202/ICX232
S/H
CXA2006Q
TG
CXD2470R
A/D
CXD2311AR
Controller
Signal Processor Block
Notes for Power-on
Of the three –7.5V, +15.0V and +3.3V power supplies, be sure to start up the –7.5V and +15.0V power supplies
in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential.
t1
t2
15.0V
0V
–7.5V
20%
20%
t2 ≥ t1
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 38 –
CXD2470R
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
42/COPPER ALLOY
PACKAGE STRUCTURE
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗ 7.0 ± 0.1
112
13
24
25
36
37
48 (0.22)
0.18 – 0.03
+ 0.08
0.2g
LQFP-48P-L01
P-LQFP48-7x7-0.5
(8.0)
0.5 ± 0.2
0.127 – 0.02
+ 0.05
A
1.5 – 0.1
+ 0.2
0.1
SOLDER PLATING
NOTE: Dimension “∗” does not include mold protrusion.
0.1 ± 0.1
0.5 ± 0.2
0˚ to 10˚
DETAIL A
0.13 M
0.5
S
S
B
DETAIL B: SOLDER
(0.18)
(0.127)
0.18 – 0.03
+ 0.08
0.127 – 0.02
+0.05
Package Outline Unit: mm
– 39 –
CXD2470R
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
COPPER ALLOY
PACKAGE STRUCTURE
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗ 7.0 ± 0.1
112
13
24
25
36
37
48 (0.22)
0.18 – 0.03
+ 0.08
0.2g
LQFP-48P-L01
P-LQFP48-7x7-0.5
(8.0)
0.5 ± 0.2
0.127 – 0.02
+ 0.05
A
1.5 – 0.1
+ 0.2
0.1
PALLADIUM PLATING
NOTE: Dimension “∗” does not include mold protrusion.
0.1 ± 0.1
0.5 ± 0.2
0˚ to 10˚
DETAIL A
0.13 M
0.5
S
S
B
DETAIL B: PALLADIUM
0.127 ± 0.04
0.18 ± 0.03
– 40 –
CXD2470R
48PIN LQFP (PLASTIC)
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
LQFP-48P-L282
b
1.7MAX
B
S
S
0.08
( 8.0 )
1.4 ± 0.05
A
MS
0.07
0.5
9.0 ± 0.2
7.0 ± 0.1
112
36 25
37
48
24
13
0.2g
b=0.21 ± 0.05
DETAIL B
(0.2)
(0.125)
0.127
+ 0.05
0.1 ± 0.05
0˚ to 7˚
DETAIL A
0.25
0.6 ± 0.15
P-LQFP48-7X7-0.5
– 0.02
( Amkor )
LEAD SPECIFICATIONS
ITEM
LEAD MATERIAL COPPER ALLOY
LEAD TREATMENT Sn-Bi 2.5%
LEAD TREATMENT THICKNESS 5-18µm
SPEC.
Sony Corporation