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Document No. 70-0157-01 │www.psemi.com ©2005 Peregrine Semic onduct or Corp. All ri ghts res erved.
The PE926C31 is a high performance monolithic CMOS
RS-422 line driver. Its operating supply range is 3.0 to 3.6
V, with an output signal overvoltage range of 0 – 6 V. The
PE26C31 offers higher speed and lower power than other
RS-422 driver types. It is packaged in a flat pack and is
ideal for space applications.
The PE926C31 is manufactured in Peregrine’s patented
Ultra Thin Silicon (UTSi®) CMOS process, offering the
performance of GaAs with the economy and integration of
conventional CMOS.
Product Specification
Product Description
Figure 1. Package Drawing
PE926C31
Features
• High-speed operation: < 10 nS typical
• Low power: < 150 uA typical
(unloaded)
• 3.3 V operation
• Standard packaging: 16-lead flat pack
• SEL Immune UTSi CMOS-on-sapphire
• SEU <10-10 errors / bit-day
• 300 Krad Total Dose
Quad RS-422 Differential Line
Driver Radiation Hardened
Product Specific ation
PE926C31
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©2005 Peregrine Semic onduct or Corp. All ri ghts res erved. Document No. 70-0157-01 │ UltraCM O S™ RFIC Solutions
Table 1. Pin Descriptions
Table 2. Recommended Operating Conditions
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 2.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 3. Truth Table
Device Functional Considerations
The PE926C31 operates at high switching
speeds. In order to obtain maximum
performance, it is crucial that pin 16 be supplied
with a bypass capacitor to ground (pin 8).
Figure 2. Pin Configuration (Top View)
1 A
PE926C31
2 AQ+
3 AQ-
4 E+
5 BQ-
6 BQ+
7 B
8 V-
16
15
14
13
12
11
10
9
V+
D
DQ+
DQ-
E-
CQ-
C
CQ+
Pin
No. Pin
Name Description
1 A Channel A Input
2 AQ+ Channel A Noninverting Ouput
3 AQ- Channel A Inverting Out put
4 E+ Enable, activ e high
5 BQ- Channel B Inverting Out put
6 BQ+ Channel B Noninverting Output
7 B Channel B Input
8 V- Ground Pin
9 C Channel C Input
10 CQ+ Channel C Noninvert i ng Output
11 CQ- Channel C Inverting Ouput
12 E- Enable, activ e low
13 DQ- Channel D Inverting Output
14 DQ+ Channel D Noninvert i ng Output
15 D Channel D Input
16 V+ Supply Pin
Symbol Parameter/Conditions Min Max Units
V+ Supply voltage 3.0 3.6 V
TOP Operating temperature
range -55 125 °C
VIN Maximum input voltage 0 Vdd V
VOUT M aximum output voltage 0 Vdd V
IOUT Maximum output current -50 50 mA
E+ E- Data Q+ Q-
L H X Z Z
H X L L H
X L
H X H H L
X L
Product Specific ation
PE926C31
Page 3 of 7
Document No. 70-0157-01 │www.psemi.com ©2005 Peregrine Semic onduct or Corp. All ri ghts res erved.
Table 4. Electrical Specifications
Notes: 1. “Line” pins refer to AQ-, AQ+, BQ-, BQ+, CQ-, CQ+, DQ-, DQ+, differential outputs
2. “Digit al Input” or “E nabl e” pins refer to E+, E-
3. “Digital Input” pins refer to A, B, C, D
Param Description Conditions Pin(s) Min Typ Max Units
VD1 Output Differential Voltage No load AQ+, AQ-, BQ+, BQ-,
CQ+, CQ-, DQ+, DQ- (V+) -0.3 (V+) (V+)
+0.6 V
VD2 Output Differential Voltage RL=100 Ω, Fig DC1 1.9 2.3 V
DVD2 Output Differential Voltage Change IOUT 0 – 20mA, Fig DC1 -0.4 0 0.4 V
VCM Common Mode Voltage RL=100 Ω, Fig DC1 1.5 2.0 V
DVCM Common Mode Voltage Change RL=100 Ω, Fig DC1 -0.4 0 0.4 V
IOZH Tristate Output Leakage (H) VOUT = V+, disabled -5 -0.1 uA
IOZL Tristate Output Leakage (L) VOUT = 0.0 V, disabled 0.1 5 uA
IOSC Output Short Circuit Current VOUT = 0.0 V, Enabled Q=H -30 -70 -100 mA
IOFFH Output Leakage Current (H) VOUT=6.0V,V+ and all inputs
= 0.0V 1 100 uA
IOFFL Output Leakage Current (L) VOUT=-0.25V,V+ and all
inputs = 0.0V -100 -1 uA
VOH Output High Voltage Iout=-20mA 2.0 2.4 V
VOL Output Low Voltage Iout=20mA 0.1 0.5 V
VIH Input threshold H Vdd=3.6V (VIHMIN=0.7*VDD) A, B, C, D, E+, E- 2.5 V
VIL Input Threshold L Vdd=3.0V
(VILMAX=0.3*VDD) A, B, C, D, E+, E- 0.9 V
IIH Input Lkg Current A, B, C, D, E+, E- -1 1 uA
IIL Input Lkg Current A, B, C, D, E+, E- -1 1 uA
VIKL Input Clamp Diode Voltage IIN=-20 mA A, B, C, D, E+, E- -1.5
VIKH Input Clamp Diode Voltage IIN=20 mA A, B, C, D, E+, E- (V+) +
1.5 V µ
ICC Supply Current No load, Inputs = 0 V or V+ V+ 120
uA 150 uA
-55° C < Tcase < 125° C, 3.0 V < V+ < 3.6 V, PreRad, unless otherwise specified
Product Specific ation
PE926C31
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©2005 Peregrine Semic onduct or Corp. All ri ghts res erved. Document No. 70-0157-01 │ UltraCM O S™ RFIC Solutions
Table 5. Post-Irradiation DC Electrical Specifications
Notes: 1. “Line” pins refer to AQ-, AQ+, BQ-, BQ+, CQ-, CQ+, DQ-, DQ+, differential outputs
2. “Digit al Input” or “E nabl e” pins refer to E+, E-
3. “Digital Input” pins refer to A, B, C, D
4. Output Short Circuit not intended to imply conti nuous operat i on
Tcase = 25° C, 3.0 V < V+ < 3.6 V, 300 KRad, unless otherwise specified
Param Description Conditions Pin(s) Min Typ Max Units
VD1 Output Differential Voltage No load AQ+, AQ-, BQ+, BQ-,
CQ+, CQ-, DQ+, DQ- (V+) -0.3 (V+) (V+) +0.6 V
VD2 Output Differential Voltage RL=100 Ω, Fig DC1 1.9 2.3 V
DVD2 Output Differential Voltage
Change IOUT 0 – 20mA, Fig DC1 -0.4 0 0.4 V
VCM Common Mode Voltage RL=100 Ω, Fig DC1 1.5 2.0 V
DVCM Common Mode Voltage Change RL=100 Ω, Fig DC1 -0.4 0 0.4 V
IOZH Tristate Output Leakage (H) VOUT = V+, disabled -5 -0.1 uA
IOZL Tristate Output Leakage (L) VOUT = 0.0 V, disabled 0.1 5 uA
IOSC Output Short Circuit Current VOUT = 0.0 V, Enabled Q=H -30 -70 -100 mA
IOFFH Output Leakage Current (H) VOUT=6.0V,V+ and all inputs
= 0.0V 1 100 uA
IOFFL Output Leakage Current (L) VOUT=-0.25V,V+ and all
inputs = 0.0V -100 -1 uA
VOH Output High Voltage Iout=-20mA 2.0 2.4 V
VOL Output Low Voltage Iout=20mA 0.1 0.5 V
VIH Input threshold H Vdd=3.6V
(VIHMIN=0.7*VDD) A, B, C, D, E+, E- 2.5 V
VIL Input Threshold L Vdd=3.0V
(VILMAX=0.3*VDD) A, B, C, D, E+, E- 0.9 V
IIH Input Lkg Current A, B, C, D, E+, E- -1 1 uA
IIL Input Lkg Current A, B, C, D, E+, E- -1 1 uA
VIKL Input Clamp Diode Voltage IIN=-20 mA A, B, C, D, E+, E- -1.5
VIKH Input Clamp Diode Voltage IIN=20 mA A, B, C, D, E+, E- (V+) +
1.5 V
ICC Supply Current No load, Inputs = 0 V or V+ V+ 120
uA 150 uA
Product Specific ation
PE926C31
Page 5 of 7
Document No. 70-0157-01 │www.psemi.com ©2005 Peregrine Semic onduct or Corp. All ri ghts res erved.
Table 6. Pre-irradiation Electrical Specifications
Param Description Conditions Pin(s) Min Typ Max Units
TPHL Prop Delay H-L RL=100 CL=50 pF AQ+,
AQ-,
BQ+,
BQ-,
CQ+,
CQ-,
DQ+,
DQ-
3 9 15 nS
TPLH Prop Delay H-L 3 9 15 nS
TSK1 Prop Delay Q+/Q- -3 0 3 nS
TSK2* Prop Delay Skew Ch/Ch -3 0 3 nS
TRISE* Rise Time 20%/80% 3 10 nS
TFALL* Fall Time 20%/80% 3 10 nS
TPHZ Prop Delay H-Z 12 20 nS
TPZH Prop Delay Z-H 12 20 nS
TPLZ Prop Delay L-Z 10 20 nS
TPZL Prop Delay Z-L 10 20 nS
-55° C < Tcase < 125° C, 3.0 V < V+ < 3.6 V, PreRad, unless otherwise specified
Table 7. Post-irradiation Electrical Specifications
25° C, 3.0 V < V+ < 3.6 V, 300 KRad, unless otherwise specified
Param Description Conditions Pin(s) Min Typ Max Units
TPHL Prop Delay H-L RL=100 CL=50 pF AQ+,
AQ-,
BQ+,
BQ-,
CQ+,
CQ-,
DQ+,
DQ-
3 9 15 nS
TPLH Prop Delay H-L 3 9 15 nS
TSK1 Prop Delay Q+/Q- -3 0 3 nS
TSK2* Prop Delay Skew Ch/Ch -3 0 3 nS
TRISE* Rise Time 20%/80% 3 10 nS
TFALL* Fall Time 20%/80% 3 10 nS
TPHZ Prop Delay H-Z 20 20 nS
TPZH Prop Delay Z-H 20 20 nS
TPLZ Prop Delay L-Z 10 20 nS
TPZL Prop Delay Z-L 10 20 nS
*Note: Guaranteed by design, not tested
Product Specific ation
PE926C31
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©2005 Peregrine Semic onduct or Corp. All ri ghts res erved. Document No. 70-0157-01 │ UltraCM O S™ RFIC Solutions
Figure 3. TPLH, TPHL Test Circuit Block Diagram
Figure 4. TPLZ, TPZL, TPHZ, TPZH Test Circuit Block Diagram
VI
0.0 – (V+)
+
-
DC 2,6,10,14
1,7,9,15
3,5,11,13
4,16
8,12
Figure 2 : TPLH, TPHL
TPLH, TPHL measured from input 50% to output
50% thresholds. TRISE, TFALL measured from
output 20% to output 80% thresholds.
I+
Q+
TPLH TPLH
Q-,
Q+
TRISE TFALL
Q-
VI
L: 0.0
H: (V+)
+
- CL
50pF
DC
2,6,10,14
1,7,9,15
3,5,11,13
16
Figure 3: TPHZ, TPZH, TPLZ, TPZL
R
L
110Ω
DC V+
3.3V
E+
0 - (V+)
4
E-
(V+) - 0
13
TPZH, TPZL measured from input 50% to output
50% thresholds. TPHZ, TPLZ measured from
input 50% to output 10% thresholds.
E-
E+
Q+,
Q-
TPZH TPHZ
Q+,
Q-
TPLZ
TPZL
Order Code Part Marking Description Package Shipping
Method
926C31-01 PE926C31-01 Engineering Sample 16-lead FLAT PACK 1/Box
926C31-21 PE926C31-21 Flight Product, FP 16-lead FLAT PACK 25/Tray
926C31-00 PE926C31-EK Evaluation Kit Evaluation Board 1/Box
Table 8. Ordering Information
Product Specific ation
PE926C31
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Document No. 70-0157-01 │www.psemi.com ©2005 Peregrine Semic onduct or Corp. All ri ghts res erved.
Sales Offices
United States
Peregrine Semiconductor Corp.
9450 Carroll Park Drive
San Diego, CA 92121
Tel 1-858-731-9400
Fax 1-858-731-9499
Japan
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: 011-81-3-3502-5211
Fax: 011-81-3-3502-5213
Europe
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: 011- 33-1-47-41-91-73
Fax : 011-33-1-47-41-91-73
China
Peregrine Semiconductor
28G, Times Square,
No. 500 Zhangyang Road,
Shanghai, 200122, P.R. China
Tel: 011-86-21-5836-8276
Fax: 011-86-21-5836-7652
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS is a trademark of Peregrine Semiconductor
Corp.
