 
  
FEATURES DESCRIPTION
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
_
+
Interface
Logic Shift
Register DAC
Register String
DAC
Power-Down
Logic
Power-On
Reset
VDD IOVDD VREFH
VFB
VOUT
VREFLGNDCLR
SDO
SDIN
SYNC
SCLK
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
12-Bit, Ultra-Low Glitch, Voltage OutputDIGITAL-TO-ANALOG CONVERTER
•Relative Accuracy (INL): ±0.35LSB
The DAC7551 is a single-channel, voltage-outputdigital-to-analog converter (DAC) with exceptional•Ultra-Low Glitch Energy: 0.1nV-s
linearity and monotonicity, and a proprietary•Low Power Operation: 100 µA at 2.7V
architecture that minimizes glitch energy. The•Power-On Reset to Zero Scale
low-power DAC7551 operates from a single 2.7V to•Power Supply: 2.7V to 5.5V Single Supply 5.5V supply. The DAC7551 output amplifiers candrive a 2k Ω, 200pF load rail-to-rail with 5 µs settling•Power-Down: 0.05 µA at 2.7V
time; the output range is set using an external•12-Bit Linearity and Monotonicity
voltage reference.•Rail-to-Rail Voltage Output
The 3-wire serial interface operates at clock rates up•Settling Time: 5 µs (Max)
to 50MHz and is compatible with SPI™, QSPI™,•SPI-Compatible Serial Interface with Microwire™, and DSP interface standards. The partsincorporate a power-on-reset circuit to ensure thatSchmitt-Trigger Input: Up to 50MHz
the DAC output powers up to 0V and remains there•Daisy-Chain Capability
until a valid write cycle to the device takes place. The•Asynchronous Hardware Clear to Zero Scale
part contains a power-down feature that reduces thecurrent consumption of the device to under 2 µA.•Specified Temperature Range:– 40 °C to +105 °C
Small size and low-power operation make the•Small, 2 x 3 mm, 12-Lead SON Package
DAC7551 ideally suited for battery-operated, portableapplications. The power consumption is typically0.5mW at 5V, 0.23mW at 3V, and reduces to 1 µW inpower-down mode.•Portable, Battery-Powered Instruments•Digital Gain and Offset Adjustment
The DAC7551 is available in a 12-lead SONpackage and is specified over –40 °C to +105 °C.•Programmable Voltage and Current Sources•Programmable Attenuators•Industrial Process Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SPI, QSPI are trademarks of Motorola, Inc.Microwire is a trademark of National Semiconductor Corp..All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
ORDERING INFORMATION
(1)
SPECIFIEDPACKAGE TEMPERATURE PACKAGEPRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING
DAC7551 SON-12 DRN –40 °C to +105 °C D51
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
Over operating free-air temperature range (unless otherwise noted).
UNIT
V
DD
, IOV
DD
to GND –0.3V to 6VDigital input voltage to GND –0.3V to V
DD
+ 0.3VV
OUT
to GND –0.3V to V
DD
+ 0.3VOperating temperature range –40 °C to +105 °CStorage temperature range –65 °C to +150 °CJunction temperature (T
J
Max) +150 °CPower dissipation (DRN) (T
J
max – T
A
)/ θ
JA
Thermal impedance, θ
JA
79 °C/WThermal impedance, θ
JC
48.57 °C/WHuman body model (HBM) 4000VESD rating
Charged device model (CDM) 1500V
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may affect device reliability.
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ELECTRICAL CHARACTERISTICS
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
all specifications at –40 °C to +105 °C, V
DD
= 2.7V to 5.5V, V
REF
H = V
DD
, V
REF
L = GND, R
L
= 2k Ωto GND, and C
L
= 200pF toGND (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
(1)
Resolution 12 BitsRelative accuracy ±0.35 ±1 LSBDifferential nonlinearity Specified monotonic by design ±0.08 ±0.5 LSBOffset error ±12 mVZero-scale error All zeroes loaded to DAC register ±12 mVGain error ±0.15 %FSRFull-scale error ±0.5 %FSRZero-scale error drift 7 µV/ °Cppm ofGain temperature coefficient 3
FSR/ °CPSRR V
DD
= 5V 0.75 mV/V
OUTPUT CHARACTERISTICS
(2)
Output voltage range 2 x V
REF
L V
REF
H VOutput voltage settling time R
L
= 2k Ω, 0pF < C
L
< 200pF 5 µsSlew rate 1.8 V/ µsR
L
=∞470Capacitive load stability pFR
L
= 2k Ω1000Digital-to-analog glitch impulse 1 LSB change around major carry 0.1 nV-sDigital feedthrough 0.1 nV-sOutput noise density 10kHz offset frequency 120 nV/ √HzTotal harmonic distortion f
OUT
= 1kHz, f
S
= 1MSPS, BW = 20kHz –85 dBDC output impedance 1 ΩV
DD
= 5V 50Short-circuit current mAV
DD
= 3V 20Coming out of power-down mode, V
DD
= 5V 15Power-up time µsComing out of power-down mode, V
DD
= 3V 15
REFERENCE INPUT
V
REF
H Input range 0 V
DD
VV
REF
L Input range V
REF
L < V
REF
H 0 GND V
DD
VReference input impedance 100 k ΩV
REF
= V
DD
= 5V 50 100Reference current µAV
REF
= V
DD
= 3V 30 60
LOGIC INPUTS
(2)
Input current ±1µAV
IN_L
, Input low voltage IOV
DD
≥2.7V 0.3 IOV
DD
VV
IN_H
, Input high voltage IOV
DD
≥2.7V 0.7 IOV
DD
VPin capacitance 3 pF
(1) Linearity tested using a reduced code range of 30 to 4065; output unloaded.(2) Specified by design and characterization; not production tested. For 1.8V < IOV
DD
< 2.7V, it is recommended that V
IH
≥0.8 IOV
DD
, andV
IL
≤0.2 IOV
DD
.
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DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
ELECTRICAL CHARACTERISTICS (continued)all specifications at –40 °C to +105 °C, V
DD
= 2.7V to 5.5V, V
REF
H = V
DD
, V
REF
L = GND, R
L
= 2k Ωto GND, and C
L
= 200pF toGND (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS
V
DD
2.7 5.5 VIOV
DD
(3)
1.8 V
DD
VNormal operation (DAC V
DD
= 3.6V to 5.5V, V
IH
= IOV
DD
, V
IL
= GND 150 200active and excluding load µAV
DD
= 2.7V to 3.6V, V
IH
= IOV
DD
, V
IL
= GND 100 150current)I
DD
(4)
V
DD
= 3.6V to 5.5V, V
IH
= IOV
DD
, V
IL
= GND 0.2 2All power-down modes µAV
DD
= 2.7V to 3.6V, V
IH
= IOV
DD
, V
IL
= GND 0.05 2
POWER EFFICIENCY
I
OUT
/I
DD
I
LOAD
= 2mA, V
DD
= 5V 93 %
TEMPERATURE RANGE
Specified performance –40 +105 °C
(3) IOV
DD
operates down to 1.8V with slightly degraded timing, as long as V
IH
≥0.8 IOV
DD
and V
IL
≤0.2 IOV
DD
.(4) I
DD
tested with digital input code = 0032.
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PIN CONFIGURATION
VDD
V H
REF
V L
REF
VFB
VOUT
GND
IOVDD
SDO
SDIN
SCLK
SYNC
CLR
1
2
3
4
5
6
12
11
10
9
8
7
DAC7751
Thermal
Pad(1)
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
Pin Descriptions
PIN
NO. NAME DESCRIPTION
1 V
DD
Analog voltage supply input2 V
REF
H Positive reference voltage input3 V
REF
L Negative reference voltage input4 V
FB
DAC amplifier sense input.5 V
OUT
Analog output voltage from DAC6 GND
(1)
Ground.
Asynchronous input to clear the DAC registers. When CLR is low, the DAC register is set to 000h and the output7 CLR
voltage to 0V.Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out8 SYNC
to the DAC7551.9 SCLK Serial clock input10 SDIN Serial data input11 SDO Serial data output12 IOV
DD
I/O voltage supply input
(1) Thermal pad should be connected to GND.
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SERIAL WRITE OPERATION
SCLK
SYNC
SDIN D15 D14 D13 D12 D11 D1 D0 D15
t8t4t3t2
t1
t7
t6
t5
D0
t9
Input Word n Input Word n+1
Undefined
D15 D14 D0
Input Word n
t10
SDO
CLR
TIMING CHARACTERISTICS
(1) (2)
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
Figure 1. Serial Write Operation Timing Diagram
All specifications at –40 °C to +105 °C, V
DD
= 2.7V to 5.5V, and R
L
= 2k Ωto GND (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
V
DD
= 2.7V to 3.6V 20t
1
(3)
SCLK cycle time nsV
DD
= 3.6V to 5.5V 20V
DD
= 2.7V to 3.6V 6.5t
2
SCLK HIGH time nsV
DD
= 3.6V to 5.5V 6.5V
DD
= 2.7V to 3.6V 6.5t
3
SCLK LOW time nsV
DD
= 3.6V to 5.5V 6.5V
DD
= 2.7V to 3.6V 4t
4
SYNC falling edge to SCLK falling edge setup time nsV
DD
= 3.6V to 5.5V 4V
DD
= 2.7V to 3.6V 3t
5
Data setup time nsV
DD
= 3.6V to 5.5V 3V
DD
= 2.7V to 3.6V 3t
6
Data hold time nsV
DD
= 3.6V to 5.5V 3V
DD
= 2.7V to 3.6V 0 t
1
– 10ns
(4)t
7
SCLK falling edge to SYNC rising edge nsV
DD
= 3.6V to 5.5V 0 t
1
– 10ns
(4)
V
DD
= 2.7V to 3.6V 20t
8
Minimum SYNC HIGH time nsV
DD
= 3.6V to 5.5V 20V
DD
= 2.7V to 3.6V 10t
9
SCLK falling edge to SDO valid nsV
DD
= 3.6V to 5.5V 10V
DD
= 2.7V to 3.6V 10t
10
CLR pulse width low nsV
DD
= 3.6V to 5.5V 10
(1) All input signals are specified with t
R
= t
F
= 1ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.(2) See Figure 1 , Serial Write Operation timing diagram.(3) Maximum SCLK frequency is 50MHz at V
DD
= 2.7V to 5.5V.(4) SCLK falling edge to SYNC rising edge time shold not exceed (t
1
– 10ns) in order to latch the correct data.
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TYPICAL CHARACTERISTICS
1.0
0.5
0
-0.5
-1.0
LE(LSB)
0 512 1024 1536 2048
DigitalInputCode
2560 3072 3584 4096
0.50
0.25
0
-0.25
-0.50
DLE(LSB)
V =5V,
DD V H=4.096V,V L=GND
REF REF
1.0
0.5
0
-0.5
-1.0
LE(LSB)
0 512 1024 1536 2048
DigitalInputCode
2560 3072 3584 4096
0.50
0.25
0
-0.25
-0.50
DLE(LSB)
V =2.7V,
DD V H=2.5V,V L=GND
REF REF
1.00
0.75
0.50
0.25
0
Zero-ScaleError(mV)
Free-AirTemperature( C)°
-40 -10 20 50 80 105
V =5V
DD
V H=4.096V
REF
V L=GND
REF
1.00
0.75
0.50
0.25
0
Zero-ScaleError(mV)
Free-AirTemperature( C)°
-40 -10 20 50 80 105
V =2.7V
DD
V H=2.5V
REF
V L=GND
REF
0
-0.25
-0.50
-0.75
-1.00
Full-ScaleError(mV)
Free-AirTemperature( C)°
-40 -10 20 50 80 105
V =5V
DD
V H=4.096V
REF
V L=GND
REF
0
-0.25
-0.50
-0.75
-1.00
Full-ScaleError(mV)
Free-AirTemperature( C)°
-40 -10 20 50 80 105
V =2.7V
DD
V H=2.5V
REF
V L=GND
REF
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
At T
A
= +25 °C, unless otherwise noted.
LINEARITY ERROR AND LINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 2. Figure 3.
ZERO-SCALE ERROR ZERO-SCALE ERRORvs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE
Figure 4. Figure 5.
FULL-SCALE ERROR FULL-SCALE ERRORvs FREE-AIR TEMPERATURE vs FREE-AIR TEMPERATURE
Figure 6. Figure 7.
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V =5.5V
DD
V H=4.096V
REF
V L=GND
REF
V =2.7V
DD
V H=2.5V
REF
V L=GND
REF
DACLoadedwith0000h
Typical
0.20
0.15
0.10
0.05
0
OutputVoltage,V (V)
O
0 5 10 15
I (mA)
SINK
VDD =VREFH=5.5V
V L=GND
REF
DACLoadedwithFFFFh
5.5
5.4
5.3
5.2
OutputVoltage,V (V)
O
0 5 10 15
I (mA)
SOURCE
VDD =VREFH=2.7V
VREFL=GND
DACLoadedwithFFFFh
2.7
2.6
2.5
2.4
OutputVoltage,V (V)
O
0 5 10 15
I (mA)
SOURCE
V =5.5V
DD
V H=4.096V
REF
V L=GND
REF
V =2.7V
DD
V H=2.5V
REF
V L=GND
REF
Powered,NoLoad
200
150
100
I( A)m
DD
-40 -10 20 50 80 110
Free-AirTemperature( C)°
175
125
DACPowered,NoLoad
V H=2.5V
REF
V L=GND
REF
V (V)
DD
2.7
110
105
100
95
90
IDD (mA)
3.53.1 3.9 4.3 4.7 5.1 5.5
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, unless otherwise noted.
SINK CURRENT SOURCE CURRENTAT NEGATIVE RAIL AT POSITIVE RAIL
Figure 8. Figure 9.
SOURCE CURRENT SUPPLY CURRENTAT POSITIVE RAIL vs DIGITAL INPUT CODE
Figure 10. Figure 11.
SUPPLY CURRENT SUPPLY CURRENTvs FREE-AIR TEMPERATURE vs SUPPLY VOLTAGE
Figure 12. Figure 13.
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DigitalInputCode=2048
V =5.5V
DD
V H=4.096V
REF
V L=GND
REF
CurrentConsumption( A)m
128 136 144 152 160 168 176 184 192
2000
1500
1000
500
0
Frequency(Hz)
V =5.5V
DD
V H=4.096V
REF
V L=GND
REF
V =2.7V
DD
V H=2.5V
REF
V L=GND
REF
T =+25 C°
A
SCLKInput
AllOtherInput=GND
1600
1200
800
400
0
I( A)m
DD
0 1 2 3 4 5
V (V)
LOGIC
DigitalInputCode=2048
V =2.7V
DD
V H=2.5V
REF
V L=GND
REF
CurrentConsumption( A)m
117 124 131 138 145 152 159 166 173
2000
1500
1000
500
0
Frequency(Hz)
V =5V
DD
V H=4.096V
REF
V L=GND
REF
T =+25 C°
A
DigitalInputCode
0
4
2
0
-2
-4
TotalError(mV)
512 1024 1536 2048 2560 3072 3584 4096
V =5V
DD
V H=4.096V
REF
V L=GND
REF
Power-UpCode=4000
5
4
3
2
1
0
OutputVoltage(V)
Time(4 s/div)m
V =2.7V
DD
V H=2.5V
REF
V L=GND
REF
T =+25 C°
A
DigitalInputCode
0
4
2
0
-2
-4
TotalError(mV)
512 1024 1536 2048 2560 3072 3584 4096
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, unless otherwise noted.
SUPPLY CURRENTvs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION - 5.5V
Figure 14. Figure 15.
HISTOGRAM OF CURRENT CONSUMPTION - 2.7V TOTAL ERROR - 5V
Figure 16. Figure 17.
TOTAL ERROR - 2.7V EXITING POWER-DOWN MODE
Figure 18. Figure 19.
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V =5V
DD
V H=4.096V
REF
V L=GND
REF
5
4
3
2
1
0
OutputVoltage,V (V)
O
Time(5 s/div)m
OutputLoadedwith200pFtoGND
Code0041to4055
V =2.7V
DD
V H=2.5V
REF
V L=GND
REF
3
2
1
0
OutputVoltage,V (V)
O
Time(5 s/div)m
OutputLoadedwith200pFtoGND
Code0041to4055
Time(400ns/div)
V (5mV/div)
O
TriggerPulse
Time(400ns/div)
V (5mV/div)
O
TriggerPulse
Time(400ns/div)
V (5mV/div)
O
TriggerPulse
V =5.5V
DD
V H=4.096V
REF
V L=GND
REF
f =1MSPS
S
-1dBFSRDigitalInput
MeasurementBandwidth=20kHz
2ndHarmonic
THD
3rdHarmonic
OutputFrequency,Tone(kHz)
0
-40
-50
-60
-70
-80
-90
-100
THD(dB)
1 2 3 4 5 6 7 8 9 10
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, unless otherwise noted.
LARGE-SIGNAL SETTLING TIME - 5V LARGE-SIGNAL SETTLING TIME - 2.7V
Figure 20. Figure 21.
MIDSCALE GLITCH WORST-CASE GLITCH
Figure 22. Figure 23.
TOTAL HARMONIC DISTORTIONDIGITAL FEEDTHROUGH ERROR vs OUTPUT FREQUENCY
Figure 24. Figure 25.
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THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
DAC
Register
REF(+)
ResistorString
REF( )-
V H
REF
VOUT
50kW
100kW100kW
VFB
V L
REF
RESISTOR STRING
VREFH
VREFL
R
R
R
R
VREFH V L-REF
2
RDIVIDER
ToOutputAmplifier
(2xGain)
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
The architecture of the DAC7551 consists of a stringDAC followed by an output buffer amplifier. Figure 26shows a generalized block diagram of the DACarchitecture.
Figure 26. Typical DAC Architecture
The input coding to the DAC7551 is unsigned binary,which gives the ideal output voltage as:V
OUT
= 2 x V
REF
L + (V
REF
H – V
REF
L) x D/4096
Where D = decimal equivalent of the binary code thatis loaded to the DAC register, which ranges from 0 to4095.
The resistor string section is shown in Figure 27 . It issimply a string of resistors, each of value R. Thedigital code loaded to the DAC register determines atwhich node on the string the voltage is tapped off to
Figure 27. Typical Resistor Stringbe fed into the output amplifier. The voltage istapped off by closing one of the switches connectingthe string to the amplifier. It is specified monotonicbecause it is a string of resistors.
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OUTPUT BUFFER AMPLIFIERS
Power Down
DAC External Reference Input
Asynchronous Clear
Amplifier Sense Input
IOVDD and Level Shifters
Power-On Reset
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
order to not turn on ESD protection devices, V
DD
andIOV
DD
should be applied before any other pin (suchThe output buffer amplifier is capable of generating
as V
REF
H) is brought high. The power-up sequencerail-to-rail voltages on its output, giving an output
of V
DD
and IOV
DD
is irrelevant. Therefore, IOV
DD
canrange of 0V to V
DD
. It is capable of driving a load of
be brought up before V
DD
, or vice-versa.2k Ωin parallel with up to 1000pF to GND. Thesource and sink capabilities of the output amplifiercan be seen in the typical curves. The slew rate is1.8V/ µs with a half-scale settling time of 3 µs with the The DAC7551 has a flexible power-down capability.output unloaded. During a power-down condition, the user hasflexibility to select the output impedance of the DAC.During power-down operation, the DAC can haveeither 1k Ω, 100k Ω, or Hi-Z output impedance toThe DAC7551 contains V
REF
H and V
REF
L reference
ground.inputs, which are unbuffered. The V
REF
H referencevoltage can be as low as 0.25V, and as high as V
DDbecause there is no restriction of headroom andfootroom from any reference amplifier. The DAC7551 output is asynchronously set tozero-scale voltage immediately after the CLR pin isIt is recommended to use a buffered reference in the
brought low. The CLR signal resets all internalexternal circuit (for example, the REF3140 ). The
registers and therefore behaves like the Power-Oninput impedance is typically 100k Ω.
Reset. The DAC7551 updates at the first rising edgeof the SYNC signal that occurs after the CLR pin isbrought back to high.The DAC7551 contains an amplifier feedback inputpin, V
FB
. For voltage output operation, V
FB
must beexternally connected to V
OUT
. For better DC
The DAC7551 can be used with different logicaccuracy, this connection should be made at load
families that require a wide range of supply voltages.points. The V
FB
pin is also useful for a variety of
To enable this useful feature, the IOV
DD
pin must beapplications, including digitally-controlled current
connected to the logic supply voltage of the system.sources. The feedback input pin is internally
All DAC7551 digital input and output pins areconnected to the DAC amplifier negative input
equipped with level-shifter circuits. Level shifters atterminal through a 100k Ωresistor. The amplifier
the input pins ensure that external logic-highnegative input terminal internally connects to ground
voltages are translated to the internal logic-highthrough another 100k Ωresistor (Figure 26 ). These
voltage, with no additional power dissipation.connections form a gain-of-two, noninverting,
Similarly, the level shifter for the SDO pin translatesamplifier configuration. Overall gain remains one
the internal logic-high voltage (V
DD
) to the externalbecause the resistor string has a divide-by-two
logic-high level (IOV
DD
). For single-supply operation,configuration. The resistance seen at the V
FB
pin is
the IOV
DD
pin can be tied to the V
DD
pin.approximately 200k Ωto ground.
On power up, all registers are cleared and the DACchannel is updated with zero-scale voltage. The DACoutput remains in this state until valid data arewritten. This setup is particularly useful inapplications where it is important to know the state ofthe DAC output while the device is powering up. In
12
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SERIAL INTERFACE
16-Bit Word and Input Shift Register
INTEGRAL AND DIFFERENTIAL LINEARITY
GLITCH ENERGY
Daisy-Chain Operation
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
As long as SYNC is high, the SDO pin is in ahigh-impedance state. When SYNC is brought lowThe DAC7551 is controlled over a versatile 3-wire
the output of the internal shift register is tied to theserial interface, which operates at clock rates up to
SDO pin. As long as SYNC is low, SDO duplicates50MHz and is compatible with SPI, QSPI, Microwire,
the SDIN signal with a 16-cycle delay. To supportand DSP interface standards.
multiple devices in a daisy chain, SCLK and SYNCsignals are shared across all devices, and SDO ofone DAC7551 should be tied to the SDIN of the nextDAC7551. For ndevices in such a daisy chain, 16 nThe input shift register is 16 bits wide. DAC data are
SCLK cycles are required to shift the entire inputloaded into the device as a 16-bit word under the
data stream. After 16 nSCLK falling edges arecontrol of a serial clock input, SCLK, as shown in
received, following a falling SYNC, the data streamFigure 1 , the Serial Write Operation timing diagram.
becomes complete and SYNC can be brought highThe 16-bit word, illustrated in Table 1 , consists of
to update ndevices simultaneously. SDO operationfour control bits followed by 12 bits of DAC data. The
is specified at a maximum SCLK speed of 10MHz.data format is straight binary with all zeroescorresponding to 0V output and all ones
In daisy-chain mode, the use of a weak pull-downcorresponding to full-scale output (V
REF
– 1LSB).
resistor on the SDO output pin, which provides theData are loaded MSB first (bit 15) where the first two
SDIN data for the next device in the chain, isbits (DB15 and DB14) are don't care bits. Bit 13 and
recommended. For standalone operation, thebit 12 (DB13 and DB12) determine either normal
maximum clock speed is 50MHz. For daisy-chainmode operation or power-down mode (see Table 1 ).
operation, the maximum clock speed is 10MHz.The SYNC input is a level-triggered input that acts asa frame synchronization signal and chip enable. Datacan only be transferred into the device while SYNC
The DAC7551 uses precision thin-film resistorsis low. To start the serial data transfer, SYNC should
providing exceptional linearity and monotonicity.be taken low, observing the minimum SYNC to SCLK
Integral linearity error is typically within ±0.35LSBs,falling edge setup time, t
4
. After SYNC goes low,
and differential linearity error is typically withinserial data is shifted into the device input shift
±0.08LSBs.register on the falling edges of SCLK for 16 clockpulses.
The SPI interface is enabled after SYNC becomes
The DAC7551 uses a proprietary architecture thatlow and the data are continuously shifted into the
minimizes glitch energy. The code-to-code glitchesshift register at each falling edge of SCLK. When
are so low that they are usually buried within theSYNC is brought high, the last 16 bits stored in the
wide-band noise and cannot be easily detected. Theshift register are latched into the DAC register, and
DAC7551 glitch is typically well under 0.1nV-s. Suchthe DAC updates.
low glitch energy provides more than a ten-timeimprovement over industry alternatives.
Daisy-chain operation is used for updatingserially-connected devices on the rising edge ofSYNC.
Table 1. Serial Interface Programming
CONTROL DATA BITS
DB13 DB12DB15 DB14 (PD1) (PD0) DB11–DB0 FUNCTION
X X 0 0 data Normal modeX X 0 1 X Powerdown 1k ΩX X 1 0 X Powerdown 100k ΩX X 1 1 X Powerdown Hi-Z
13Submit Documentation Feedback
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APPLICATION INFORMATIONWAVEFORM GENERATION
GENERATING INDUSTRIAL VOLTAGE
GENERATING ±5V, ±10V, AND ±12V
Loop Accuracy
DAC7551
VREFH
DAC7551
_
+
Vdac
R2
R1
REF3140
VREF
Vtail
VOUT
OPA4130
VOUT +VREFǒR2
R1 )1ǓSDIN
4096 *Vtail ǒR2
R1Ǔ
(1)
Loop Speed
DAC7551
SLAS441E – MARCH 2005 – REVISED APRIL 2007
slow the loop down. With its 1MSPS (small-signal)maximum data update rate, DAC7551 can supportAs a result of the exceptional linearity and low glitch
high-speed control loops. Ultralow glitch energy ofof the DAC7551, the device is well-suited for
the DAC7551 significantly improves loop stability andwaveform generation (from DC to 10kHz). The
loop settling time.DAC7551 large-signal settling time is 5 µs, supportingan update rate of 200kSPS. However, the updaterates can exceed 1MSPS if the waveform to be
RANGESgenerated consists of small voltage steps betweenconsecutive DAC updates. To obtain a high dynamic
For control loop applications, DAC gain and offsetrange, REF3140 (4.096V) or REF02 (5.0V) are
errors are not important parameters. Thisrecommended for reference voltage generation.
consideration could be exploited to lower trim andcalibration costs in a high-voltage control circuitdesign. Using a quad operational amplifierOUTPUTS FOR PRECISION INDUSTRIAL (OPA4130 ), and a voltage reference (REF3140 ), theCONTROL DAC7551 can generate the wide voltage swingsrequired by the control loop.Industrial control applications can require multiplefeedback loops consisting of sensors, ADCs, MCUs,DACs, and actuators. Loop accuracy and loop speedare the two important parameters of such controlloops.
DAC offset, gain, and the integral linearity errors arenot factors in determining the accuracy of the loop.As long as a voltage exists in the transfer curve of amonotonic DAC, the loop can find it and settle to it.On the other hand, DAC resolution and differentiallinearity do determine the loop accuracy, because
Figure 28. Low-cost, Wide-swing Voltageeach DAC step determines the minimum incremental
Generator for Control Loop Applicationschange the loop can generate. A DNL error less than–1LSB (non-monotonicity) can create loop instability.
The output voltage of the configuration is given by:A DNL error greater than +1LSB impliesunnecessarily large voltage steps and missedvoltage targets. With high DNL errors, the loop losesits stability, resolution, and accuracy. Offering 12-bit
Fixed R1 and R2 resistors can be used to coarselyensured monotonicity and ±0.08LSB typical DNL
set the gain required in the first term of the equation.error, DAC755x devices are great choices for
Once R2 and R1 set the gain to include someprecision control loops.
minimal over-range, a single DAC7551 could beused to set the required offset voltages. Residualerrors are not an issue for loop accuracy becauseMany factors determine the control loop speed, such
offset and gain errors could be tolerated. Oneas ADC conversion time, MCU speed, and DAC
DAC7551 can provide the V
tail
voltages, while foursettling time. Typically, the ADC conversion time,
additional DAC7551 devices can provide V
dacand the MCU computation time are the two major
voltages to generate four high-voltage outputs. Afactors that dominate the time constant of the loop.
single SPI interface is sufficient to control all fiveDAC settling time is rarely a dominant factor because
DAC7551 devices in a daisy-chain configuration.ADC conversion times usually exceed DAC
For ±5V operation:conversion times. DAC offset, gain, and linearityerrors can slow the loop down only during the
R1 = 10k Ω, R2 = 15k Ω, V
tail
= 3.33V, V
REF
= 4.096Vstart-up. Once the loop reaches its steady-state
For ±10V operation:operation, these errors do not affect loop speed anyfurther. Depending on the ringing characteristics of
R1 = 10k Ω, R2 = 39k Ω, V
tail
= 2.56V, V
REF
= 4.096Vthe loop transfer function, DAC glitches can also
For ±12V operation:
R1 = 10k Ω, R2 = 49k Ω, V
tail
= 2.45V, V
REF
= 4.096V
14
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC7551IDRNR ACTIVE USON DRN 12 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Call Local Sales Office
DAC7551IDRNRG4 ACTIVE USON DRN 12 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
DAC7551IDRNT ACTIVE USON DRN 12 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Call Local Sales Office
DAC7551IDRNTG4 ACTIVE USON DRN 12 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC7551IDRNR USON DRN 12 3000 330.0 12.4 2.3 3.3 0.85 4.0 12.0 Q1
DAC7551IDRNT USON DRN 12 250 330.0 12.4 2.3 3.3 0.85 4.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Dec-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC7551IDRNR USON DRN 12 3000 340.5 338.1 20.6
DAC7551IDRNT USON DRN 12 250 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Dec-2009
Pack Materials-Page 2
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