0 1 2 3 4 5
0
20
40
60
80
100
120
SUPPLY CURRENT (A)
SUPPLY VOLTAGE (V)
-40°C
25°C
85°C
125°C
20 40 60 80 100
70
75
80
85
90
PROPAGATION DELAY (ns)
INPUT OVERDRIVE (mV)
Rising Edge
Falling Edge
VS= 5V
CLOAD=15pF
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV7235
,
LMV7239
SNOS532O –SEPTEMBER 2000–REVISED APRIL 2018
LMV7235 and LMV7239 75-ns, Ultra Low Power, Low Voltage, Rail-to-Rail Input
Comparator With Open-Drain and Push-Pull Output
1
1 Features
1• VS=5V,TA= 25°C (Typical Values Unless
Otherwise Specified)
• Propagation Delay: 75 ns
• Low supply Current: 65 µA
• Rail-to-Rail Input
• Open Drain and Push-Pull Output
• Ideal for 2.7-V and 5-V, Single-Supply
Applications
• Available in Space-Saving Packages:
– 5-Pin SOT-23
– 5-Pin SC70
2 Applications
• Portable and Battery-Powered Systems
• Set Top Boxes
• High-Speed Differential Line Receiver
• Window Comparators
• Zero-Crossing Detectors
• High-Speed Sampling Circuits
3 Description
The LMV7235 and LMV7239 are ultra low power, low
voltage, 75-ns comparators. They are ensured to
operate over the full supply voltage range of 2.7 V to
5.5 V. These devices achieve a 75-ns propagation
delay while consuming only 65 µA of supply current
at 5 V.
The LMV7235 and LMV7239 have a greater than rail-
to-rail common-mode voltage range. The input
common mode voltage range extends 200 mV below
ground and 200 mV above supply, allowing both
ground and supply sensing.
The LMV7235 features an open drain output. By
connecting an external resistor, the output of the
comparator can be used as a level shifter.
The LMV7239 features a push-pull output stage. This
feature allows operation without the need of an
external pullup resistor.
The LMV7235 and LMV7239 are available in the 5-
pin SC70 and 5-pin SOT-23 packages, which are
ideal for systems where small size and low power is
critical.
Device Information(1)
PART NUMBER PACKAGES BODY SIZE (NOM)
LMV7235, LMV7239 SOT-23 (5) 2.90 mm × 1.60 mm
SC70 (5) 2.00 mm × 1.25 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Supply Current vs. Supply Voltage Propagation Delay vs. Overdrive
2
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,
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics, 2.7 V ............................... 5
6.6 Electrical Characteristics, 5 V .................................. 6
6.7 Typical Characteristics.............................................. 7
7 Detailed Description............................................ 10
7.1 Overview................................................................. 10
7.2 Functional Block Diagram....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
8 Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Applications ................................................ 15
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support................. 20
11.1 Device Support...................................................... 20
11.2 Documentation Support ....................................... 20
11.3 Related Links ........................................................ 20
11.4 Receiving Notification of Documentation Updates 20
11.5 Community Resources.......................................... 20
11.6 Trademarks........................................................... 20
11.7 Electrostatic Discharge Caution............................ 20
11.8 Glossary................................................................ 21
12 Mechanical, Packaging, and Orderable
Information........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (April 2015) to Revision O Page
• Moved the LMV7239-Q1 automotive device to a standalone data sheet (SNOSD85).......................................................... 1
• Added minimum values for the input offset voltage in the Electrical Characteristics, 2.7 V table.......................................... 5
• Changed the input offset voltage typical value at room temperature from 0.8 to ±0.8 in the Electrical Characteristics,
2.7 V table .............................................................................................................................................................................. 5
• Added minimum values for the input offset voltage in the Electrical Characteristics, 5 V table............................................. 6
• Changed the input offset voltage typical value at room temperature from 1 to ±1 in the Electrical Characteristics, 5 V
table........................................................................................................................................................................................ 6
Changes from Revision M (February 2013) to Revision N Page
• Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions;
Specifications.Detailed DescriptionLayout;Device and Documentation Support;Mechanical, Packaging, and
Ordering Information............................................................................................................................................................... 1
Changes from Revision L (February 2013) to Revision M Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 1
Inverting
Input
5V+
V±
VOUT
Non-Inverting
Input 4
1
2
3
3
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,
LMV7239
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5 Pin Configuration and Functions
DBV and DGK Package
5-Pin SC70 and SOT-23
Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 VOUT O Output
2 V-P Negative Supply
3 IN+ I Noninverting Input
4 IN- I Inverting Input
5 V+P Positive Supply
4
LMV7235
,
LMV7239
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(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30mA over long term may adversely
affect reliability.
(3) Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Differential Input Voltage ± Supply Voltage V
Output Short Circuit Duration See (2)
Supply Voltage (V+- V−) 6 V
SOLDERING INFORMATION
Infrared or Convection (20 sec) 235 °C
Wave Soldering (10 sec) 260 (lead temp) °C
Voltage at Input/Output Pins (V+) +0.3, (V−)−0.3 V
Current at Input Pin (3) ±10 mA
Storage Temperature, Tstg –65 150 °C
Junction Temperature,TJ150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Machine model (MM) ±100
(1) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA) / θJA. All numbers apply for packages soldered directly onto a PCB.
6.3 Recommended Operating Conditions MIN MAX UNIT
Supply Voltages (V+- V−) 2.7 5.5 V
Temperature Range(1) –40 85 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1) LMV7235, LMV7239
UNITDGK (SC70) DBV (SOT-23)
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 478 265 °C/W
5
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(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
(3) CMRR is not linear over the common mode range. Limits are guaranteed over the worst case from 0 to VCC/2 or VCC/2 to VCC.
(4) A 10k pullup resistor was used when measuring the LMV7235. The rise time of the LMV7235 is a function of the R-C time constant.
(5) Propagation Delay Skew is defined as the absolute value of the difference between tPDLH and tPDHL.
6.5 Electrical Characteristics, 2.7 V
Unless otherwise specified, all limits ensured for TA= 25°C, VCM = V+/2, V+= 2.7 V, V−= 0 V−.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VOS Input Offset Voltage –6 ±0.8 +6 mV
At temp extremes –8 +8
IBInput Bias Current 30 400 nA
At temp extremes 600
IOS Input Offset Current 5 200 nA
At temp extremes 400
CMRR Common-Mode Rejection
Ratio 0 V < VCM < 2.7 V(3) 52 62 dB
PSRR Power Supply Rejection Ratio V+= 2.7 V to 5 V 65 85 dB
VCM Input Common-Mode Voltage
Range CMRR > 50 dB V−−0.1 −0.2 to 2.9 V++0.1 V
At temp extremes V−V+
VO
Output Swing High
(LMV7239 only)
IL= 4 mA,
VID = 500 mV V+−0.35 V+−0.26 V
IL= 0.4 mA,
VID = 500 mV V+−0.02 V
Output Swing Low
IL=−4 mA,
VID =−500 mV 230 350 mV
At temp extremes 450
IL=−0.4 mA,
VID =−500 mV 15 mV
ISC Output Short Circuit Current
Sourcing, VO= 0 V
(LMV7239 only) 15 mA
Sinking, VO= 2.7 V
(LMV7235, RL= 10 k) 20 mA
ISSupply Current No load 52 85 µA
At temp extremes 100
tPD Propagation Delay
Overdrive = 20 mV
CLOAD = 15 pF(4) 96 ns
Overdrive = 50 mV
CLOAD = 15 pF(4) 87 ns
Overdrive = 100 mV
CLOAD = 15 pF(4) 85 ns
tSKEW Propagation Delay Skew
(LMV7239 only) Overdrive = 20 mV(5) 2 ns
trOutput Rise Time
LMV7239/LMV7239Q
10% to 90% 1.7 ns
LMV7235
10% to 90%(4) 112 ns
tfOutput Fall Time 90% to 10% 1.7 ns
ILEAKAGE Output Leakage Current
(LMV7235 only) 3 nA
6
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(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on
shipped production material.
(3) A 10k pullup resistor was used when measuring the LMV7235. The rise time of the LMV7235 is a function of the R-C time constant.
(4) Propagation Delay Skew is defined as the absolute value of the difference between tPDLH and tPDHL.
6.6 Electrical Characteristics, 5 V
Unless otherwise specified, all limits ensured for TA= 25°C, VCM = V+/2, V+= 5 V, V−= 0 V.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
VOS Input Offset Voltage –6 ±1 +6 mV
At temp extremes –8 +8
IBInput Bias Current 30 400 nA
At temp extremes 600
IOS Input Offset Current 5 200 nA
At temp extremes 400
CMRR Common-Mode Rejection
Ratio 0 V < VCM < 5 V 52 67 dB
PSRR Power Supply Rejection Ratio V+= 2.7 V to 5 V 65 85 dB
VCM Input Common-Mode Voltage
Range CMRR > 50dB V−−0.1 −0.2 to
5.2 V++0.1 V
At temp extremes V−V+
VO
Output Swing High
(LMV7239 only)
IL= 4 mA,
VID = 500 mV V+−0.25 V+−0.15 V
IL= 0.4 mA,
VID = 500 mV V+−0.01 V
Output Swing Low
IL=−4 mA,
VID =−500 mV 230 350 mV
At temp extremes 450
IL=−0.4 mA,
VID =−500 mV 10 mV
ISC Output Short Circuit Current
Sourcing, VO= 0 V
(LMV7239 only) 25 55 mA
At temp extremes 15
Sinking, VO= 5 V
(LMV7235, RL= 10k) 30 60 mA
At temp extremes 20
ISSupply Current No load 65 95 µA
At temp extremes 110
tPD Propagation Delay
Overdrive = 20 mV
CLOAD = 15 pF(3) 89 ns
Overdrive = 50 mV
CLOAD = 15 pF(3) 82 ns
Overdrive = 100 mV
CLOAD = 15 pF(3) 75 ns
tSKEW Propagation Delay Skew
(LMV7239 only) Overdrive = 20 mV(4) 1 ns
trOutput Rise Time
LMV7239
10% to 90% 1.2 ns
LMV7235
10% to 90% 100 ns
tfOutput Fall Time 90% to 10% 1.2 ns
ILEAKAGE Output Leakage Current
(LMV7235 only) 3 nA
5
-0.2 1234
-50
-40
-30
-20
-10
0
10
20
30
40
50
INPUT BIAS CURRENT (nA)
VIN (V)
VS = 5V
IBIAS+
IBIAS-
.01 .1 1 10
OUTPUT VOLTAGE REFERENCED TO GND (V)
.1
1
10
100
ISINK (mA)
VS = 2.7V
.01 .1 1 10
OUTPUT VOLTAGE REFERENCED TO GND (V)
.1
1
10
100
ISINK (mA)
VS = 5V
10
OUTPUT VOLTAGE REFERENCED TO V+ (V)
.01 .1 1
.1
1
10
100
ISOURCE (mA)
VS = 5V
0 1 2 3 4 5
0
20
40
60
80
100
120
SUPPLY CURRENT (A)
SUPPLY VOLTAGE (V)
-40°C
25°C
85°C
125°C
7
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6.7 Typical Characteristics
(Unless otherwise specified, VS= 5V, CL= 10pF, TA= 25°C).
Figure 1. Supply Current vs. Supply Voltage Figure 2. Sourcing Current vs. Output Voltage
Figure 3. Sourcing Current vs. Output Voltage Figure 4. Sinking Current vs. Output Voltage
Figure 5. Sinking Current vs. Output Voltage Figure 6. Input Bias Current vs. Input Voltage
0 20 40 60 80 100
88
90
92
94
96
PROPAGATION DELAY (ns)
CAPACITANCE (pF)
Rising Edge
Falling Edge
VS= 5V
VOD=20mV
20 30 40 50 60 70 80 90 100
80
85
90
95
100
PROPAGATION DELAY (ns)
INPUT OVERDRIVE (mV)
Rising Edge
Falling Edge
VS= 2.7V
CLOAD=15pF
-40 -20 0 20 40 60 80 100 120 140
80
90
100
110
120
130
140
PROPAGATION DELAY (ns)
TEMPERATURE (°C)
VS=5V
VOD=20mV
CLOAD=15pF
Falling Edge
Rising Edge
0 20 40 60 80 100
94
96
98
100
102
104
106
PROPAGATION DELAY (ns)
CAPACITANCE (pF)
Rising Edge
Falling Edge
VS= 2.7V
VOD=20mV
012
-50
-40
-30
-20
-10
0
10
20
30
50
INPUT BIAS CURRENT (nA)
VIN (V)
2.7
VS = 2.7V
IBIAS-
IBIAS+
60
-60
70
40
-40 -20 0 20 40 60 80 100 120 140
80
90
100
110
120
130
140
150
160
PROPAGATION DELAY (ns)
TEMPERATURE (°C)
VS=2.7V
VOD=20mV
CLOAD=15pF
Falling Edge
Rising Edge
8
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Typical Characteristics (continued)
(Unless otherwise specified, VS= 5V, CL= 10pF, TA= 25°C).
Figure 7. Input Bias Current vs. Input Voltage Figure 8. Propagation Delay vs. Temperature
Figure 9. Propagation Delay vs. Temperature Figure 10. Propagation Delay vs. Capacitive Load
Figure 11. Propagation Delay vs. Capacitive Load Figure 12. Propagation Delay vs. Input Overdrive
0 1 2 3 4 5
80
90
100
110
PROPAGATION DELAY (ns)
INPUT COMMON MODE VOLTAGE (V)
Rising Edge
Falling Edge
VS= 5V
VOD=20mV
CLOAD=15pF
20 40 60 80 100
70
75
80
85
90
PROPAGATION DELAY (ns)
INPUT OVERDRIVE (mV)
Rising Edge
Falling Edge
VS= 5V
CLOAD=15pF
0.0 0.5 1.0 1.5 2.0 2.5 3.0
80
85
90
95
100
105
110
115
120
PROPAGATION DELAY (ns)
INPUT COMMON MODE VOLTAGE (V)
Rising Edge Falling Edge
VS= 2.7V
VOD=20mV
CLOAD=15pF
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Typical Characteristics (continued)
(Unless otherwise specified, VS= 5V, CL= 10pF, TA= 25°C).
Figure 13. Propagation Delay vs. Input Overdrive Figure 14. Propagation Delay vs. Common-Mode Voltage
Figure 15. Propagation Delay vs. Common-Mode Voltage
10
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7 Detailed Description
7.1 Overview
The LMV7235 and LMV7239 are ultra low power, low voltage, 75-ns comparators. They are ensured to operate
over the full supply voltage range of 2.7 V to 5.5 V. These devices achieve a 75-ns propagation delay while
consuming only 65 µA of supply current at 5 V.
The LMV7235 and LMV7239 have a greater than rail-to-rail common-mode voltage range. The input common-
mode voltage range extends 200 mV below ground and 200 mV above supply, allowing both ground and supply
sensing.
7.2 Functional Block Diagram
Figure 16. Simplified Schematic of LMV7239
7.3 Feature Description
7.3.1 Input Stage
The LMV7235 and LMV7239 are rail-to-rail input and output. The typical input common-mode voltage range of
−0.2 V below the ground to 0.2 V above the supply. The LMV7235 and LMV7239 use a complimentary PNP and
NPN input stage in which the PNP stage senses common-mode voltage near V−and the NPN stage senses
common-mode voltage near V+. If either of the input signals falls below the negative common mode limit, the
parasitic PN junction formed by the substrate and the base of the PNP will turn on resulting in an increase of
input bias current.
If one of the inputs goes above the positive common mode limit, the output will still maintain the correct logic
level as long as the other input stays within the common mode range. However, the propagation delay will
increase. When both inputs are outside the common-mode voltage range, current saturation occurs in the input
stage, and the output becomes unpredictable.
The propagation delay does not increase significantly with large differential input voltages. However, large
differential voltages greater than the supply voltage should be avoided to prevent damage to the input stage.
7.3.2 Output Stage: LMV7239
The LMV7239 has a push-pull output. When the output switches, there is a low resistance path between VCC and
ground, causing high output sinking or sourcing current during the transition.
11
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Feature Description (continued)
Figure 17. LMV7239 Push-Pull Output Stage
7.3.3 Output Stage: LMV7235
The LMV7235 has an open drain that requires a pull-up resistor to a positive supply voltage for the output to
switch properly. The internal circuitry is identical to the LMV7239 except that the upper P channel output device
M4 is absent in the Functional Block Diagram above. When the internal output transistor is off, the output voltage
will be pulled up to the external positive voltage by the external pull-up resistor. This allows the output to be
OR'ed with other open drain outputs on the same bus. The output pull-up resistor can be connected to any
voltage level between V- and V+ for level shifting applications.
Figure 18. LMV7235 Open Drain Output
7.4 Device Functional Modes
7.4.1 Capacitive and Resistive Loads
The propagation delay on the rising edge of the LMV7235 depends on the load resistance and capacitance
values.
7.4.2 Noise
Most comparators have rather low gain. This allows the output to spend time between high and low when the
input signal changes slowly. The result is the output may oscillate between high and low when the differential
input is near zero. The high gain of this comparator eliminates this problem. Less than 1 μV of change on the
input will drive the output from one rail to the other rail. If the input signal is noisy, the output cannot ignore the
noise unless some hysteresis is provided by positive feedback. (See Hysteresis.)
7.4.3 Hysteresis
To improve propagation delay when low overdrive is needed hysteresis can be added.
REF 1 2
IN1 2
V (R R )
VR
'
CC 1 2
A1 2 1 3 2 3
V R R
VR R R R R R
'
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Device Functional Modes (continued)
7.4.3.1 Inverting Comparator With Hysteresis
The inverting comparator with hysteresis requires a three resistor network that is referenced to the supply voltage
V+of the comparator as shown in Figure 19. When VIN at the inverting input is less than VA, the voltage at the
noninverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VOswitches as
high as V+). The three network resistors can be represented as R1//R3in series with R2.
Figure 19. Inverting Comparator With Hysteresis
The lower input trip voltage VA1 is defined as:
VA1 = VCCR2/ [(R1// R3)+R2)] (1)
When VIN is greater than VA, the output voltage is low or very close to ground. In this case the three network
resistors can be presented as R2// R3in series with R1.
The upper trip voltage VA2 is defined as:
VA2 = VCC (R2// R3) / [(R1) + (R2// R3)] (2)
The total hysteresis provided by the network is defined as ΔVA= VA1 - VA2.
(3)
7.4.3.2 Non-Inverting Comparator With Hysteresis
A noninverting comparator with hysteresis requires a two resistor network, and a voltage reference (VREF) at the
inverting input. When VIN is low, the output is also low. For the output to switch from low to high, VIN must rise up
to VIN1 where VIN1 is calculated by:
(4)
As soon as VOswitches to VCC, VAsteps to a value greater than VREF which is given by:
VCC
VO
R2
R1
VA+
-
VREF
RL
VIN
REF 1 2 CC 1
IN2 2
V (R R ) V R
VR
CC IN1 1
A IN 1 2
(V V )R
V V R R
13
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Device Functional Modes (continued)
(5)
To make the comparator switch back to its low state, VIN must equal VREF before VAwill again equal VREF. VIN2
can be calculated by:
(6)
The hysteresis of this circuit is the difference between VIN1 and VIN2.
ΔVIN = VCCR1/ R2(7)
Figure 20. Noninverting Comparator With Hysteresis
Figure 21. Noninverting Comparator Thresholds
7.4.4 Zero Crossing Detector
In a zero crossing detector circuit, the inverting input is connected to ground and the noninverting input is
connected to a 100 mVPP AC signal. As the signal at the noninverting input crosses 0V, the comparator’s output
changes state.
Figure 22. Simple Zero Crossing Detector
7.4.4.1 Zero Crossing Detector With Hysteresis
To improve switching times and centering the input threshold to ground a small amount of positive feedback is
added to the circuit. Voltage divider R4and R5establishes a reference voltage, V1, at the positive input. By
making the series resistance, R1plus R2equal to R5, the switching condition, V1= V2, will be satisfied when VIN
= 0.
The positive feedback resistor, R6, is made very large with respect to R5|| R6= 2000 R5). The resultant
hysteresis established by this network is very small (ΔV1< 10 mV) but it is sufficient to insure rapid output
voltage transitions.
R2
R4
VO
R5
R6
R3
V2
+
-
R1
VIN
D1
VCC
V1
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Device Functional Modes (continued)
Diode D1is used to ensure that the inverting input terminal of the comparator never goes below approximately
−100 mV. As the input terminal goes negative, D1will forward bias, clamping the node between R1and R2to
approximately −700 mV. This sets up a voltage divider with R2and R3preventing V2from going below ground.
The maximum negative input overdrive is limited by the current handling ability of D1.
Figure 23. Zero Crossing Detector With Hysteresis
7.4.5 Threshold Detector
Instead of tying the inverting input to 0 V, the inverting input can be tied to a reference voltage. As the input on
the noninverting input passes the VREF threshold, the comparator’s output changes state. It is important to use a
stable reference voltage to ensure a consistent switching point.
Figure 24. Threshold Detector
CC 2
A1 2 1 3
V R
VR R R
˜
R
C1
R4
VO
R2
R3
R1 VA
+
-
VC
V+
0
V+
15
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,
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV7235 and LMV7239 are single supply comparators with 75 ns of propagation delay and only 65 µA of
supply current.
8.2 Typical Applications
8.2.1 Square Wave Oscillator
Figure 25. Square Wave Oscillator
8.2.1.1 Design Requirements
A typical application for a comparator is as a square wave oscillator. The circuit in Figure 25 generates a square
wave whose period is set by the RC time constant of the capacitor C1and resistor R4.
8.2.1.2 Detailed Design Procedure
The maximum frequency is limited by the large signal propagation delay of the comparator and by the capacitive
loading at the output, which limits the output slew rate.
Figure 26. Square Wave Oscillator Timing Thresholds
Consider the output of Figure 25 to be high to analyze the circuit. That implies that the inverted input (VC) is
lower than the noninverting input (VA). This causes the C1to be charged through R4, and the voltage VC
increases until it is equal to the noninverting input. The value of VAat this point is:
(8)
If R1= R2= R3, then V A1 =2Vcc/3
-1
0
1
2
3
4
5
6
0 10 20 30 40 50
VOUT (V)
TIME (µs)
C001
VOUT
Va
Vc
CC 2 3
A2 1 2 3
V (R R )
VR (R R )
R
R
16
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,
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Typical Applications (continued)
At this point the comparator switches pulling down the output to the negative rail. The value of VAat this point is:
(9)
If R1= R2= R3, then VA2 = VCC/3.
The capacitor C1now discharges through R4, and the voltage VCdecreases until it is equal to VA2, at which point
the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it
takes to discharge C1from 2VCC/3 to VCC/3, which is given by R4C1·ln2. Hence the formula for the frequency is:
F = 1/(2·R4·C1·ln2) (10)
The LMV7239 should be used for a symmetrical output. The LMV7235 will require a pullup resistor on the output
to function, and will have a slightly asymmetrical output due to the reduced sourcing current.
8.2.1.3 Application Curves
Figure 27 shows the simulated results of an oscillator using the following values:
1. R1= R2= R3= R4= 100 kΩ
2. C1= 100 pF, CL= 20 pF
3. V+ = 5 V, V– = GND
4. CSTRAY (not shown) from Va to GND = 10 pF
Figure 27. Square Wave Oscillator Output Waveform
8.2.2 Crystal Oscillator
A simple crystal oscillator using the LMV7235 or LMV7239 is shown in Figure 28. Resistors R1and R2set the
bias point at the comparator’s noninverting input. Resistors, R3and R4and capacitor C1set the inverting input
node at an appropriate DC average level based on the output. The crystal’s path provides resonant positive
feedback and stable oscillation occurs. The output duty cycle for this circuit is roughly 50%, but it is affected by
resistor tolerances and to a lesser extent by the comparator
V+
R1
R2
R3
-
+
-
+OUTPUT A
OUTPUT B
VREF2
VREF1
A
B
VIN
Crystal
100K
VOUT
0.1uF
VCC
100K
100K
17
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,
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Typical Applications (continued)
Figure 28. Crystal Oscillator
8.2.3 Infrared (IR) Receiver
The LMV7235 and LMV7239 can also be used as an infrared receiver. The infrared photo diode creates a
current relative to the amount of infrared light present. The current creates a voltage across RD. When this
voltage level cross the voltage applied by the voltage divider to the inverting input, the output transitions.
Figure 29. IR Receiver
8.2.4 Window Detector
Figure 30. Window Detector
A window detector monitors the input signal to determine if it falls between two voltage levels. Both outputs are
true (high) when VREF1 < VIN < VREF2
V+
VREF2
VREF1
BOTH OUTPUTS
ARE HIGH
OUTPUT A
OUTPUT B
VIN
18
LMV7235
,
LMV7239
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Typical Applications (continued)
Figure 31. Window Detector Output Signal
The comparator outputs A and B are high only when VREF1 < VIN < VREF2, or "within the window", where these are
defined as:
VREF1 = R3/R1+R2+R3) × V+ (11)
VREF2 = R2+R3)/R1+R2+R3) × V+ (12)
To determine if the input signal falls outside of the two voltage levels, both inputs on each comparators can be
reversed to invert the logic.
The LMV7235 with an open drain output should be used if the outputs are to be tied together for a common logic
output.
Other names for window detectors are: threshold detector, level detector, and amplitude trigger or detector.
9 Power Supply Recommendations
To minimize supply noise, power supplies should be decoupled by a 0.01-μF ceramic capacitor in parallel with a
10-μF capacitor.
Due to the nanosecond edges on the output transition, peak supply currents will be drawn during the time the
output is transitioning. Peak current depends on the capacitive loading on the output. The output transition can
cause transients on poorly bypassed power supplies. These transients can cause a poorly bypassed power
supply to "ring" due to trace inductance and low self-resonance frequency of high ESR bypass capacitors.
Treat the LMV7235 and LMV72391 as high-speed devices. Keep the ground paths short and place small (low
ESR ceramic) bypass capacitors directly between the V+ and V– pins.
Output capacitive loading and output toggle rate will cause the average supply current to rise over the quiescent
current.
19
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,
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10 Layout
10.1 Layout Guidelines
Proper grounding and the use of a ground plane will help to ensure the specified performance of the LMV7235
and LMV72391. Minimizing trace lengths, reducing unwanted parasitic capacitance and using surface-mount
components will also help. Comparators are very sensitive to input noise.
The LMV7235 and LMV72391 require a high-speed layout. Follow these layout guidelines:
1. Use printed-circuit board with a good, unbroken low-inductance ground plane.
2. Place a decoupling capacitor (0.1-µF, ceramic surface-mount capacitor) as close as possible to VCC pin.
3. On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback
around the comparator. Keep inputs away from output.
4. Solder the device directly to the printed-circuit board rather than using a socket.
5. For slow moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some
degradation to tPD when the source impedance is low.
6. The top-side ground plane runs between the output and inputs.
7. Ground trace from the ground pin runs under the device up to the bypass capacitor, shielding the inputs from
the outputs.
10.2 Layout Example
Figure 32. SOT-23 Board Layout Example
20
LMV7235
,
LMV7239
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Submit Documentation Feedback Copyright © 2000–2018, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LMV7239 TINA SPICE Model, SNOM392
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
11.2 Documentation Support
11.2.1 Related Documentation
A Quad of Independently Func Comparators (SNOA654)
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
LMV7235 Click here Click here Click here Click here Click here
LMV7239 Click here Click here Click here Click here Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
21
LMV7235
,
LMV7239
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Submit Documentation FeedbackCopyright © 2000–2018, Texas Instruments Incorporated
11.8 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Apr-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV7235M5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 C21A
LMV7235M5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C21A
LMV7235M5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 C21A
LMV7235M5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C21A
LMV7235M7 NRND SC70 DCK 5 1000 TBD Call TI Call TI -40 to 85 C21
LMV7235M7/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C21
LMV7235M7X/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C21
LMV7239M5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 C20A
LMV7239M5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C20A
LMV7239M5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 C20A
LMV7239M5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C20A
LMV7239M7 NRND SC70 DCK 5 1000 TBD Call TI Call TI -40 to 85 C20
LMV7239M7/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C20
LMV7239M7X NRND SC70 DCK 5 3000 TBD Call TI Call TI -40 to 85 C20
LMV7239M7X/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C20
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Apr-2018
Addendum-Page 2
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMV7239 :
•Automotive: LMV7239-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMV7235M5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7235M5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7235M5X SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7235M5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7235M7 SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7235M7/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7235M7X/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7239M5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7239M5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7239M5X SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7239M5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV7239M7 SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7239M7/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7239M7X SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7239M7X/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Apr-2018
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV7235M5 SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV7235M5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV7235M5X SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV7235M5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV7235M7 SC70 DCK 5 1000 210.0 185.0 35.0
LMV7235M7/NOPB SC70 DCK 5 1000 210.0 185.0 35.0
LMV7235M7X/NOPB SC70 DCK 5 3000 210.0 185.0 35.0
LMV7239M5 SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV7239M5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV7239M5X SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV7239M5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV7239M7 SC70 DCK 5 1000 210.0 185.0 35.0
LMV7239M7/NOPB SC70 DCK 5 1000 210.0 185.0 35.0
LMV7239M7X SC70 DCK 5 3000 210.0 185.0 35.0
LMV7239M7X/NOPB SC70 DCK 5 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Apr-2018
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
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associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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