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FIGURE 27. Demo Board Schematic .......................................................................................................... 104
FIGURE 28. Top Silkscreen ..................................................................................................................... 105
FIGURE 29. Top Layer ........................................................................................................................... 105
FIGURE 30. Inner Layer 2 ....................................................................................................................... 106
FIGURE 31. Inner Layer 3 ....................................................................................................................... 106
FIGURE 32. Bottom Layer ...................................................................................................................... 107
FIGURE 33. Bottom Silkscreen ................................................................................................................. 107
List of Tables
TABLE 1. Device Register Map .................................................................................................................. 32
TABLE 2. Nonzero I2C Default Registers ....................................................................................................... 35
TABLE 3. PMC_SETUP (0x00h) ................................................................................................................. 36
TABLE 4. PMC_SETUP (0x01h) ................................................................................................................. 37
TABLE 5. PMC_SETUP (0x02h) ................................................................................................................ 37
TABLE 6. DAC Clock Requirements ............................................................................................................. 38
TABLE 7. ADC Clock Requirements ............................................................................................................. 38
TABLE 8. PLL Settings for Common System Clock Frequencies .......................................................................... 40
TABLE 9. PLL_CLOCK_SOURCE (0x03h) .................................................................................................... 41
TABLE 10. PLL_M (0x04h) ........................................................................................................................ 42
TABLE 11. PLL_N (0x05h) ........................................................................................................................ 42
TABLE 12. PLL_N_MOD (0x06h) ................................................................................................................ 42
TABLE 13. PLL_P1 (0x07h) ....................................................................................................................... 43
TABLE 14. PLL_P2 (0x08h) ....................................................................................................................... 43
TABLE 15. CLASS_D_OUTPUT (0x10h) ....................................................................................................... 44
TABLE 16. LEFT HEADPHONE_OUTPUT (0x11h) .......................................................................................... 45
TABLE 17. RIGHT HEADPHONE_OUTPUT (0x12h) ........................................................................................ 45
TABLE 18. AUX_OUTPUT (0x13h) .............................................................................................................. 46
TABLE 19. OUTPUT_OPTIONS (0x14h) ....................................................................................................... 47
TABLE 20. ADC_INPUT (0x15h) ................................................................................................................. 48
TABLE 21. MIC_INPUT (0x16h) ................................................................................................................. 48
TABLE 22. AUX_LEVEL (0x18h) ................................................................................................................. 49
TABLE 23. MONO_LEVEL (0x19h) .............................................................................................................. 50
TABLE 24. HP_SENSE (0x1Bh) ................................................................................................................. 52
TABLE 25. ADC Basic (0x20h) ................................................................................................................... 53
TABLE 26. ADC_CLK_DIV (0x21h) ............................................................................................................. 53
TABLE 27. ADC_MIXER (0x23h) ................................................................................................................ 54
TABLE 28. DAC Basic (0x30h) .................................................................................................................. 55
TABLE 29. DAC_CLK_DIV (0x31h) ............................................................................................................. 55
TABLE 30. Input Levels 1 (0x40h) ............................................................................................................... 57
TABLE 31. Input Levels 2 (0x41h) ............................................................................................................... 57
TABLE 32. Audio Port 1 Input (0x42h) .......................................................................................................... 58
TABLE 33. Audio Port 2 Input (0x43h) .......................................................................................................... 58
TABLE 34. DAC Input Select (0x44h) ........................................................................................................... 59
TABLE 35. Decimator Input Select (0x45h) .................................................................................................... 59
TABLE 36. BASIC_SETUP (0x50h/0x60h) ..................................................................................................... 61
TABLE 37. CLK_GEN_1 (0x51h/0x61h) ........................................................................................................ 61
TABLE 38. CLK_GEN_1 (0x52h/62h) ........................................................................................................... 62
TABLE 39. CLK_GEN_1 (0x53h/63h) ........................................................................................................... 62
TABLE 40. DATA_WIDTHS (0x54h/64h) ....................................................................................................... 63
TABLE 41. RX_MODE (0x55h/x65h) ............................................................................................................ 64
TABLE 42. TX_MODE (0x56h/x66h) ............................................................................................................ 65
TABLE 43. ADC EFFECTS (0x70h) ............................................................................................................. 66
TABLE 44. DAC EFFECTS (0x71h) ............................................................................................................. 67
TABLE 45. HPF MODE (0x80h) .................................................................................................................. 67
TABLE 46. ADC_ALC_1 (0x81h) ................................................................................................................. 70
TABLE 47. ADC_ALC_2 (0x82h) ................................................................................................................. 70
TABLE 48. ADC_ALC_3 (0x83h) ................................................................................................................. 71
TABLE 49. ADC_ALC_4 (0x84h) ................................................................................................................. 72
TABLE 50. ADC_ALC_5 (0x85h) ................................................................................................................. 73
TABLE 51. ADC_ALC_6 (0x86h) ................................................................................................................ 74
TABLE 52. ADC_ALC_7 (0x87h) ................................................................................................................ 74
TABLE 53. ADC_ALC_8 (0x88h) ................................................................................................................. 74
TABLE 54. ADC_L_LEVEL (0x89h) ............................................................................................................ 75
TABLE 55. ADC_R_LEVEL (0x8Ah) ............................................................................................................. 76
TABLE 56. EQ_BAND_1 (0x8Bh) ................................................................................................................ 77
TABLE 57. EQ_BAND_2 (0x8Ch) ................................................................................................................ 78
TABLE 58. EQ_BAND_3 (0x8Dh) ................................................................................................................ 79
TABLE 59. EQ_BAND_4 (0x8Eh) ................................................................................................................ 80
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