© Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 3 1Publication Order Number:
MAX1720/D
MAX1720
Switched Capacitor Voltage
Inverter with Shutdown
The MAX1720 is a CMOS charge pump voltage inverter that is
designed for operation over an input voltage range of 1.15 V to 5.5 V
with an output current capability in excess of 50 mA. The operating
current consumption is only 67 mA, and a power saving shutdown
input is provided to further reduce the current to a mere 0.4 mA. The
device contains a 12 kHz oscillator that drives four low resistance
MOSFET switches, yielding a low output resistance of 26 W and a
voltage conversion efficiency of 99%. This device requires only two
external 10 mF capacitors for a complete inverter making it an ideal
solution for numerous battery powered and board level applications.
The MAX1720 is available in the space saving TSOP−6 package.
Features
Operating Voltage Range of 1.15 V to 5.5 V
Output Current Capability in Excess of 50 mA
Low Current Consumption of 67 mA
Power Saving Shutdown Input for a Reduced Current of 0.4 mA
Operation at 12 kHz
Low Output Resistance of 26 W
Space Saving TSOP−6 Package
Pb−Free Package is Available
Typical Applications
LCD Panel Bias
Cellular Telephones
Pagers
Personal Digital Assistants
Electronic Games
Digital Cameras
Camcorders
Hand Held Instruments
6
4
2
3
1
Figure 1. Typical Application
−Vout
Vin 5
This device contains 77 active transistors.
PIN CONNECTIONS
1
3GND
Vout
2
C− 4
C+6
(Top View)
TSOP−6
SN SUFFIX
CASE 318G
MARKING DIAGRAM
Device Package Shipping
ORDERING INFORMATION
MAX1720EUT TSOP−6 3000 Tape & Reel
5SHDN
EACAYW G
G
1
6
1
EAC = Device Code
A = Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
Vin
MAX1720EUTG TSOP−6
(Pb−Free) 3000 Tape & Reel
(Note: Microdot may be in either location)
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For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
MAX1720
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2
MAXIMUM RATINGS*
Rating Symbol Value Unit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Voltage Range (Vin to GND)
ÁÁÁÁ
ÁÁÁÁ
Vin
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
−0.3 to 6.0
ÁÁÁÁ
ÁÁÁÁ
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output Voltage Range (Vout to GND)
ÁÁÁÁ
ÁÁÁÁ
Vout
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
−6.0 to 0.3
ÁÁÁÁ
ÁÁÁÁ
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output Current (Note 1)
ÁÁÁÁ
ÁÁÁÁ
Iout
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
100
ÁÁÁÁ
ÁÁÁÁ
mA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output Short Circuit Duration (Vout to GND, Note 1)
ÁÁÁÁ
ÁÁÁÁ
tSC
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
Indefinite
ÁÁÁÁ
ÁÁÁÁ
sec
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Operating Junction Temperature
ÁÁÁÁ
ÁÁÁÁ
TJ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
150
ÁÁÁÁ
ÁÁÁÁ
°C
Power Dissipation and Thermal Characteristics
Thermal Resistance, Junction−to−Air
Maximum Power Dissipation @ TA = 70°CRqJA
PD256
313 °C/W
mW
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Storage Temperature
ÁÁÁÁ
ÁÁÁÁ
Tstg
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
−55 to 150
ÁÁÁÁ
ÁÁÁÁ
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
*ESD Ratings
ESD Machine Model Protection up to 200 V, Class B
ESD Human Body Model Protection up to 2000 V, Class 2
ELECTRICAL CHARACTERISTICS (Vin = 5.0 V, C1 = 10 mF, C2 = 10 mF, TA = −40°C to 85°C, ty pical values shown are for TA = 25°C
unless otherwis e noted. See Figure 14 for Tes t Set up.)
Characteristic Symbol Min Typ Max Unit
Operating Supply Voltage Range (SHDN = Vin, RL = 10 k) Vin 1.5 to 5.5 1.15 to 6.0 V
Supply Current Device Operating (SHDN = 5.0 V, RL = R)
TA = 25°C
TA = 85°C
Iin
67
72 90
100
mA
Supply Current Device Shutdown (SHDN = 0 V)
TA = 25°C
TA = 85°C
ISHDN
0.4
1.6
mA
Oscillator Frequency
TA = 25°C
TA = −40°C to 85°C
fOSC 8.4
6.0 12
15.6
21
kHz
Output Resistance (Iout = 25 mA, Note 2) Rout 26 50 W
Voltage Conversion Efficiency (RL = R) VEFF 99 99.9 %
Power Conversion Efficiency (RL = 1.0 k) PEFF 96 %
Shutdown Input Threshold Voltage (Vin = 1.5 V to 5.5 V)
High State, Device Operating
Low State, Device Shutdown
Vth(SHDN)
0.6 Vin
0.5 Vin
V
Shutdown Input Bias Current
High State, Device Operating, SHDN = 5.0 V
TA = 2
TA = 85°C5°C
Low State, Device Shutdown, SHDN = 0 V
TA = 25°C
TA = 85°C
IIH
IIL
5.0
100
5.0
100
pA
Wake−Up Time from Shutdown (RL = 1.0 k) tWKUP 1.2 ms
1. Maximum Package power dissipation limits must be observed to ensure that the maximum junction temperature is not exceeded.
TJ+TA)(PDRqJA)
2. Capacitors C1 and C2 contribution is approximately 20% of the total output resistance.
MAX1720
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Vin, SUPPLY VOLTAGE (V)
fOSC, OSCILLATOR FREQUENCY (kHz)
1.5 3.02.52.0 3.5 4.0 4.5 5.0
0
35
30
25
20
502010
15
10
5
040
C1, C2, C3, CAPACITANCE (mF)
I
out
, OUTPUT CURRENT (mA)
30
Rout, OUTPUT RESISTANCE (W)
Vin, SUPPLY VOLTAGE (V)
80
70
60
50
40
30
10.5
10.0
11.0
11.5
12.0
12.5
13.0
70
50
80
40
60
20
90
Figure 2. Output Resistance vs. Supply Voltage Figure 3. Output Resistance vs. Ambient
Temperature
Figure 4. Output Current vs. Capacitance Figure 5. Output Voltage Ripple vs.
Capacitance
Figure 6. Supply Current vs. Supply Voltage Figure 7. Oscillator Frequency vs. Ambient
Temperature
30
TA, AMBIENT TEMPERATURE (°C)
−50 25 10
0
−25 0 50 75
Rout, OUTPUT RESISTANCE (W)
05
0
2010 4030
200
100
250
50
150
0
300
350
400
Vout, OUTPUT VOLTAGE RIPPLE (mVp−p)
I
in
, SUPPLY CURRENT (
m
A)
−50 25 10
0
−25 0 50 75
TA, AMBIENT TEMPERATURE (°C)
C1, C2, C3, CAPACITANCE (mF)
Vin = 1.5 V
TA = 85°C
Figure 14 Test Setup
Vin = 2.0 V
Vin = 3.3 V
Vin = 5.0 V
Vin = 4.75 V
Vout = −4.00 V
Vin = 3.15 V
Vout = −2.50 V
Vin = 1.90 V
Vout = −1.50 V
Figure 14 Test Setup
TA = 25°C
Figure 14 Test Setup
RL =
TA = 25°CTA = −40°CVin = 1.5 V
Vin = 3.3 V
Vin = 5.0 V
Figure 14 Test Setup
Figure 14 Test Setup
TA = 25°C
20
60
40
80
70
50
30
90
100
1.0 5.03.52.5 5.54.54.03.02.01.5
Figure 14 Test Setup
TA = 25°C
Vin = 4.75 V
Vout = −4.00 V
Vin = 3.15 V
Vout = −2.50 V
Vin = 1.90 V
Vout = −1.50 V
MAX1720
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4
5.0
4.5
3.5
4.0
3.0
2.5
1.5
80
60
90
50
70
40
100
1.00
0
−2.0
30
−5.0
2010
Vout, OUTPUT VOLTAGE (V)
−6.0
Iout, OUTPUT CURRENT (mA)
Figure 8. Output Voltage vs. Output Current Figure 9. Power Conversion Efficiency vs.
Output Current
h, POWER CONVERSION EFFICIENCY (%
)
Figure 10. Output Voltage Ripple and Noise
TIME = 25 ms / Div.
Figure 11. Shutdown Supply Current vs.
Ambient Temperature
TA, AMBIENT TEMPERATURE (°C)
ISHDN, SHUTDOWN SUPPLY CURRENT (mA)
OUTPUT VOLTAGE RIPPLE AND
NOISE = 10 mV / Div. AC COUPLED
Figure 12. Supply Voltage vs. Shutdown Input
Voltage Threshold
Vth(SHND), SHUTDOWN INPUT VOLTAGE THRESHOLD (V)
Figure 13. Wakeup Time From Shutdown
TIME = 500 ms / Div.
V
in
, SUPPLY VOLTAGE (V)
WAKEUP TIME FROM SHUTDOWN
0.0
0.5 2.52.01.51.0 3.0
−50 50 7525010
0
−25
0.50
1.25
0.75
0.25
1.50
1.75
Iout, OUTPUT CURRENT (mA)
−4.0
−3.0
−1.0
40 50 0 302010 40 5
0
2.0
Low State,
Device Shutdown
Vin = 2.0 V
Vin = 3.3 V
Vin = 5.0 V
RL = 10 kW
SHDN = GND
Figure 14 Test Setup
TA = 25°C
Vin = 1.5 V
Vin = 3.3 V
Vin = 5.0 V
Vin = 1.5 V
Vin = 2.0 V
Vin = 3.3 V
Figure 14 Test Setup
Vin = 3.3 V
Iout = 5.0 mA
TA = 25°C
TA = 25°C
High State,
Device Operating
Figure 14 Test Setup
TA = 25°C
Vin = 5.0 V
Vin = 5.0 V
RL = 1.0 kW
TA = 25°C
Vout = 1.0 V/Div.
SHDN = 5.0V/Div.
MAX1720
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5
6
4
2
3
1OSC
−Vout
C1
C2RL
+
+C3
Vin
+
Figure 14. Test Setup/Voltage Inverter
5
C1 = C2 = C3 = 10 mF
DETAILED OPERATING DESCRIPTION
The M AX1720 c harge p ump c onverter i nverts t he v oltage
applied to the Vin pin. Conversion consists of a two−phase
operation (Figure 15). D uring t he f irst p hase, switches S2 and
S4 are open and S1 and S3 are closed. During this time, C1
charges to t he v oltage o n Vin a nd l oad current is supplied f rom
C2. D uring t he s econd phase, S 2 and S4 are closed, and S1 and
S3 are open. This action connects C1 across C2, restoring
charge to C2.
Figure 15. Ideal Switched Capacitor Charge Pump
S3 S4
C2
C1
S1 S2
Vin
−Vout
From Osc
APPLICATIONS INFORMATION
Output Voltage Considerations
The MAX1720 performs volta ge conversion but does not
provide regulation. The output voltage will drop in a linear
manner with respect to load current. The value of this
equivalent output resist ance is approximately 26 W nominal
at 2 5°C w ith Vin = 5.0 V. Vout i s approxi mately 5.0 V a t l ight
loads, and drops according to the equation below:
VDROP +Iout Rout
Vout +*(Vin *VDROP)
Charge Pump Efficiency
The overall power conversion efficiency of the charge
pump is affected by four factors:
1. Losses from power consumed by the internal
oscillator, switch drive, etc. (which vary with input
voltage, temperature and oscillator frequency).
2. I2R losses due to the on−resistance of the MOSFET
switches on−board the charge pump.
3. Charge pump capacitor losses due to Equivalent
Series Resistance (ESR).
4. Losses that occur during charge transfer from the
commutation capacitor to the output capacitor when
a voltage difference between the two capacitors
exists.
Most of the conversion losses are due to factors 2, 3 and 4.
These losses are given by Equation 1.
PLOSS(2,3,4) +Iout2 Rout ^Iout2
ƪ1
(fOSC)C1)8RSWITCH )4ESRC1)ESRC2ƫ
(eq. 1)
The 1/(fOSC)(C1) term in Equation 1 is the effective output
resistance of an ideal switched capacitor circuit (Figures 16
and 17).
The losses due to charge transfer above are also shown in
Equation 2 . T he o utput v olta ge r i pple i s g i ven b y E quation 3 .
)0.5C2(VRIPPLE2*2VoutVRIPPLE)] fOSC
P
LOSS +[0.5C1(Vin2*Vout2)
(eq.
2)
VRIPPLE +Iout
(fOSC)(C2))2(Iout)(ESRC2)
(eq. 3)
RL
C2
C1
Vin Vout
f
Figure 16. Ideal Switched Capacitor Model
RL
C2
Vin Vout
REQUIV
REQUIV +1
f C1
Figure 17. Equivalent Output Resistance
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6
Capacitor Selection
In order to maintain the lowest output resistance and
output ripple voltage, it is recommended that low ESR
capacitors be used. Additionally, larger values of C1 will
lower the output resistance and larger values of C2 will
reduce output voltage ripple. (See Equation 3).
Table 1 shows various values of C1, C2 and C3 with the
corresponding output resistance values at 25°C. Table 2
shows the output voltage ripple for various values of C1, C2
and C3. The data in Tables 1 and 2 was measured not
calculated.
Table 1. Output Resistance vs. Capacitance
(C1 = C2 = C3), Vin = 4.75 V and Vout = −4.0 V
C1 = C2 = C3
(mF) Rout
(W)
0.7 129.1
1.4 69.5
3.3 37.0
7.3 26.5
10 25.9
24 24.1
50 24
Table 2. Output Voltage Ripple vs. Capacitance
(C1 = C2 = C3), Vin = 4.75 V and Vout = −4.0 V
C1 = C2 = C3
(mF) Output Voltage Ripple
(mV)
0.7 382
1.4 342
3.3 255
7.3 164
10 132
24 59
50 38
Input Supply Bypassing
The input voltage, Vin should be capacitively bypassed to
reduce AC impedance and minimize noise effects due to the
switching internals in the device. If the device is loaded from
Vout to GND, it is recommended that a large value capacitor
(at least equal to C1) be connected from Vin to GND. If the
device is loaded from Vin to Vout, a small (0.7 mF) capacitor
between the pins is sufficient.
Voltage Inverter
The most common application for a charge pump is the
voltage inverter (Figure 14). This application uses two or
three external capacitors. The C1 (pump capacitor) and C2
(output capacitor) are required. The input bypass capacitor,
C3, may be necessary depending on the application. The
output is equal to −Vin plus any voltage drops due to loading.
Refer to Tables 1 and 2 for capacitor selection. The test setup
used for the majority of the characterization is shown in
Figure 14.
Layout Considerations
As with any switching power supply circuit, good layout
practice is recommended. Mount components as close
together as possible to minimize stray inductance and
capacitance. A ls o, u se a l ar ge g round p lane to mini mize n oise
leakage into other circuitry.
Capacitor Resources
Selecting t he p roper t ype o f c apacitor c an reduce s witching
loss. L ow E SR c apacitors a re recommended. The M AX1720
was characterized using the capac itors listed i n Table 3. T his
list identifies low ESR capacitors for the voltage inverter
application.
Table 3. Capacitor Types
Manufacturer/Contact Part Types/Series
AVX
843−448−9411
www.avxcorp.com
TPS
Cornell Dubilier
508−996−8561
www.cornell−dubilier.com
ESRD
Sanyo/Os−con
619−661−6835
www.sanyovideo.com/oscon.htm
SN
SVP
Vishay
603−224−1961
www.vishay.com
593D
594
6
4
2
3
1OSC
Capacitors = 10 mF
+
+
Vin 5
+
−Vout
Figure 18. Voltage Inverter
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7
The MAX1720 p rimary f unct ion i s a v oltage i nverter. T he d evice w ill c onvert 5 .0 V into 5.0 V with l i ght l oads. Two c apaci tors
are required for t he inverter to f uncti on. A third capacitor, the input bypas s c apaci t or, may be required depending on the pow e r
source for the inverter. The performance for this device is illustrated below.
Figure 19. Inverter Load Regulation, Output Voltage vs. Output Current
0
−2.0
30
−5.0
2010
Vout, OUTPUT VOLTAGE (V)
−6.0
0
Iout, OUTPUT CURRENT (mA)
−4.0
−3.0
−1.0
40 50
TA = 25°C
Vin = 3.3 V
Vin = 5.0 V
Figure 20. Cascaded Devices for Increased Negative Output Voltage
+
6
4
2
3
1OSC
Capacitors = 10 mF
+
Vin
5
+
6
4
2
3
1OSC +
5
−Vout
+
Two or more devices can be cascaded for increased output voltage. Under light load conditions, the output voltage is
approximately equal to −Vin times the number of stages. The converter output resistance increases dramatically with each
additional stage. This i s d ue t o a r eduction o f i nput v oltage t o e ach s ucces s ive stage as the converter output is loaded. Note that
the ground connection for each successive stage must connect to the negative output of the previous stage. The performance
characteristics for a converter consisting of two cascaded devices are shown below.
Figure 21. Cascade Load Regulation, Output Voltage vs. Output Current
−2.0
−4.0
−10.0
0
Iout, OUTPUT CURRENT (mA)
Vout, OUTPUT VOLTAGE (V)
02040
−6.0
−8.0
10 30
A
B
TA = 25°C
A 5.0 140
B 3.0 174
Curve Vin (V) Rout (W)
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8
+
6
4
2
3
1OSC
Capacitors = 10 mF
+
+
Vin 5
+ +
−Vout
Figure 22. Negative Output Voltage Doubler
A single device can be used to construct a negative voltage doubler. The output voltage is approximately equal to −2V in minus
the forward voltage drop of each external diode. The performance characteristics for the above converter are shown below.
Note that curves A and C show the circuit performance with economical 1N4148 diodes, while curves B and D are with lower
loss MBRA120E Schottky diodes.
0
0
−2.0
2010
−4.0
−6.0
−10.0 30 40
Iout, OUTPUT CURRENT (mA)
Vout, OUTPUT VOLTAGE (V)
−8.0
F
igure 23. Doubler Load Regulation, Output Voltage vs. Output Current
A
B
TA = 25°C
C
D
A 3.0 1N4148
B 3.0 MBRA120E
Curve Vin (V) All Diodes
124
115
Rout (W)
C 5.0 1N4148
D 5.0 MBRA120E
96
94
+
6
4
2
3
1OSC
Capacitors = 10 mF
+
+
Vin 5
+ +
−Vout
++
Figure 24. Negative Output Voltage Tripler
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A single device can be used to construct a negative voltage tripler. The output voltage is approximately equal to −3Vin minus
the forward voltage drop of each external diode. The performance characteristics for the above converter are shown below.
Note that curves A and C show the circuit performance with economical 1N4148 diodes, while curves B and D are with lower
loss MBRA120E Schottky diodes.
−6.0
Iout, OUTPUT CURRENT
Vout, OUTPUT VOLTAGE
040302010 50
−10.0
−4.0
−12.0
−8.0
−16.0
−2.0
0
−14.0
F
igure 25. Tripler Load Regulation, Output Voltage vs. Output Current
A
B
TA = 25°C
C
D
A 3.0 1N4148
B 3.0 MBRA120E
Curve Vin (V) All Diodes
267
250
Rout (W)
C 5.0 1N4148
D 5.0 MBRA120E
205
195
+
+
6
4
2
3
1OSC
Capacitors = 10 mF
+
Vin 5Vout
Figure 26. Positive Output Voltage Doubler
A single device can be used to construct a positive voltage doubler. The output voltage is approximately equal to 2Vin minus
the forward voltage drop of each external diode. The performance characteristics for the above converter are shown below.
Note that curves A and C show the circuit performance with economical 1N4148 diodes, while curves B and D are with lower
loss MBRA120E Schottky diodes.
10.0
8.0
6.0
4.0
2.0
0
Iout, OUTPUT CURRENT (mA)
Vout, OUTPUT VOLTAGE (V)
02010 30 40
F
igure 27. Doubler Load Regulation, Output Voltage vs. Output Current
A
B
TA = 25°C
C
D
A 3.0 1N4148
B 3.0 MBRA120E
Curve Vin (V) All Diodes
32
26
Rout (W)
C 5.0 1N4148
D 5.0 MBRA120E
26
21
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10
+
+
6
4
2
3
1OSC
Capacitors = 10 mF
+
Vin 5Vout
+
+
Figure 28. Positive Output Voltage Tripler
A single device can be used to construct a positive voltage tripler. The output voltage is approximately equal to 3Vin minus
the forward voltage drop of each external diode. The performance characteristics for the above converter are shown below.
Note that curves A and C show the circuit performance with economical 1N4148 diodes, while curves B and D are with lower
loss MBRA120E Schottky diodes.
6.0
2.0
4.0
0
8.0
10.0
12.0
14.0
Iout, OUTPUT CURRENT (mA)
V
out
, OUTPUT VOLTAGE (V)
0302010 40
F
igure 29. Tripler Load Regulation, Output Voltage vs. Output Current
A
B
TA = 25°C
C
D
A 3.0 1N4148
B 3.0 MBRA120E
Curve Vin (V) All Diodes
111
97
Rout (W)
C 5.0 1N4148
D 5.0 MBRA120E
85
75
+
6
4
2
3
1OSC
+
Vin 5
−Vout
+
Figure 30. Load Regulated Negative Output Voltage
Capacitors = 10 mF
100 k
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11
A zener diode can be used with the shutdown input to provide closed loop regulation performance. This significantly reduces
the converters output resistance and dramatically enhances the load regulation. For closed loop operation, the desired
regulated output voltage must be lower in magnitude than −Vin. The output will regulate at a level of −VZ + Vth(SHDN). Note that
the shutdown input voltage threshold is typically 0.5 Vin and therefore, the regulated output voltage will change proportional
to the converters input. This characteristic will not present a problem when used in applications with constant input voltage.
In this case the zener breakdown was measured at 25 mA. The performance characteristics for the above converter are shown
below. Note that the dashed curve sections represent the converters open loop performance.
0
−2.0
302010
Vout, OUTPUT VOLTAGE (V)
−5.0
−1.0
Iout, OUTPUT CURRENT (mA)
−4.0
−3.0
40 6050
Figure 31. Load Regulation, Output Voltage vs.
Output Current
A
B
TA = 25°C
A 3.3 V 4.5
B 5.0 V 6.5
Curve Vin (V) Vz (V)
−2.8
−3.8
Vout (V)
Capacitors = 10 mF
+
6
4
2
3
1OSC
+
Vin 5
−Vout
+
R1
R2
10 k
Figure 32. Line and Load Regulated Negative Output Voltage
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An adjustable shunt regulator can be used with the shutdown input to give excellent closed loop regulation performance. The
shunt regulator acts as a comparator with a precise input offset voltage which significantly reduces the converter s output
resistance and dramatically enhances the line and load regulation. For closed loop operation, the desired regulated output
voltage must be lower in magnitude than −Vin. The output will regulate at a level of −Vref (R2/R1 + 1). The adjustable shunt
regulator can be from either the TLV431 or TL431 families. The comparator offset or reference voltage is 1.25 V or 2.5 V
respectively. The performance characteristics for the converter are shown below. Note that the dashed curve sections represent
the converter s open loop performance.
−2.0
−3.0
−1.0
−4.0
−5.0
Iout, OUTPUT CURRENT (mA)
Vout, OUTPUT VOLTAGE (V)
030 7010 20 40 50 60
Figure 33. Load Regulation, Output Voltage vs.
Output Current
A
B
TA = 25°C
A 3.0 5.0 k
B 5.0 20 k
Curve Vin (V) R2 (W)
−1.8
−3.6
Vout (V)
10 k
10 k
R1 (W)
−2.0
−3.0
−1.0
−4.0
1.0 3.02.0 4.0 5.0 6
.0
0
Vin, INPUT VOLTAGE (V)
Vout, OUTPUT VOLTAGE (V)
Figure 34. Line Regulation, Output Voltage vs.
Input Current
Iout = 25 mA
R1 = 10 k
R2 = 20 k
TA = 25°C
+
6
4
2
3
1OSC
Capacitors = 10 mF
Vin 5
6
4
2
3
1OSC
+
5
−Vout
+
+
Figure 35. Paralleling Devices for Increased Negative Output Current
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An i ncrease i n c onverter o utput c urrent c apability with a r eduction i n o utput r esistance c an b e o btained b y p aralleling two or more
devices. The output current c apability is a pproximately e qual t o the number of d evices paralleled. A s i ngle s hared output capac itor
is sufficient for proper operation but each device does require it’s own pump capacitor. Note that t he output ripple frequency will
be complex s ince the oscillators are not synchronized. The performance characteristics for a converter consisting o f two paralleled
devices is shown below.
0
0
−1.0
−2.0
403020
−3.0
−4.0
−5.0 10 50 80 100
Iout, OUTPUT CURRENT (mA)
Vout, OUTPUT VOLTAGE (V)
60 70 90
Figure 36. Parallel Load Regulation, Output
Voltage vs. Output Current
A
B
TA = 25°C
A 5.0
B 3.0
Curve Vin (V)
14.5
17
Rout (W)
+
6
4
2
3
1OSC
+
Vin 5
−Vout
Q1
C3
−Vout = Vin −VBE(Q1) VBE(Q2) −2 VF
+C2
Q2C1
C1 = C2 = 470 mF
C3 = 220 mF
Q1 = PZT751
Q2 = PZT651
Figure 37. External Switch for Increased Negative Output Current
The output current capability of the MAX1720 can be extended beyond 600 mA with the addition of two external switch
transis tors a nd tw o Sc hott ky diodes . The out put volt age i s approxi mate ly equal t o Vin minus the sum of the base emitter drops of
both transistors and the forward voltage of both diodes. The performance characteristic s for the converter are shown below. Note
that the output resistance is reduced to 0.9 W.
−2.8
Iout, OUTPUT CURRENT (mA)
Vout, OUTPUT VOLTAGE (V)
0 0.4 0.50.30.20.1 0.6
−3.2
−2.6
−3.0
−2.4
−2.2
Figure 38. Current Boosted Load Regulation, Output Voltage vs. Output Current
Vin = 5.0 V
Rout = 0.9 W
TA = 25°C
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Figure 39. Line and Load Regulated Negative Output Voltage
with High Current Capability
+
6
4
2
3
1OSC
+
Vin 5
−Vout
Q1
C3
+C2
Q2
C1
C1 = C2 = 470 mF
C3 = 220 mF
Q1 = PZT751
Q2 = PZT651
R1
R2
10 k
This converter is a combination of Figures 37 and 32. It provides a line and load regulated output of −2.36 V at up to 450 mA
with an input voltage of 5.0 V. The output will regulate at a level of −Vref (R2/R1 + 1). The performance characteristics are shown
below. Note, the dashed line is the open loop and the solid line is the closed loop performance.
−2.6
Iout, OUTPUT CURRENT (A)
Vout, OUTPUT VOLTAGE (V)
0 0.4 0.50.30.20.1 0.6
−3.2
−2.4
−2.8
−2.2
Figure 40. Current Boosted Load Regulation,
Output Voltage vs. Output Current
Vin = 5.0 V
Rout = 0.9 W
R1 = 10 kW
R2 = 9.0 kW
TA = 25°C
−3.0
−1.4
Vout, OUTPUT VOLTAGE (V)
3.0 5.0 5.54.54.03.5 6
.0
−2.4
−1.2
−1.6
−1.0
−1.8
Vin, INPUT VOLTAGE (V)
−2.0
−2.2
Figure 41. Current Boosted Line Regulation,
Output Voltage vs. Input Voltage
Iout = 100 mA
R1 = 10 k
R2 = 9 kW
TA = 25°C
Figure 42. Positive Output Voltage Doubler with High Current Capability
+
6
4
2
3
1OSC
+
Vin 5
Vout
Q1
C3
+C2
Q2C1
Capacitors = 220 mF
Q1 = PZT751
Q2 = PZT651
50
50
MAX1720
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The MAX1720 can b e configured to produce a pos itive o utput voltage doubler w ith c urrent capability in excess of 500 mA.
This is accomplished with the addition of two external switch transistors and two Schottky diodes. The output voltage is
approximately equal t o 2 Vin minus the sum of the b ase e mitter drops of b oth transistors and the forward voltage of both diodes.
The performance characteristics for the converter is shown below. Note that the output resistance is reduced to 1.9 W.
8.0
Iout, OUTPUT CURRENT (A)
Vout, OUTPUT VOLTAGE (V)
0 0.4 0.50.30.20.1 0.6
6.8
8.4
7.6
8.8
Figure 43. Positive Doubler with Current Boosted Load Regulation, Output Voltage vs. Output Current
Vin = 5.0 V
Rout = 1.9 W
TA = 25°C
7.2
Figure 44. Line and Load Regulated Positive Output Voltage Doubler with High Current Capability
+
6
4
2
3
1OSC
+
Vin 5
Vout
Q1
C3
+C2
Q2
C1
Capacitors = 220 mF
Q1 = PZT751
Q2 = PZT651
R2
R1
10 k 50
50
This converter i s a c ombinat ion of F i gures 42 a nd t he s hunt re gulator t o c los e t he loop. In t hi s c as e the anode o f t he r egul ator
is connected to ground. This convert provides a line and load regulated output of 7.6 V at up to 300 mA with an input volta ge
of 5.0 V. The output will regulate at a level of Vref (R2/R1 + 1). The open loop configuration is the dashed line and the closed
loop is the solid line. The performance characteristics are shown below.
8.0
Iout, OUTPUT CURRENT (A)
Vout, OUTPUT VOLTAGE (V)
0 0.4 0.50.30.20.1 0.6
6.8
8.4
7.6
8.8
Figure 45. Current Boosted Close Loop Load
Regulation, Output Voltage vs. Output Current
Vin = 5.0 V
Rout = 1.9 W Open Loop
Rout = 0.5 W Closed Loop
R1 = 10 k
R2 = 51.3 kW
TA = 25°C
7.2
6.0
Vin, INPUT VOLTGE (V)
Vout, OUTPUT VOLTAGE (V)
1.0 4.0 5.03.02.0 6
.0
1.0
7.0
5.0
8.0
Figure 46. Current Boosted Close Loop Line
Regulation, Output Voltage vs. Input Voltage
Iout = 100 mA
R1 = 10 k
R2 = 51.3 kW
TA = 25°C
4.0
3.0
2.0
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6
4
2
3
1OSC
Capacitors = 10 mF
+
Vin = −5.0 V
5
+
+
Figure 47. Negative Input Voltage Splitter
C
C
+C
Vout = −2.5 V
C
A single device can be used to split a negative input voltage. The output voltage is approximately equal to −Vin/2. The
performance characteristics are shown below. Note that the converter has an output resistance of 10 W.
0
−1.5
−1.7
−1.9
403020
−2.1
−2.3
−2.5 10 50 80
Iout, OUTPUT CURRENT (mA)
Vout, OUTPUT VOLTAGE (V)
60 70
Figure 48. Negative Voltage Splitter Load Regulation, Output Voltage vs. Output Current
TA = 25°C
Rout = 10 W
+
6
4
2
3
1OSC
+
Vin 5
−Vout
+
Figure 49. Combination of a Closed Loop Negative Inverter with a Positive Output Voltage Doubler
Capacitors = 10 mF
10 k
+
+
R1
R2
+Vout
MAX1720
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All of the previously shown converter circuits have only single outputs. Applications requiring multiple outputs can be
constructed by incorporating combinations of the former circuits. The converter shown above combines Figures 26 and 32 to
form a regulated negative output inverter with a non−regulated positive output doubler. The magnitude of −Vout is controlled
by the resistor values and follows the relationship −Vref (R2/R1 + 1). Since the positive output is not within the feedback loop,
its output voltage will increase as the negative output load increases. This cross regulation characteristic is shown in the upper
portion of Figure 50. The dashed line is the open loop and the solid line is the closed loop configuration for the load regulation.
The load regulation for the positive doubler with a constant load on the −Vout is shown in Figure 51.
−4.0
−5.0
−3.0
8.0
9.0
Iout, NEGATIVE INVERTER OUTPUT CURRENT (mA)
Vout, OUTPUT VOLTAGE (V)
02010 30
Figure 50. Load Regulation, Output
Voltage vs. Output Current
8.0
7.0
9.0
10.0
Iout, POSITIVE DOUBLER OUTPUT CURRENT (mA)
Vout, OUTPUT VOLTAGE (V)
0302010 5
0
Figure 51. Load Regulation, Output
Voltage vs. Output Current
R1 = 10 kW
R2 = 20 kW
TA = 25°C
40
Negative Inverter Iout = 15 mA
Negative Inverter
Positive Doubler
Iout = 15 mA
Rout = 45 W − Open Loop
Rout = 2 W − Closed Loop
R1 = 10 k, R2 = 20 k
TA = 25°C
Figure 52. Inverter Circuit Board Layout, Top View Copper Side
Vin
GND
IC1 C1
Inverter Size = 0.5 in x 0.2 in
Area = 0.10 in2, 64.5 mm2
−Vout
GND
C3+
C2
+
SHDN
+
0.5
TAPING FORM
PIN 1
USER DIRECTION OF FEED
Component Taping Orientation for TSOP−6 Devices
Standard Reel Component Orientation
(Mark Right Side Up)
DEVICE
MARKING
TSOP−6
Package Tape Width (W) Pitch (P) Part Per Full Reel Diameter
8 mm 4 mm 3000 7 inches
Tape & Reel Specifications Table
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PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE P
23
456
D
1
eb
E
A1
A
0.05 (0.002)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
c
L
0.95
0.037
1.9
0.075
0.95
0.037
ǒmm
inchesǓ
SCALE 10:1
1.0
0.039
2.4
0.094
0.7
0.028
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
HE
DIM
AMIN NOM MAX MIN
MILLIMETERS
0.90 1.00 1.10 0.035
INCHES
A1 0.01 0.06 0.10 0.001
b0.25 0.38 0.50 0.010
c0.10 0.18 0.26 0.004
D2.90 3.00 3.10 0.114
E1.30 1.50 1.70 0.051
e0.85 0.95 1.05 0.034
L0.20 0.40 0.60 0.008
0.039 0.043
0.002 0.004
0.014 0.020
0.007 0.010
0.118 0.122
0.059 0.067
0.037 0.041
0.016 0.024
NOM MAX
2.50 2.75 3.00 0.099 0.108 0.118
HE
0°10°0°10°
q
q
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MAX1720/D
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