CD74HC147NSR96 - Texas Instruments

Data sheet acquired from Harris Semiconductor

SCHS149B

Features

• Buffered Inputs and Outputs

• Typical Propagation Delay: 13ns at VCC = 5V,

CL = 15pF, TA = 25oC

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Description

The ’HC147 and CD74HCT147 are high speed silicon-gate

CMOS devices and are pin-compatible with low power

Schottky TTL (LSTTL).

The ’HC147 and CD74HCT147 9-input priority encoders

accept data from nine active LOW inputs (l1to l9) and

provide binary representation on the four active LOW inputs

(Y0 to Y3). A priority is assigned to each input so that when

two or more inputs are simultaneously active, the input with

the highest priority is represented on the output, with input

line l9 having the highest priority.

These devices provide the 10-line to 4-line priority encoding

function by use of the implied decimal “zero”. The “zero” is

encoded when all nine data inputs are HIGH, forcing all four

outputs HIGH.

Pinout CD54HC147

(CERDIP)

CD74HC147

(PDIP, SOIC, SOP)

CD74HCT147

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC147F3A -55 to 125 16 Ld CERDIP

CD74HC147E -55 to 125 16 Ld PDIP

CD74HC147M -55 to 125 16 Ld SOIC

CD74HC147NSR -55 to 125 16 Ld SOP

CD74HCT147E -55 to 125 16 Ld PDIP

CD74HCT147M -55 to 125 16 Ld SOIC

NOTES:

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

2. Waferor diefor thispart numberis availablewhich meetsall elec-

trical specifications. Please contact your local TI sales office or

customer service for ordering information.

GND

VCC

September 1997 - Revised March 2002

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC147,

CD74HCT147

High Speed CMOS Logic

10-to-4 Line Priority Encoder

[ /Title

(CD74

HC147

CD74

HCT14

/Sub-

ject

(High

Speed

CMOS

Logic

10-to-4

Line

Prior-

ity

Encode

/Autho

r ()

/Key-

words

(High

Speed

CMOS

Logic

10-to-4

Line

Prior-

ity

Encode

r, High

Speed

CMOS

Logic

10-to-4

Line

Prior-

ity

Functional Diagram

TRUTH TABLE

INPUTS OUTPUTS

I1 I2 I3 I4 I5 I6 I7 I8 I9 Y3 Y2 Y1 Y0

HHHHHHHHHHHHH

XXXXXXXXLLHHL

XXXXXXXLHLHHH

XXXXXXLHHHLLL

XXXXXLHHHHLLH

XXXXLHHHHHLHL

XXXLHHHHHHLHH

XXLHHHHHHHHLL

XLHHHHHHHHHLH

LHHHHHHHHHHHL

NOTE: H = High Logic Level, L = Low Logic Level, X = Don’t Care

I8 10

I9 GND = 8

VCC = 16

CD54/74HC147, CD74HCT147

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Package Thermal Impedance, θJA (see Note 3):

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

SOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

3. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

- - ---- - - -V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

- - ---- - - -V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC or

GND -6--±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 6 - - 8 - 80 - 160 µA

CD54/74HC147, CD74HCT147

HCT TYPES

High Level Input

Voltage VIH - - 4.5 to

5.5 2--2 - 2 - V

Low Level Input

Voltage VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output

Voltage

TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC and

GND 0 5.5 - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - - 8 - 80 - 160 µA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

∆ICC VCC

-2.1 - 4.5 to

5.5 - 100 360 - 450 - 490 µA

NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) speciﬁcation is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

I1, I2, I3, I6, I71.1

I4, I5, I8, I91.5

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical Table, e.g.,

360µA max at 25oC.

Switching Speciﬁcations Input tr, tf = 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay,

Input to Output (Figure 1) tPLH, tPHL CL= 50pF 2 - - 160 - 200 - 240 ns

4.5 - - 32 - 40 - 48 ns

5 - 13 - - - - - ns

6 - - 27 - 34 - 41 ns

Transition Times

(Figure 1) tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance CIN - - - - 10 - 10 - 10 pF

CD54/74HC147, CD74HCT147

Power Dissipation Capaci-

tance

(Notes 4, 5)

CPD -5-32-----pF

HCT TYPES

Propagation Delay,

Input to Output (Figure 2) tPLH, tPHL CL= 50pF 4.5 - - 35 - 44 - 53 ns

5 - 14 - - - - - ns

Transition Times (Figure 2) tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns

Input Capacitance CIN - - - - 10 - 10 - 10 pF

Power Dissipation Capaci-

tance

(Notes 4, 5)

CPD -5-42-----pF

NOTES:

4. CPD is used to determine the dynamic power consumption, per gate.

5. PD = VCC2 fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER SYMBOL TEST

CONDITIONS VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

FIGURE 6. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC FIGURE 7. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

CD54/74HC147, CD74HCT147

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