February 1994 - Linear Technology

FEBRUARY 1994 VOLUME IV NUMBER 1

C-Load

Op Amps

Tame Instabilities

by William Jett and George Feliz

impedance of the amplifier. This out-

put pole increases the phase lag

around the loop, reducing the phase

margin of the amplifier. If the phase

lag is large enough, the amplifier will

oscillate.

External networks can be used to

improve the amplifier’s stability with

a capacitive load (Figure 1). The net-

works cause the load impedance to

appear more resistive to the output.

The series resistor R

isolates the

capacitive load from the output,

whereas the RC network (snubber)

, added in parallel with the load,

swamps out the load capacitance with

the real impedance R

. These net-

works work best when the load

capacitance is well defined and con-

stant, so the values can be optimized.

Disadvantages include reduced out-

put swing and drive current, and

increased component count.

An Example

Existing op amps vary greatly in

regard to stability with capacitive

loads. Some older amplifiers are quite

stable with resistive loads but

continued on page 15

Introduction

Traditionally, operational amplifi-

ers have been tricky to use with

capacitive loads. Driving capacitive

loads can bring out the worst behav-

ior in most operational amplifiers.

How often has discussion around the

coffee pot centered on how to suc-

cessfully decouple the op amp’s output

from the load so that oscillations do

not run rampant?

Now the problem has become moot.

Advances in process technology and

innovative circuit design have made

it possible for Linear Technology Cor-

poration to develop a series of

C-Load

op amps that are tolerant of

capacitive loading, including the ulti-

mate: amplifiers that are stable with

any capacitive load. These amplifiers

span a range of bandwidths from

1MHz to 140MHz. The designer no

longer has to worry; the amplifiers

drive C

LOAD

without problems.

The Problem

The cause of the capacitive load

stability problems in most amplifiers

is the pole formed by the load capac-

itance and the open-loop output

IN THIS ISSUE…

COVER ARTICLE

C-LoadTM Op Amps

Tame Instabilities ........... 1

William Jett and George Feliz

Editor's Page ................... 2

Richard Markell

DESIGN FEATURES

New 500ksps ADC Solves

High-Speed Design

Problems ......................... 3

William C. Rempfer and Ringo Lee

Triple-Output 3.3V, 5V,

and 12V High-Efficiency

Notebook Power Supply ... 6

Randy G. Flatness

The LT1203: 150MHz Video

Multiplexer Features 25ns

Switching Time and Better

Than –90dB Crosstalk..... 8

John Wright and Frank Cox

LTC1065, Clock-Tunable,

DC-Accurate, Fifth-Order

Bessel Lowpass Filter .... 11

Nello Sevastopoulos

The World’s First Low-Cost

Micropower, 12-Bit ADCs

in SO-8 Packages........... 13

William C. Rempfer and Marco Pan

DESIGN IDEAS ......... 17–32

(complete listing on page 17)

DESIGN INFORMATION

Reconfigurable CMOS

EIA562/RS232 and RS485

Transceivers.................. 33

Dave Dwelley

New Device Cameos ....... 34

LTC in the News ............ 35

cload_4.eps

–

OUTPUT

RC NETWORK

(SNUBBER)

SERIES R

Figure 1. Conventional approaches to driving capacitive loads

C-Load

is a trademark of Linear Technology Corporation

LINEAR TECHNOLOGY

Linear Technology Magazine • February 1994

EDITOR'S PAGE

New Isolator Device, LTC1145/1146,

Wins Innovation of the Year Award

by Richard Markell

Out of the swirling mists will come

ideas. Some will be poor ideas. But

some will be novel and produce cre-

ative products.

The LTC1145 and LTC1146

emerged from the mind of Bob Dobkin

several years ago. The goal was isola-

tion similar to that provided by

opto-isolator circuits, without the

hybrid LED/photodiode type of isola-

tion barrier. Innovation came when

Dobkin saw, “in a flash,” that the

capacitors required to provide isola-

tion could be part of the lead frame.

This “leadframe as capacitor” con-

cept provides excellent isolation (UL

approved to 4000 Volts DC) and also

allows the product to be competi-

tively priced.

The LTC1145 and LTC1146 are

the first members of our isolator prod-

uct line. These products include an

on-chip digital filter to guarantee sig-

nal integrity, rather than speed.

Our lead article in this issue de-

scribes new operational amplifiers

that drive any load capacitance. De-

signers no longer experience the

nightmare of driving changing C

LOAD

when they use these new LTC op

amps. New analog-to-digital convert-

ers continue to come off the LTC

product line; the LTC1298 and

LTC1286 are new 12-bit converters

in SO8 packages that convert to

12.5ksps. We also introduce the

LTC1278, a 12-bit parallel ADC that

samples at 500ksps.

In this issue we introduce the

LT1203/LT1205 family of 150MHz,

two- and four-channel multiplexers.

Both feature an incredible isolation

of better than −90dB at 10MHz. The

LTC line of DC-accurate filters has

another member: the LTC1065 fifth-

order Bessel filter. The LTC1065

features less than 1 millivolt typical

DC offset with 13 bits or more of

dynamic range. Its cutoff frequency

can be programmed by either an in-

ternal or an external clock.

Also highlighted in these pages is

the LTC1142, a 5V and 3.3V synchro-

nous, step-down switching regulator

controller IC with two independent

regulator sections. The LTC1142 is

featured in a triple notebook power

supply with outputs of 3.3V, 5V,

and 12V.

Also in this issue we have informa-

tion on new products from LTC for

RS562 serial links. These

are reconfigurable RS232/RS562/

RS422/RS485 products that operate

in many modes.

As is becoming our habit, in this

issue we feature a good sampling of

Design Ideas, as well as the famous

underground LTC barometer circuit

from the last LTC seminar.

FAE Cameo: Georg Dumsky

LTC now has twenty-one Field Ap-

plication Engineers (FAEs) worldwide

to assist our customers in the design

and selection of circuits available from

LTC.

Georg Dumsky is one of Linear

Technology’s three German Field

Application Engineers. He was born

in Franken, Germany and studied

electronics in Munich. Georg has been

with LTC for nearly six years. During

most of this time, his territory has

Georg tells a story of how he spent

a long time convincing a customer

that he could use an LTC reference in

his system, eliminating trims while

maintaining stability. A new designer

who took over the project later told

Georg that they did not need the LTC

parts, because they “had something

in there that gives 5.000 volts with-

out adjustment.” Needless to say,

Georg and the new designer were talk-

ing about the same thing: the LT1029.

included Switzerland, Austria, and

all or part of Germany.

Georg and his wife and their daugh-

ter Barbara live in Neufahrn, a small

town north of Munich, near the LTC

office in Eching.

Georg’s hobbies include garden-

ing, but he says he “prefers to play

squash.” (Do you think the pun is

intended?) In the summer he is a

windsurfer and in the winter he skis

with his family and friends.

Innovation is the name of the game

in today’s fiercely competitive prod-

uct environment. EDN Magazine

recently awarded Bob Dobkin and

Bob Reay of Linear Technology Corp.

the Innovation of the Year award for

semiconductors.

How does one innovate? How can a

company cultivate an innovative en-

vironment? These are the keys to the

success of LTC and of other trail

blazing companies:

•Provide an environment where

smart thinking and innovative

ideas are rewarded.

•Give the potential innovator

room to bounce ideas around a

room full of critics.

Linear Technology Magazine • February 1994

DESIGN FEATURES

New 500ksps ADC Solves High-

Speed Design Problems

Welcome the Newest

ADC Family Member

The LTC1278 is a high-speed,

low-power, 12-bit sampling ADC.

It is complete and requires no ex-

ternal components. It runs at

500ksps and typically draws only

75mW from single 5V or ±5V sup-

plies. It offers a 5mW power-down mode

with instant wake up.

As shown in Table 1, the LTC1278 is

the fastest member of LTC’s high-speed

ADC family. The family also includes

300ksps/5V members and a 140ksps/

3V device. Like other family members,

the LTC1278 uses a capacitively-based

successive-approximation (SAR) algo-

rithm. However, this device takes the

SAR architecture to new levels of speed.

By using the SAR approach, it can pro-

vide very high performance at low power

and low cost.

The block diagram of Figure 1 shows

the components contained within the

chip: a fast SAR ADC with sample-and-

hold, an internal reference, and

internally synchronized conversion clock

and power-down circuitry. This archi-

tecture is very similar to that of the

previous family members. Process and

design improvements have allowed the

speed to be increased. A power-down

function has been added to provide

Introduction

The newest member in Linear Tech-

nology’s high-speed ADC family has

arrived. It is the LTC1278. This 500

kilo-samples-per-second (ksps), 12-

bit device solves the major problems

faced by designers of today’s high

speed systems: performance, power

dissipation, board space, complexity,

and cost. This device offers the fol-

lowing radical improvements to

designers of telecommunications,

digital signal processing, and

high-speed and multiplexed data-

acquisition systems:

•Single 5V or ±5V supply

operation

•Low power dissipation and power

shutdown

•Complete: requires no external

components, crystals or clocks

•Excellent AC and DC

performance

•Small 24-pin SO or 24-pin

narrow DIP package

These features of the LTC1278 can

simplify, improve, and lower the cost

of high-speed designs. This article

describes the LTC1278 and discusses

its benefits and how they can solve

the system designer's problems.

Device Sampling S/(N + D) Input Power Power

Type Frequency @Nyquist Range Supply Dissipation

LTC1272 250kHz 65dB 0V–5V 5V 75mW

LTC1273 300kHz 70dB 0V–5V 5V 75mW

LTC1275 300kHz 70dB ±2.5V ±5V 75mW

LTC1276 300kHz 70dB ±5V ±5V 75mW

LTC1278 500kHz 70dB 0V–5V 5V 75mW

or ±2.5V or ±5V 5mW*

LTC1282 140kHz 68dB 0V–2.5V 3V 12mW

or ±1.25V or ±3V

*5mW power shutdown with instant wake-up

Table 1. LTC’s high-speed ADC family includes 5V and 3V devices. The 500ksps LTC1278 is

the fastest member

1278_1.eps

12-BIT CAPACITIVE DAC COMP

2.42V

REF

SAMPLE

SUCCESSIVE APPROXIMATION

•

•

D11

BUSY

CONTROL LOGIC

CSCONVST RDSHDN

INTERNAL

CLOCK

ZEROING

SWITCH

Figure 1. The LTC1278 ADC is complete, with sample-and-hold, internal reference, internally

synchronized conversion clock, and power-down circuitry

by William C. Rempfer

and Ringo Lee

Linear Technology Magazine • February 1994

Figure 3. The complete 500ksps ADC requires only bypass capacitors and one power supply.

Surface-mount packaging means the complete solution occupies well under one-half square inch

of valuable real estate

DESIGN FEATURES

reduced power consumption during

inactive periods. A separate conver-

sion-start input and some new digital

interface modes allow more flexibility

and an easier interface to latches,

FIFOs, and DSPs.

Benefits

The LTC1278 offers benefits in

performance, power dissipation, con-

figuration simplicity, and board

space. It will operate on a single power

supply.

Outstanding DC and AC

Performance Beyond Nyquist

The DC performance of the new

ADC includes ±1LSB INL and DNL.

No missing codes performance is

guaranteed over temperature. Maxi-

mum full-scale drift of the internal

reference is 25ppm/°C.

On the AC front, the LTC1278 can

digitize input signals up to the Nyquist

rate (250kHz) with nearly perfect lin-

earity. Even more significant is its

ability to digitize beyond the Nyquist

frequency. This makes it useful in

“undersampling” applications such

as synchronous demodulation of high

frequency IF signals. Figure 2 shows

how the effective bits and signal-to-

noise plus distortion ratio of the

converter perform as input frequency

is increased.

Lowest Power Dissipation

and Shutdown

The 150mW maximum power dis-

sipation (75mW typical) is at least

1278_2.eps

INPUT FREQUENCY (Hz)

EFFECTIVE BITS

10k 100k 1M

02M

1VDD = 5V

fSAMPLE = 500kHz

NYQUIST

FREQUENCY

S/(N + D)(dB)

two times lower than any other ADC

in this speed range. It is even further

enhanced by a power shutdown fea-

ture (5mW typical) that can be invoked

with an external pin (SHDN). The

ADC wakes up “instantly” (300ns)

from shutdown, so power-down can

be invoked even during brief inactive

periods with no penalty or delay when

conversions must start again.

Fewer Power Supplies

The new ADC runs at full speed on

either a single 5V supply or ±5V sup-

plies. This makes it extremely

attractive in new high-speed designs,

which are abandoning the ±15V sup-

plies of the past. Many new designs

use 5V supplies for reduced power

dissipation and higher op amp per-

formance. Many new high speed op

amps are being developed on ad-

vanced, high-speed processes that can

stand only ±5V rails. In addition to its

±5V supplies, the LTC1278’s ±2.5V

input span nicely matches output

swings of this new generation of

op amps.

Simple Configuration:

No External Components

The LTC1278 is complete. No ex-

ternal components are required

except for the normal supply and

reference bypass capacitors used by

all high speed ADCs. Figure 3 shows

the extremely simple configuration

provided by this new device.

Unbeatable Board Space

The simple configuration of Figure

3 also allows a very small board lay-

out. All components are available in

surface-mount packages, including

the ADC. The actual board space,

including an input op amp and by-

pass capacitors is one-half

square inch.

Applications Abound

At least four major application ar-

eas can benefit from the LTC1278:

telecommunications, digital signal

processing, portable-computer data-

acquisition boards, and high-speed

or multiplexed data acquisition.

Telecom and DSP

In telecom applications such as

HDSL (High-bit-rate Digital Subscrib-

er Line interface), low ADC power

dissipation is a must because the

systems are usually powered by the

phone line itself. Excellent dynamic

performance is required of the ADC’s

sample-and-hold. Noise cancellation

and echo cancellation are examples

of DSP problems that also require

excellent dynamic performance. The

LTC1278 excels in these applications,

even beating the performance of many

14- and 16-bit converters. How can

1278_3.eps

1

2

3

4

5

6

7

8

9

10

11

24

23

22

21

20

19

18

17

16

15

14



REF



AGND

D11(MSB)

D10

D9

D8

D7

D6

D5

D4

DGND



BUSY

CS

RD

CONVST

SHDN



D0

D1

D2

LTC1278

0.1µF

10µF

2.42V

REF



OUTPUT

ANALOG INPUT

(0V TO 5V)

10µF0.1µF

12-BIT

PARALLEL

BUS

µP CONTROL

LINES

CONVERT INPUT

SHUTDOWN INPUT

Figure 2. The LTC1278 can accurately digitize

input signals up to the Nyquist frequency and

beyond, making it useful even in under-

sampling applications

Linear Technology Magazine • February 1994

D11

VDD

AIN µP

or 

DSP

BUSY

–5V

LTC1275

VSS

VEE ABC

–5V

ENABLE

CD4051

VDD

NO BUFFER REQUIRED

RESET

COUNTERQ1

8 INPUT

CHANNELS

±2.5V

RANGE

CD4520

1278_4.eps

DESIGN FEATURES

this be? How can a 12-bit converter

outperform higher resolution

devices? The answer is in the sample-

and-hold.

At low input frequencies (e.g., be-

low 10kHz), most 14- and 16-bit ADCs

will outperform 12-bit ADCs. This is

because the quantization noise

caused by the discrete ADC steps is

smaller due to the smaller step size.

However, as the input frequency is

increased, the sample-and-hold can

dominate and degrade the ADC per-

formance in two ways. First, the

aperture-time jitter in the sam-

ple-and-hold will translate into in-

put-referred voltage noise via the

dv/dt of the input signal. The higher

the dv/dt, the higher the jitter-

induced noise. This can degrade the

noise floor of the higher resolution

ADC to below the 12-bit level.

Second, the distortion of the sample-

and-hold will distort the input signal

and add unwanted harmonics to the

output spectrum of the ADC. This

will degrade the distortion (THD) and

signal-to-noise plus distortion (S/

(N+D)) of the ADC. These two effects

combine and can make a poorly de-

signed 14- or 16-bit converter worse

than a 12-bit device at high input

frequencies.

The LTC1278 is a winner in these

types of systems because of the per-

formance of its sample-and-hold.

Figure 2 shows how well the effective

bits and signal-to-noise plus distor-

tion ratio of the converter hold up as

the input frequency is increased. For

input signals up to the Nyquist rate

(250kHz), jitter and distortion remain

low enough so as not to degrade the

overall ADC performance. Beyond the

Nyquist frequency, the sample-and-

hold still performs better than many

14- and 16-bit devices. The LTC1278

can achieve 70dB of S/(N + D) when

synchronously demodulating a

455kHz IF signal.

PC Data Acquisition Cards

Another common application is PC

data acquisition cards. The high sam-

ple rate, the simple, complete

configuration, and the low cost of

these converters make them ideal

Figure 4. The high input impedance of the ADC family allows multiplexing without a buffer

amplifier. The 300ksps LTC1275 is shown here with the low cost CD4051 multiplexer

choices here. Another subtle feature,

the synchronized internal conversion

clock, is also useful in this application.

Other sampling ADCs require an

external clock to run the conversion,

in addition to the normal sample

signal. Aside from the extra hardware

and circuitry needed to generate the

clock, a synchronizing problem oc-

curs between the conversion clock

and the sample signal. If the two

signals are not synchronized, noise

from the conversion clock couples

into the ADC as the sample is taken,

generating errors. Hence, with these

converters, the two clocks must be

synchronized. In constant-sample-

rate systems, this is possible,

although bothersome; however, in PC

data-acquisition systems the sample

command often comes from the out-

side, and its exact timing cannot be

known. In this case, the system de-

signer must design conversion-clock

circuitry that senses when the

sample command occurs and auto-

matically synchronizes to it. This is

difficult to do with the fast and pre-

cise clocks required by these ADCs.

This is one of the big benefits of the

LTC1278 and its brothers in Table 1.

They have been designed with

internal conversion clocks that auto-

matically synchronize to the incoming

sample command. The devices are

factory trimmed with adequate preci-

sion to meet the 1.6µs conversion

time of the ADC. This feature makes

this new converter a clear winner for

PC data acquisition cards.

Multiplexed and

High-Speed Data Acquisition

Both single-channel and

multiplexed high-speed data acqui-

sition systems can benefit from the

LTC1278’s performance. The 1.6µs

conversion time and 300nsec acqui-

sition time allow a high 500ksps

throughput on a very low power and

cost budget. In addition, the high-

impedance inputs of the ADCs make

them very easy to multiplex. Figure 4

shows the 300ksps LTC1275 multi-

plexed with a low cost MUX and

counter. (The LTC1278 can be used

for higher speeds). The system scans

through the eight channels, convert-

ing at full speed. The high input

impedance of the ADC eliminates the

need for a buffer between the MUX

and the ADC. The combined price of

the MUX and counter is less than

$0.50, making an extremely low-cost

configuration.

Conclusion

The ADC’s new features can sim-

plify, improve and lower the cost of

high speed designs. This will make it

the converter of choice for designers

of telecom, DSP, and high-speed

and multiplexed data-acquisition

systems.

Linear Technology Magazine • February 1994

DESIGN FEATURES

Triple-Output 3.3V, 5V, and 12V High-

Efficiency Notebook Power Supply

by Randy G. Flatness

Introduction

The new LTC1142 is a dual, 5V and

3.3V synchronous, step-down switch-

ing-regulator controller, featuring

automatic Burst Mode

operation

for high efficiencies at low output

currents. Two independent regulator

sections, each driving a pair of com-

plementary MOSFETs, can be

separately shut down to less than

20µA per output. This feature is ab-

solutely necessary for maximizing

battery life in portable applications.

Additionally, the input voltage to each

regulator section can be individually

connected to different potentials (20V

maximum), allowing a wide range of

novel applications.

The operating current levels for

both regulator sections can be pro-

grammed, via external current-sense

resistors, to set current limits. A wide

input-voltage range for the LTC1142

allows operation from 4V to 16V. The

LTC1142HV extends this voltage

range to 20V, permitting operation

with up to 12-cell battery packs.

LTC1142 Circuit Operation

Both regulator blocks in the

LTC1142 and LTC1142HV use a

constant off-time current-mode

architecture with Burst Mode

op-

eration identical to that of the

LTC1148. This results in a power

Figure 2 are limited to 150mV/R

SENSE

or 3.0A and 3.75A respectively.

When the output current for either

regulator section drops below approx-

imately 15mV/R

SENSE

, that section

automatically enters Burst Mode

operation to reduce switching losses.

In this mode the LTC1142 holds both

MOSFETs off and “sleeps” at 160µA

supply current, while the output ca-

pacitor supports the load. When the

output capacitor falls 50mV below its

specified voltage (3.3V or 5V), the

LTC1142 briefly turns this section

back on, or “bursts,” to recharge the

output capacitor. The timing capaci-

tor pins, which go to 0V during the

sleep interval, can be monitored with

an oscilloscope to observe burst ac-

tion. As the load current is decreased,

the circuit will burst less and less

frequently.

The timing capacitors C

and C

set the off-time according to the for-

mula t

OFF

= 1.3 × 10

× C

. The

constant off-time architecture main-

tains a constant ripple current, while

the operating frequency varies only

with input voltage. The 3.3V section

has an off-time of approximately 5

microseconds, resulting in a operat-

ing frequency of 120kHz with an 8V

input. The 5V section has an off-time

of 2.6 microseconds and a switching

frequency of 140kHz with an 8V

input.

Auxiliary 12V Output

The operation of the 5V section is

identical to the 3.3V section, with

inductor L1 replaced by transformer

T1. The 12V output is derived from an

auxiliary winding on the 5V inductor

T1. The output from this additional

winding is rectified by diode D3 and

applied to the input of an LT1121

regulator. The output voltage is set by

resistors R3 and R4. A turns ratio of

supply that has very high efficiency

over a wide load-current range, fast

transient response, and very low drop-

out. The LTC1142 is ideal for

applications requiring 5V and 3.3V

outputs with high conversion effi-

ciencies over a wide load-current

range, in a small amount of board

space. The LTC1142 and LTC1142HV

are available in 28-pin SSOP

packages.

The application circuit in Figure 2

is configured to provide output volt-

ages of 3.3V, 5V, and 12V. The current

capability of both the 3.3V and 5V

outputs is 2A (2.5A peak). The

logic-controlled 12V output can pro-

vide 150mA (200mA peak), which is

ideal for flash-memory applications.

The operating efficiency, shown in

Figure 1, exceeds 90% for both the

3.3V and 5V sections.

The 3.3V section of the circuit in

Figure 2 comprises the main switch

Q4, synchronous switch Q5, induc-

tor L1, and current shunt R

SENSE3

The current sense resistor R

SENSE

monitors the inductor current and is

used to set the output current ac-

cording to the formula I

OUT

= 100mV/

SENSE

. Advantages of current con-

trol include excellent line and load

transient rejection, inherent short-

circuit protection, and controlled

startup currents. Peak inductor cur-

rents for L1 and T1 of the circuit in

The LTC1142 is ideal for

applications requiring 5V

and 3.3V outputs with high

conversion efficiencies over

a wide load current range,

in a small amount

of board space.

OUTPUT CURRENT (A)

1mA

EFFICIENCY (%)

100

10mA 2.5A

1142_1.eps

100mA 1A

LTC1142

= 8V

3.3V SECTION

LTC1142

= 8V

5V SECTION

Burst Mode

is a trademark of Linear Technology Corporation

Figure 1. LTC1142 efficiency

Linear Technology Magazine • February 1994

DESIGN FEATURES

Figure 2. Schematic diagram, LTC1142 high-efficiency power supply

offset at pin 14. When this external

offset cancels the built-in 25mV off-

set, Burst Mode

operation is

inhibited.

Auxiliary 12V Output Options

The circuit of Figure 2 can be

modified for operation in low-battery-

count (6-cell) applications. For

applications where heavy 12V-load

currents exist in conjunction with

low input voltages (<6.5V), the auxil-

iary winding should be derived from

the 3.3V instead of the 5V section. As

the input voltage falls, the 5V duty

cycle increases to the point when

there is simply not enough time to

transfer energy from the 5V primary

winding to the 12V secondary wind-

ing. For operation from the 3.3V

section, a transformer with a turns

ratio of 1:3.25 should be used in

place of the 33µH inductor L1. Like-

1:1.8 is used for T1 to ensure that the

input voltage to the LT1121 is high

enough to keep the regulator out of

dropout mode while maximizing

efficiency.

The LTC1142 synchronous switch

removes the normal limitation that

power must be drawn from the pri-

mary 5V inductor winding in order to

extract power from the auxiliary wind-

ing. With synchronous switching, the

auxiliary 12V output may be loaded

without regard to the 5V primary

output load, provided that the

loop remains in continuous-mode

operation.

When the 12V output is activated

by a TTL high (6V maximum) on the

12V enable line, the 5V section of the

LTC1142 is forced into continuous

mode. A resistor divider composed of

R1, R5, and switch Q1 forces an off-

set, subtracting from the internal

wise, a 30µH inductor would replace

T1 in the 5V section. With these com-

ponent changes, the duty cycle of the

3.3V section is more than adequate

for full 12V load currents. The mini-

mum input voltage in this case will be

determined only by the dropout volt-

age of the 5V output. The 100% duty

cycle inherent in the LTC1142 pro-

vides low dropout operation limited

only by the load current multiplied by

the sum of the resistances of the 5V

inductor, Q2 R

DS(ON)

and current sense

resistor R

SENSE5

Extending the

Maximum Input Voltage

The circuit in Figure 2 is designed

for a 14V maximum input voltage.

The operation of the circuit can be

extended to over 18V if a few key

components are changed. The parts

continued on page 31

1142_2.eps

1000pF

P-DRIVE 3

SENSE

–

N-DRIVE 3

P-GND3 S-GND3 C

TH3

TH5

S-GND5 P-GND5

N-DRIVE 5

SENSE

–

SENSE

P-DRIVE 5

IN3

SHDN3 SHDN5 V

IN5

LTC1142



200pF

4 3 25 27 13 11 17 18

510Ω

3300pF 3300pF



390pF

510Ω

1µF

24 16 10

OUT5

5V

220µF

10V

× 2

SENSE 5

0.04Ω

30µH

D2

MBRS140

Q3

Si9410DY

0V = NORMAL

>1.5V = SHUTDOWN 1µF

22µF

25V

× 2

IN

6.5V TO 14V

Q4

Si9430DY

Q5

Si9410DY

D1

MBRS140

100µF

10V

× 2

L1

33µH

SENSE 3

0.05Ω

OUT3

3.3V

22µF

25V

× 2

Q2

Si9430DY

0.01µF

COILTRONICS CTX33-4

DALE LPE-6562-A026

PRIMARY: SECONDARY = 1:1.8

KRL SL-1R050J

KRL SL-1R040J

 COILTRONICS (407) 241-7876

DALE (605) 665-9301

KRL/BANTRY (603) 668-3210

L1:

T1:

SENSE 3

:

SENSE 5

22Ω

R1

100Ω

12V ENABLE

0V = 12V OFF

>3V = 12V ON

(6V MAX)

1000pF

D3

MBRS140

R3

649k

R4

294k

20pF

22µF

25V

C9

22µF

35V

12V

150mA

LT1121

OUT

SHDN

ADJ

100Ω

Q1

VN2222LL

R5

18k

GND

Linear Technology Magazine • February 1994

1203_3.eps

OUTPUT

(50mV/DIV)

INPUT

(10mV/DIV)

LOGIC

(5V/DIV)

1203_2.eps

OUTPUT

(1V/DIV)

INPUT

(1V/DIV)

LOGIC

(5V/DIV)

DESIGN FEATURES

The LT1203: 150MHz Video Multiplexer

Features 25ns Switching Time and

Better Than –90dB Crosstalk

Introduction

The LT1203 is a wide-band, two-

input video multiplexer designed for

pixel switching and broadcast-quality

routing. The LT1205 is a dual version

that is configured as a four-input,

two-output multiplexer. These

multiplexers act as SPDT video

switches with 10ns transition times

at toggle rates up to 30MHz. Both

devices are fast enough for SVGA or

workstation applications, and are

SO packages, whereas the LT1205 is

packaged in the 16-lead narrow SO.

Advantages of

Complementary

Bipolar Processing

As picture processing and special

video effects become popular, there is

increased demand for higher perfor-

mance switching. For many years

video multiplexers have been fabri-

cated on a variety of CMOS processes

because of the ease of implementa-

tion and low cost; but along with low

cost comes low performance. CMOS

multiplexers are inherently bidirec-

tional because they are just a switch

between input and output. This re-

sults in poor output-to-input isolation

during switching unless a dead-time

is introduced. CMOS MUX’s have been

built with break-before-make switch-

ing to eliminate the talking between

channels, but these parts suffer from

output glitches large enough to in-

terfere with sync circuitry and input

glitches that couple to other equip-

ment. This is shown in Figure 1. The

input and output switching transients

of a CMOS multiplexer are shown in

Figure 2.

ideal for multimedia applications

where signals are routed on PCBs

prior to cable driving.

The 150MHz −3dB bandwidth en-

sures 0.1dB flatness to 30MHz for

HDTV systems, and the insertion loss

at 1MHz is only 0.03dB. Easy input

expansion, low switching transients,

and outstanding crosstalk make the

LT1203 and LT1205 ideal for quality

video distribution. The LT1203 is

available in 8-lead P DIP and 8-lead

As picture processing and

special video effects become

popular, there is increased

demand for higher

performance switching.

1203_1.eps

INPUT

GLITCHES

CMOS

MUX

75Ω

GLITCHES TO

ALL EQUIPMENT

ON CABLES

VIDEO

LOOP THRU

CONNECTIONS

–

OUTPUT

GLITCH

Figure 1. CMOS MUXs cause glitches on inputs and outputs

Figure 3 is a photo of the LT1203

switching transients. The input and

output transients of the LT1203 are

50 times lower than those of the CMOS

multiplexer. To prevent input tran-

sients from reaching other circuitry,

CMOS MUXs require buffers on each

input; this raises total system com-

plexity and cost. Outputs must also

be buffered because the high on-

resistance of the switch (R

DS(ON)

)

causes large insertion loss. CMOS

multiplexers suffer other problems

as well, including low operating

supply voltage, varying R

DS(ON)

with

supply or input voltage, part-to-part

variations, and poor channel separa-

tion, even when configured as tee

switches.

The LT1203 and LT1205, by con-

trast, are fabricated on LTC’s

by John Wright

and Frank Cox

Figure 2. CMOS MUX switching glitch (R

50Ω) Note: Output 1V/Div.

Figure 3. LT1203 switching glitch (R

= 50Ω)

Note: Output 50mV/Div.

Linear Technology Magazine • February 1994

DESIGN FEATURES

complementary bipolar process to

attain fast switching speed, high

bandwidth, and a wide supply-voltage

range compatible with traditional

video systems. The AC characteris-

tics change very little as the supply

voltage changes from +5V to +15V.

Channel-to-channel switching time

and chip-enable time are both 25ns;

hence, the delay is the same when

switching between channels or be-

tween ICs.

To demonstrate the switching

speed of the LT1203/LT1205, the RGB

MUX of Figure 4 is used to switch the

inputs of an RGB workstation with a

22ns pixel width. Figure 5a is a photo

showing the workstation output and

RGB MUX output. The slight rise-

time degradation at the RGB MUX

output is due to the bandwidth of the

LT1260 current-feedback amplifier

used to drive the 75 ohm cable. In

Figure 5b, the LT1203 switches at the

end of the first pixel to an input at

zero and removes the following

pixels.

1203_6.eps

IN2

OFF

FROM

INTERNAL

LOGIC

FROM

INTERNAL

LOGIC

–2V

IN1

V–

V+

V–OUT

I3I

Q8 Q7

Q10 Q9

Figure 4. Fast RGB MUX

Figure 6. LT1203 internal schematic

Circuit Topology

The LT1203 and LT1205 use a tee

switch configuration to attain excel-

lent crosstalk and disable isolation.

In addition, these multiplexers have

internal input buffers to prevent

switching transients from reaching

their inputs. Figure 6 is the internal

schematic of the LT1203. When the

logic selects channel 1, Q7 and Q9

each steer 3I to the complementary

Darlington configuration made up of

Q1– Q4. Current sources I1 and I2

remain biased at all times and sub-

tract 1/3 of the collector current from

Q7 and Q9. This results in Q1–Q4

having a bias current of 2I, or about

1mA each. Transistors Q5 and Q6 are

held off in this condition. DC offset

1203_4.eps

–

1.5k

75Ω

V+

OUT

LOGIC

V+

OUT

LOGIC

75Ω

RED OUT

1.5k

CHANNEL

SELECT

1.5k1.5k

75ΩGREEN OUT

1.5k

75ΩBLUE OUT

V+

OUT

BLUE 2

BLUE 1

V–LOGIC

LT1203

LT1260

LT1205

GREEN 2

GREEN 1

V–

RED 2

RED 1

V–

1203_5b.eps

“WORK-

STATION”

OUTPUT

RGB MUX

OUTPUT

1203_5a.eps

“WORK-

STATION”

OUTPUT

RGB MUX

OUTPUT

Figure 5a. Workstation and RGB MUX output

Figure 5b. RGB MUX output switched to

ground after one pixel

Linear Technology Magazine • February 1994

matching between channels is more

important to the video engineer than

the actual value of the input offset. A

DC mismatch as small as 3mV be-

tween channels is just visible on a

quality video monitor. The typical V

mismatch between channels on the

LT1203 is about 300µV. Components

R1, C1, R2, and C2 compensate the

complementary Darlington connec-

tion for capacitive loads. Maximum

peaking occurs with a 50pF capaci-

tive load, and is less than 3dB.

To change inputs, logic circuitry

switches the current steering differ-

ential pairs and 3I is routed to channel

2. This current steering technique is

very fast and accounts for the rapid

switching of the multiplexer. Tee

switches are formed when current

sources I1 and I2 turn on Q5 and Q6.

Q1–Q4 become reverse biased and

isolate the input and output, provid-

ing over 90dB off-channel rejection

at 10MHz. The complementary

Darlington is protected from emitter-

base breakdown by ESD clamps on

the inputs that activate at +3V.

Multiplexer Expansion

with Better Than −90dB

Crosstalk at 10MHz

The output impedance of the

LT1203 is typically 20Ω when en-

abled, and 10MΩ when disabled or

not selected. This high disabled out-

put impedance allows the output of

several LT1205s to be shorted togeth-

er to form large cross-point arrays.

Four LT1205s can be used to form a

16-to-1 cross-point switch. In this

application, 15 switches are turned

off and only one is active. An attenu-

ator is formed by the 15 de-selected

amplifiers and the output of the one

active device. Because of the wide

bandwidth in the LT1203, the output

impedance is constant at 20Ω up to

10MHz and then rises. Figure 7 is the

all hostile crosstalk response for this

16-to-1 MUX.

DESIGN FEATURES

enough for use in SVGA or worksta-

tion environments, while all hostile

crosstalk is low enough for the mul-

tiplexer to be used in very large

cross-point configurations. Expan-

sion is simple, with an enable feature

that raises the output impedance to

10MΩ. These high-performance mul-

tiplexers complement the large

number of video products offered

by LTC.

Performance

Table 1 summarizes the major per-

formance specifications of the

LT1203.

Conclusion

By taking full advantage of LTC’s

complementary bipolar process, the

LT1203/LT1205 can route high-speed

video signals without the switching

transients common in CMOS multi-

plexers. Switching speed is fast

Table 1. LT1203/LT1205 performance

Parameter Conditions Typical Value

Bandwidth RL = 1k 150MHz

0.1dB gain flatness RL = 1k 30MHz

Slew rate RL = 1k 300V/µs

Differential gain RL = 10k 0.01%

Differential phase RL = 10k 0.01 deg

Channel-select time RL = 1k, VIN = 1V 25ns

Enable time RL = 1k 25ns

Output voltage swing RL = 1k ±3V

Gain error RL = 1k, VIN = ±2V 2%

Input voltage range ±3V

Output offset voltage 10mV

Supply current 10mA

Supply current disabled 5.8mA

Figure 7. “All hostile” crosstalk of 16-to-1 MUX

1203_7.eps

ALL HOSTILE REJECTION (dB)

100

120

= ±15V

= 10Ω

110

FREQUENCY (MHz)

100

Linear Technology Magazine • February 1994

LTC1065, Clock-Tunable,

DC-Accurate, Fifth-Order Bessel

Lowpass Filter

Introduction

The LTC1065 is a monolithic fifth-

order lowpass filter with a frequency

response that closely approximates a

linear-phase Bessel filter. (Our hero

and the frequency response of the

LTC1065 are shown in Figures 1 and

2, respectively.) The LTC1065’s pro-

prietary architecture, like that of the

LTC1063, gives outstanding DC and

AC performance.

The LTC1065 features 1mV typical

output DC offset, 13 bits or more of

dynamic range, and excellent device-

to-device matching. The LTC1065’s

cutoff frequency is programmed by

either an internal or an external clock.

DC Performance

The output DC offset of the

LTC1065 filter depends on the offset

of a single internal op amp and on the

charge injection of the input switch-

es. The LTC1065 output DC offset is

trimmed to less than 1mV and is

optimized for ±5V supply operation.

The output offset of the LTC1065 is

low enough to allow it to compete

with discrete RC active filters using

low-offset op amps.

Calling the LTC1065 “DC accu-

rate” implies that it can pass DC

signals without significantly altering

by Nello Sevastopoulos

Figure 1. Our hero

DESIGN FEATURES

INPUT FREQUENCY (kHz)

GAIN (dB)

10 100

1065_2.eps

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90 200

AB C D

A. f

CLK

= 1MHz

B. f

CLK

= 2MHz

C. f

CLK

= 3MHz

D. f

CLK

= 4MHz

= 1.4V

RMS

= 25°C



their values. The LTC1065’s DC out-

put offset is measured (to 13 bits of

accuracy) with the input terminal

grounded.

The common-mode rejection of the

filter (in dB) is defined as the ratio of

the allowed input-voltage range to

the DC output offset change:

CMR = 20 log(V

IN(DC)

OS(OUT)

) (dB)

Table 1 shows the measured CMR

of several devices over the industrial

temperature range.

For example, an LTC1065 is placed

in front of an A/D converter with

±2.5V input range, V

= ±5V. The filter

output DC offset will not change by

more than 0.7mV over the entire ±2.5V

DC input range and over −40 to 85

degrees C. If a 12-bit A/D is used, the

filter will contribute slightly more than

1/2 LSB DC error.

DC accuracy is obtained if the out-

put DC offset does not change with

varying input DC signals. Power sup-

ply decoupling and PC board layout

are extremely critical in achieving a

constant output offset over a wide

range of cutoff frequencies. Note that

the DC performance of the LTC1065

will degrade somewhat when the filter

cutoff frequency exceeds 15kHz.

Figure 2. LTC1065 passband and gain vs.

frequency response

LTC1065

–5V

1065_3.eps

CLOCK

OUT

+5V

0.1µF

C = 220pF

(TYPICAL)

0.1µF

1

CLOCK

≅

Figure 3. Setting the LTC1065 internal clock

with an external RC

AC Performance

Clock Requirements

An external or internal clock pro-

grams the filter’s cutoff frequency

with a clock-to-cutoff-frequency ratio

of 100:1. If no external clock is avail-

able, the internal oscillator can be

used. The clock frequency of the in-

ternal oscillator is set by a simple RC

network, as shown in Figure 3. Note

that the ±3% typical tolerance of the

internal oscillator frequency does not

affect the flatness of the filter pass-

band. Figure 4 shows how to select

the exact values of the external RC

network: for a given power supply

choose the value of parameter K, set

C = 220pF + 4pF (parasitic capaci-

tance) and solve for R.

Example:

CUTOFF

= 2kHz, f

CLK

= 200kHz, V

= ±5V,

K = 1, C = 220pF, R = 22.6K (1% value)

For clock frequencies above 500kHz

and for more information on temper-

ature behavior, please consult the

LTC1065 final data sheet or the

LTC1063 data sheet.

Linear Technology Magazine • February 1994

1065_6.eps

2µs/DIV

500µV/DIV

DESIGN FEATURES

Device-to-Device Matching

The unique filter architecture of

the LTC1065 and LTC1063 allows

outstanding device-to-device phase

and amplitude matching. Channel-

to-channel matching is a common

requirement of multichannel systems.

Figure 5 shows the phase matching

of a group of fifty randomly selected

devices. The filters were set up for a

20kHz cutoff frequency and phase

versus frequency was measured. The

worst phase mismatch between two

devices was a total 0.7 degrees at

20kHz. Amplitude matching in the

devices is also excellent. Amplitude

mismatch ranges from an infinitesi-

mal 0.01dB to 25% of the filter

passband to a mere 0.05dB at 50% of

the filter passband.

Noise, Clock Feedthrough,

and Dynamic Range

The LTC1065 design approach is

based on optimum S/N ratio plus

THD rather than just low noise. The

total noise of the LTC1065, however,

INTERNAL CLOCK FREQUENCY (kHz)

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

1065_4.eps

100 300 500

VS = ±7.5V

VS = ±2.5V

fCLK = K/RC

C = 220pF

TA = 25°C

VS = ±5V

200 400

INPUT FREQUENCY (kHz)

PHASE MISMATCH (±DEG)

0.6

0.5

0.4

0.3

0.2

0.1

0481216

1065_5.eps

20 2426

10 14 18 22

= ± 7.5V

= 1V

RMS



= 20kHz

CLK

= 2MHz



Figure 6. LTC1065 output clock feedthrough

+ noise; filter input grounded

is quite low (80µV

RMS

) and is indepen-

dent of the value of the cutoff

frequency. The noise peak distribu-

tion is gaussian. Using a crest factor

of 5.5, the amplitude of a noise peak

is 220µV. Note that 1/2LSB of a 14-bit

system is 305µV (10V full scale). This

means that when noise is the critical

factor, the LTC1065 can be placed in

front of a 14-bit A/D. Signal-to-noise

ratio is 93dB (measured RMS) with a

10Vp-p output swing. The device’s

maximum S/N ratio is 95dB.

Internal layout techniques mini-

mize clock feedthrough. Clock

feedthrough is defined as the sum of

the RMS amplitudes of the clock and

its harmonics measured at the out-

put of the filter. In the past, clock

feedthrough was orders of magnitude

greater in amplitude and it could, at

best, cause system errors and, at

worst, render the filter unusable

in other than telephone-type

applications.

Figure 6 shows an oscilloscope

photo of the filter output when

Figure 5. LTC1065 typical phase matching

(device-to-device)

Figure 4. Selecting the external RC

components for a given clock frequency

continued on page 31

its input is grounded. The clock

feedthrough is embedded in the

peak-to-peak wideband noise. The

switching transients shown in Figure

6 have frequency contents well above

the clock frequency and, if they are

bothersome, they can be removed ei-

ther with a simple RC network, or by

bandwidth limiting the circuits fol-

lowing the filter.

Figure 7 shows the typical

configuration for dynamic range mea-

surement. An inverting buffer is

preferred over a unity-gain follower.

Large input common-mode signals

can severely degrade the distortion

performance of a noninverting buffer.

Figure 8 shows the THD-plus-noise

performance of the LTC1065 mea-

sured with a 1kHz pure sine wave

input. Curve A shows the dynamic

range for V

≤ 2V

RMS

(5.6Vp-p) being

limited by wideband noise. Harmonic

distortion dominates over noise

for input voltages ranging from

RMS

up to 4.2V

RMS

. The outstanding

–

50k

0.1µF

OUT

–15V

15V

1065_7.eps

0.1µF

0.1µFCLOCK IN

–

LT1022

20pF

50k

8

7

6

5



1

2

3

LTC1065

Figure 7. Typical connection for dynamic range measurement

Power 25°C

Supply ∆VIN –40°C25°C85°C(V

OS Nulled)

±2.5V ±1.8V 84dB 83dB 80dB 83dB

±5V ±4V 82dB 78dB 77dB 78dB

±7.5V ±6V 80dB 77dB 76dB 80dB

The above data is valid for clock frequencies up to 800kHz, 900kHz,

1MHz for VS = ±2.5V, ±5V, and ±7.5V respectively

Table 1. CMR data, f

CLK

= 100kHz

Linear Technology Magazine • February 1994

The World’s First Low-Cost Micropower,

12-Bit ADCs in SO-8 Packages

–

SAMPLE

BIAS AND 

SHUTDOWN CIRCUIT SERIAL PORT

REF

) CS/SHDN CLK(D

)

OUT

+IN (CH0)

–IN (CH1)

MICROPOWER

COMPARATOR

CAPACITIVE DAC

SAR

REF

GND PIN NAMES IN PARENTHESES

REFER TO THE LTC1298

1286_2.eps

Introduction

Small, low-cost, battery-powered

electronic instruments are appearing

everywhere. Examples include cellu-

lar phones, hand-held scanners,

pen-based computers, and a host of

others. Designers of these new sys-

tems face unbelievable challenges as

they struggle to provide ever increas-

ing performance and battery life in

smaller and lighter packages at ever

lower costs.

Many of these systems require

internal A/D conversion. Some ap-

plications, such as digitizing the

pen-screen input in pen-based com-

puters, have A/D converters at their

very cores. Others use ADCs more

peripherally, to monitor voltages or

other parameters inside the instru-

ment. Regardless of the use of the

ADC, it has been difficult to obtain

small ADCs at low enough power lev-

els and prices.

Fortunately, relief is here in the

form of the world’s first 12-bit, micro-

power ADCs in SO-8 packages: the

LTC1286 and LTC1298. These two

converters provide the micropower,

small-size, low-cost conversion

sought after by system designers. This

article discusses these two new con-

verters and some of their benefits.

Micropower and 12-Bits

in an SO-8 Package

The LTC1286 and LTC1298 add to

LTC’s SO-8 family of ADCs (see Table

1). They are 12-bit upgrades of the

popular 8-bit, micropower LTC1096/

LTC1098, which were also the first of

their kind in SO-8 packages. The block

diagram of Figure 1 shows the suc-

cessive approximation (SAR)

architecture. The pinouts of the

LTC1286 and LTC1298 are similar,

as shown in Figure 2. Both convert-

ers contain sample-and-holds and

have serial inputs and outputs. The

LTC1286 is a single-channel device

with differential inputs. The LTC1298

is a two-channel device. The channel

selection is made with the digital in-

put pin (D

). The LTC1286 draws

only 250 microamperes from a single

5V supply when running at full speed.

Both devices also feature automatic

shutdown, which reduces the cur-

rent to 1 nanoamp (typical) whenever

the ADC is not converting. This re-

duces power consumption as the

sample rate is reduced (see Figure 3).

The LTC1286 samples at a maximum

of 12.5ksps, whereas the LTC1298

samples at a maximum rate of

11.1ksps. At an average sample rate

DESIGN FEATURES

Table 1. The 12-bit LTC1286/LTC1298 add to LTC’s growing family of SO-8 packaged ADCs

Sample Supply Current Auto SO-8

Resolution Rate at fs max Shutdown Package

LTC1096 8 bits 33ksps 100µA* ✔✔

LTC1098 8 bits 33ksps 100µA* ✔✔

LTC1196 8 bits 1Msps 8µA✔

LTC1198 8 bits 750ksps 8µA* ✔✔

LTC1286 12 bits 12.5ksps 250µA* ✔✔

LTC1298 12 bits 11.1.ksps 340µA* ✔✔

*Auto shutdown reduces supply current at lower rates

Figure 1. Micropower design of the ADC’s comparator achieves a supply current of only 250

microamps for the LTC1286 (340 microamps for the LTC1298). Auto-shutdown between

conversions saves even more power as sample rate is reduced

by William C. Rempfer and Marco Pan

Linear Technology Magazine • February 1994

DESIGN FEATURES

1286_3.eps

1

2

3

8

7

6

REF

)



CLK

OUT



CH0

CH1

GND

SO-8 PACKAGE

CS/

SHDN

1

2

3

8

7

6

CC

CLK

OUT



CS/

SHDN

REF

+IN

–IN

GND

SO-8 PACKAGE

LTC1286 LTC1298

Figure 2. The extremely small size of these converters makes them popular in compact designs

Good DC Performance

The DC specs include excellent dif-

ferential non-linearity (DNL) of ±3/4

LSB, as required by pen-screen

and other monitoring applications.

No missing codes are guaranteed over

temperature.

Tiny Configuration

You can’t find a smaller 12-bit ADC

anywhere. The tiny SO-8 design is

even more attractive because it can

be used with a single, surface mount

bypass capacitor (1µF or less). The

serial interface saves board space and

package pins on the processor. A

sample configuration is shown in Fig-

ure 4. For ratiometric applications,

such as the pen screen, the reference

input can be tied to the sensor drive.

In these cases, an external voltage

reference is not required. For abso-

lute reference applications, the

devices can be used with an external

reference, which sets the span of the

of 1ksps, the supply current drops to

around 20 microamps. During long

idle periods when no conversions are

being requested, the supply current

is zero.

Benefits

Lowest Power Dissipation

and Auto-Shutdown

No 12-bit ADCs offer lower power

dissipation than the LTC1286/

LTC1298. The power dissipation au-

tomatically adjusts to the sample rate

as needed. When converting rapidly,

the converter stays on continuously,

but when the conversion rate drops,

the auto-shutdown reduces the power

to give the lowest possible overall

power dissipation (see Figure 3). Bat-

tery-powered designs will benefit

tremendously from this automatic

power optimization. It is totally trans-

parent to the user.

ADCs. The ADCs can be powered di-

rectly from the external reference if

desired, eliminating the need for a

separate voltage regulator.

Low Cost Solution

Reaching the required size and

power levels provides only two-thirds

of the solution. The final area is cost.

To keep system cost low, the ADC

contains everything required except

the reference (which is not necessary

in many target applications). The se-

rial port makes a very space-efficient

interface and significantly reduces

cost in isolated applications. The high-

impedance analog inputs can digitize

many sensors and signals directly

without needing buffer amplifiers.

Finally, the ADCs themselves are very

attractively priced, making them the

ideal choice for new designs.

Conclusion

The new LTC1286 and LTC1298

are the lowest power, smallest 12-bit

ADCs anywhere. They can make the

job of the designer of hand-held

instruments much easier by solving

the A/D conversion problem in the

space, power, and cost budget

required. They will find their way into

many applications in this exciting

new area.

Figure 4. The SO-8 package, serial I/O and no external components make

this the smallest possible ADC configuration

1286_4.eps

SAMPLE FREQUENCY (Hz)

0.1

SUPPLY CURRENT (µA)

1000

1k 100k

10k

100

= 25°C

= V

REF

= 5V

CLK

= 350kHz

1286_5.eps

5V1µF

ANALOG INPUT

0V TO 5V RANGE

MPU

(e.g., 8051)

P1.4

P1.3

P1.2

SERIAL DATA LINK

CC

CLK

OUT



CS/

SHDN

REF

+IN

–IN

GND

LTC1286

Figure 3. Automatic power shutdown between

conversions saves power as sample rate is

reduced

Linear Technology Magazine • February 1994

Cload_3.eps

= 0pF

= 250pF

= 1000pF

Cload_2.eps

= 0pF

= 50pF

= 1000pF

Cload_1.eps

= 0pF

= 50pF

Table 1. Unity-gain stable C-Load

amplifiers

stable with all capacitive loads

GBW IS/Amp

Singles Duals Quads (MHz) (mA)

LT1200 LT1201 LT1202 11 1

LT1220 —— —— 45 8

LT1224 LT1208 LT1209 45 7

LT1354 LT1355 LT1356 12 1

LT1357 LT1358 LT1359 25 2

LT1360 LT1361 LT1362 50 4

LT1363 LT1364 LT1365 70 6

Table 2. Unity-gain stable C-Load

amplifiers

stable with C

≤ 10,000pF

GBW IS/Amp

Singles Duals Quads (MHz) (mA)

LT1012 —— —— 0.6 0.4

—— LT1112 LT1114 0.65 0.32

LT1097 —— —— 0.7 0.35

—— LT1457 —— 2.0 1.6

Table 3. Current-feedback amplifiers with

adjustable bandwidth

GBW IS/Amp

Singles Duals Quads (MHz) (mA)

LT1217 —— —— 10 1

LT1223 —— —— 100 6

LT1227 —— —— 140 10

—— LT1229 LT1230 100 6

LT1252 —— —— 100 10

LT1206 —— —— 60 20

Figure 2. Medium-speed, non-LTC op amp

shown with C

= 0pF and C

= 50pF. V

=±15

V, A

= +1, R

=5K

Figure 3. LT1355 voltage-feedback amplifier

shown with C

= 0pF, C

= 50pF and

= 1000pF. V

=±5V, A

= +1, R

=5K

Figure 4. LT1206 current-feedback amplifier

shown with C

= 0pF, C

= 250pF and

= 1000pF. V

=±15V, A

= +1, R

= 3K,

= 5K, C

COMP

= 0.01µF

C-Load

amplifiers are great in

systems where the load is not fixed or

is ill defined. Examples include driv-

ing coaxial cables that may be

unterminated, driving twisted-pair

transmission lines, and buffering the

inputs of sampling A-to-D converters

that present time varying impedances.

Table 1 lists LTC’s unconditionally

stable voltage-feedback C-Load

amplifiers. Table 2 lists other voltage-

feedback C-Load

amplifiers that

are stable with loads up to 10,000pF.

All LTC op amps that allow the

bandwidth to be adjusted as a func-

tion of the capacitive load can be

stabilized. This approach is feasible

on current-feedback amplifiers where

the bandwidth is set by the external

feedback resistor. The proper value of

feedback resistor is selected for the

desired C

. Graphs of feedback resis-

tor versus C

for values up to 1000pF

appear on the data sheets of most of

the current-feedback amplifiers in the

LTC catalog. The LT1206 current-

feedback amplifier provides the

additional enhancement of an inter-

nal compensation network around

C-Load

, continued from page 1

DESIGN FEATURES

become unstable with even small

amounts of capacitance. Figure 2

shows an example of a competitor’s

medium-speed device, which is sen-

sitive to capacitive loading. With the

5kΩ load, the transient response

shows no sign of instability, but when

50pF is paralleled with the 5kΩ, the

response exhibits considerable ring-

ing. With a 75pF load, the device

oscillates.

By comparison, the transient re-

sponses of the 12MHz LT1355

voltage-feedback amplifier and the

60MHz LT1206 current-feedback

amplifier (Figures 3 and 4) show the

improvement in stability achieved by

C-Load

op amps. Each device main-

tains a stable transient response, even

with 1000pF of C

LOAD

The Solution—

Maintaining Stability

LTC’s new family of voltage-feed-

back amplifiers adjusts the frequency

response of the op amp to maintain

adequate phase margin regardless

of the capacitive load. Thus, the am-

plifiers cannot oscillate. These

the output stage, which can be con-

nected with an external bypass

capacitor. This current-feedback am-

plifier has a 250mA output-current

capability and can easily drive loads

up to 10,000pF. Table 3 lists LTC’s

current-feedback amplifiers that can

be stabilized with a simple modifica-

tion to the feedback resistor.

How Amplifiers

are Made Stable

with All Capacitive Loads

The basic approach used to ac-

commodate all capacitive loads is to

first create a high-frequency, high-

gain amplifier in a single gain stage,

using LTC’s advanced, complemen-

tary-bipolar process. To this amplifier,

we add a network that effectively

senses the amplifier’s C

and adjusts

the bandwidth, and therefore the

phase margin, accordingly.

The C-Load

block diagram in

Figure 5 illustrates this approach.

The input voltage is converted to

differential currents by a transcon-

ductance stage. The differential

currents are then mirrored off each

Linear Technology Magazine • February 1994

cload_5.eps

OUT

GBW = G



2 πC

CURRENT

MIRROR

–i

CURRENT

MIRROR

–i

–

i =V



 2

supply rail to the high impedance

node V

. The output impedance of the

mirrors is high, so the gain, G

× R

is typically greater than 10,000. The

capacitor C

and the output imped-

ance of the current mirrors R

form

the dominant pole for the amplifier.

The bandwidth is determined by the

input transconductance G

and the

compensation capacitor C

as noted

previously. A unity-gain buffer with

an output impedance R

isolates the

high-impedance node from the load.

Phase shifts through the mirrors and

the input and output stages add to

the 90 degrees from the dominant

pole, resulting in a phase margin of

40–60 degrees, depending on the par-

ticular amp.

The network R

exploits boot-

strapping to adjust the amplifier

compensation as a function of out-

put loading. Looking at the block

diagram, observe that the voltage

that appears across the network is

the voltage drop across the output

impedance I

. With no load on the

output, no voltage differential ap-

pears across the network, so no

current flows through the network

and the network does not affect the

frequency response of the amplifier.

The heavier the output loading, the

greater the current in the network

and the larger the effect of the net-

work. At the limit, with very heavy

loads and at frequencies near the

unity-gain cross, the network R

appears effectively in parallel with

the compensation capacitor C

. The

overall effect of R

on the response

is to reduce the bandwidth and to add

a pole-zero pair as C

is increased.

The bandwidth reduction improves

the phase margin by moving the uni-

ty-gain cross away from the output

pole, and the added pole-zero pair

compensates for some of the phase

lag. The added zero ensures that the

total phase lag can never exceed 180

degrees (corresponding to zero phase

margin), even for very large load ca-

pacitances, and that the amplifier

remains stable.

Figures 6 and 7 show a set of

transient responses illustrating the

effect of the compensation network.

The device, the LT1360 (a 50MHz

amplifier) is loaded with 100pF,

1000pF, 10,000pF (0.01µF), and

100,000pF (0.1µF). As the capacitive

loading is increased, the transient

responses show increasing overshoots

and ringing, but, as discussed previ-

ously, some phase margin is always

maintained, even for a 0.1µF load.

DESIGN FEATURES

Figure 5. Block diagram of C-Load

amplifier

Conclusions

Linear Technology has developed

families of medium- and high-speed

amplifiers that are much easier to

apply than their predecessors. Stable

operation with capacitive loads can

be achieved without critical external

components or loss of output drive.

These C-Load

operational amplifi-

ers are designed to be the next

generation of standard amplifiers

because they are stable under any

capacitive loading condition. They are

ideal for applications where the

load is not well defined, and can

simplify even low frequency designs

by ensuring stability under all condi-

tions of loading.

Cload_7.eps

= 10,000pF

1µs/DIV

= 100,000pF

5µs/DIV

Cload_6.eps

= 100pF

50ns/DIV

= 1000pF

200ns/DIV

Figure 6. LT1360 shown with C

= 100pF and

= 1000pF. V

= 100mVp-p, V

=±15V,

= +1, R

=5K

Figure 7. LT1360 shown with C

= 10,000pF

and C

= 100,000pF. V

= 100mVp-p,

=±15V, A

= +1, R

=5K

Linear Technology Magazine • February 1994

A Simple 300mA

NiCad Battery Charger

Figure 1. Four cell, 300mA, LTC1174 battery charger implemented with all surface-mount

components

1174_1.eps

OUT

C2

0.1µF

C1

22µF

25V



8V TO 12.5V

GND

LTC1174

BATT



4 CELLS

D1

MBRS130LT3

L1

50µH

R1

182k

R2

39.2k

C3

100µF

10V

D2

MBRS130LT3

AVX (TA) TPSD226M025R0200 ESR = 0.200 I

RMS

= 0.775A

AVX (TA) TPSD107M010R0100 ESR = 0.100 I

RMS

= 1.095A

MOTOROLA SCHOTTKY VBR = 30V

COILTRONICS CTX50-2P DCR = 0.212 IDC = 0.729A TYPE 52 CORE

COILTRONICS (407) 241-7876

C1 =

C3 =

D1, D2 =

L1 =

OUT

= 1.25V • (1 + R1/R2) = 7.0V

IPGM

SHDN

FAST CHARGE ≈ 0.6A – (V

BATT

+ 0.6V) • 4µs

2 • L (EQ.1)

OUT

LTC1174’s architecture allows the

LTC1174 to achieve 100% duty cycle,

forcing the internal P-channel MOS-

FET on 100% of the time.

When the batteries are being

charged, the resistor divider network

(R1 and R2) forces the LTC1174’s

feedback pin (V

) below 1.25V, caus-

ing the LTC1174 to operate at the

maximum output current. An inter-

nal 100mΩ resistor senses this

current and sets it at approximately

300mA, according to equation 1

(shown on the schematic). When the

batteries are disconnected, the error

amplifier drives the feedback pin to

1.25V, limiting the output voltage to

7.0V. Diode D2 prevents the batteries

from discharging through the divider

network when the charger is shut

down. In shut-down mode, less than

10 microamps of supply current is

drawn from the input supply.

Low-current battery charger cir-

cuits are required in hand-held

products such as palmtop, pen-based,

and fingertip computers. The charg-

ing circuitry for these applications

must use surface mount components

and consume minimal board space.

The circuit shown in Figure 1 meets

both of these requirements.

The circuit shown in Figure 1 uses

an LTC1174 to control the charging

circuit. A fully self-contained switch-

ing regulator IC, the LTC1174

contains both a power switch and the

control circuitry (constant off-time

controller, reference voltage, error

amplifier, and protection circuitry).

The internal power switch is a

P-channel MOSFET transistor in a

common source configuration; con-

sequently, when the switch turns on,

the LTC1174’s V

pin is connected

to the input voltage. This power switch

handles peak currents of 600mA. The

by Randy G. Flatness

DESIGN IDEAS

A Simple 300mA NiCad

Battery Charger ............ 17

Randy G. Flatness

A Perfectly

Temperature-Compensated

Battery Charger ............ 18

Mitchell Lee and Kevin Vasconcelos

All-Surface-Mount,

Programmable VPP

Generator for PCMCIA.... 19

Jon A. Dutra

Clock-Tunable Bandpass

Filter Operates to 160kHz

in Single-Supply Systems

...................................... 20

Philip Karantzalis

A Fully Isolated, Quad,

4A High-Side Switch...... 21

Milton Wilcox

A Single-Cell Barometer

...................................... 22

Jim Williams and Steve Pietkiewicz

LT1074/LT1076 Adjustable

0V to 5V Power Supply

...................................... 23

Kevin Vasconcelos

Clock-Synchronized

Switching Regulator has

Coherent Noise .............. 24

Jim Williams, Sean Gold,

and Steve Pietkiewicz

Isolated High-Side Driver

...................................... 25

James Herr

Using Super Op Amps to

Push Technological

Frontiers: an Ultra-Pure

Oscillator ...................... 26

Dale Eagar

High Efficiency 5V to

3.3V/1.25A Converter .... 29

Randy G. Flatness

RS485 Repeater Extends

System Capability ......... 30

Mitchell Lee

±5V Converter Uses

Off-the-Shelf,

Surface-Mount Coil ........ 32

Mitchell Lee and Kevin Vasconcelos

DESIGN IDEAS

Linear Technology Magazine • February 1994

A Perfectly

Temperature-Compensated

Battery Charger

tions, follows the true curvature of a

lead-acid cell. This prevents over- or

under-charging of the battery during

periods of extended low or high ambi-

ent temperatures. Temperature

compensation is conveniently pro-

vided by a Tempsistor



as shown in

Figure 1. The Tempsistor is used to

generate a temperature-dependent

current, which, in turn, adjusts the

charger’s output voltage to match

that of the battery. The match is within

100mV for a 12V battery over a range

of −10 degrees C to +60 degrees C. The

best place for the Tempsistor is di-

rectly under the battery, with the

battery resting on a pad of styrofoam.

Q1 provides a low voltage discon-

nect function, which reduces the

charger standby current to zero. When

the input voltage (from a rectified

transformer) is available, Q1 is bi-

ased ON and Q2 is turned ON. Q2

connects the various current paths

on the output of the regulator to

ground, activating the charging cir-

cuitry. If the input voltage is removed,

Q1 and Q2 turn off, and all current

paths from the battery to ground (ex-

cept for the load, of course) are

interrupted. This prevents unneces-

sary battery drain when the charging

source is not available.

A dual-rate charging characteris-

tic is achieved by means of a

current-sense resistor (R

) and a sense

comparator (LT1012). If the bat-

tery-charge current exceeds the float-

current threshold of 10mV/R

, the

comparator pulls the gate of Q3 low,

increasing the output voltage by

600mV. This sets the charging volt-

age to 14.4V at 25 degrees C. After the

battery reaches full charge, the

Battery charging circuits are usu-

ally greeted with a yawn, but this

lead-acid charger offers a combina-

tion of features that sets it apart from

all others. It incorporates a low-

dropout regulator, temperature com-

pensation, dual-rate charging, true

negative ground, and consumes zero

standby current.

The LT1083 family of linear regu-

lators exhibits dropout characteristics

of less than 1.5V, as compared to

2.5V in standard regulators. A small-

er regulator drop allows for lower

input voltages and less power dissi-

pation in the regulator. In this

application the regulator is used to

control charging voltage and limit

maximum charging current.

The temperature compensation

employed in this circuit, unlike

diode-based straight-line approxima-

continued on page 31

DESIGN IDEAS

by Mitchell Lee and

Kevin Vasconcelos

Tempsistor



is a registered trademark of Thermodisc Inc.

Figure 1. Battery charger follows temperature coefficient of a lead-acid cell very accurately

1086_1.eps

LT1086

ADJ

OUTIN

C1

10µF

TANT

D1

1N4001

R1

≥ 16.0V

C2

10µF

TANT

C3

47µF

ALUM

TO LOAD

R2

10k

R3

300Ω

R8

1k



200mΩ

R10

12V

GELCELL

TO V

R4

12Ω

R5

2210Ω

R6

250Ω



1K821J

= THERMODISC: 1K821J.

TEL: (616) 777-4100

–

R9

124k

R11

R7

110Ω

Q2

VN2222

Q3

VN2222

= 10mV/I

LT1012

Q1

2N3906

Linear Technology Magazine • February 1994

All-Surface-Mount, Programmable

0, 3.3V, 5V, and 12V VPP Generator

for PCMCIA

Generating the VPP voltage for a

PCMCIA port in laptop computers

has become more complicated with

PCMCIA standard 2.0. The VPP line

must come up to +5V initially until

the card “tupple” tells the card its

type and VPP voltage. For example, a

3.3V SRAM card must have VPP ad-

justed to 3.3V. If it is a flash memory

card, +12V must be supplied during

programming. During card insertion,

zero volts is desirable to uncondition-

ally prevent latch-up. Shutdown

supply current must be as low as

possible, and the supply must not

overshoot. This Design Idea presents

a circuit (Figure 1) that meets these

specifications. The same topology

could be useful for generating other

programmable supplies.

The circuit uses the LT1107 micro-

power DC-to-DC converter with a

single surface-mount transformer.

The LT1107 features an I

LIM

pin which

enables direct control of maximum

inductor current. This allows use of a

smaller transformer without risk of

saturation. The LT1111 could also be

used, with a reduction in output

power.

Circuit Operation

The circuit is basically a gated-

oscillator flyback topology. The SET

pin of the LT1107 is held at 1.25V

by negative feedback. Summing cur-

rents into the SET pin to zero for the

three different output states yields

three equations with three unknown

resistor values. The resistor

values are easily solved for using

Mathametica, MathCad, or classical

techniques.

Output noise is reduced by using

the auxiliary gain block (AGB) in the

feedback path. This added gain effec-

tively reduces the hysteresis of the

comparator and tends to randomize

output noise. With a low ESR capac-

itor for C1, output noise is below

30mV over the output load range.

Output power increases with

BATTERY

, from about 1.4W out with

5V in to about 2W out with 8V or

more. Efficiency is 62% to 76% over a

broad output power range. No mini-

mum load is required.

Component Selection

Substantial current flows through

and C

OUT

. Most tantalum capac-

itors are not rated for current flow

and can result in field failures. Using

a rated tantalum or rated electrolytic

will result in longer system life.

Shutdown

The circuit is shut down by using

two sections of the CD4066 in paral-

lel as a high-side switch. Alternatively,

simply disabling the logic supply to

the V

and I

LIM

nodes of the LT1107

will shut it down. This drops quies-

cent current from the V

BATTERY

input

below 2µA. When the device is shut

down, V

OUT

drops to zero volts.

DESIGN IDEAS

Figure 1. Schematic diagram for VPP generator

by Jon A. Dutra

PCMCIA_1.eps

LT1107

SW2 GND

LIM



5V ±

10%

C1

1µF

16V



SET

SW1

30Ω

1/4 CD4066

100k



10µF

16V



T1*

CTX33-4

1N5819

OUT

56µF

35V



0V, 3.3V, 5V, 12V

0mA TO 60mA

165k

100k

1/4 CD40661/4 CD4066

121k

29.4k

1N5819 OR

MBRS140

*COILTRONICS (407) 241-7876

Linear Technology Magazine • February 1994

DESIGN IDEAS

When the only available power sup-

ply in a system is 5V or 12V and a

precision bandpass filter is needed at

cutoff frequencies greater than 20kHz,

the LTC1264 switched-capacitor ac-

tive-filter building block can be

configured to realize an eighth-order

bandpass filter accurate to ±1% or

better over temperature (−40 degrees

C to 85 degrees C). Figure 1 is a

schematic diagram of an eighth-

order bandpass filter tunable with a

TTL clock signal to any center fre-

quency up to 70kHz with a 5V supply

or to 100kHz with a 12V supply. The

clock-frequency-to-center-frequency

ratio is 20:1. The gain response for a

50kHz bandpass filter is shown in

Figure 2 and the input dynamic range

with a 5V supply is shown in Figure 3.

The passband frequency range (the

frequency range where the filter’s at-

tenuation is 3dB or less) is equal to

Clock-Tunable Bandpass Filter

Operates to 160kHz

in Single-Supply Systems

the center frequency divided by ten.

The stopband attenuation reaches

60dB at twice the center frequency

and at one-half the center frequency.

The typical gain variation at the cen-

ter frequency is ±0.5dB at 25 degrees

C and ±1.5dB over temperature. (Note

that an additional ±0.4dB should be

added to account for the gain varia-

tion due to the 1% resistors). If the

operating temperature range is 25

degrees C (±20 degrees C) and the

power supply voltage can be con-

trolled to ±2%, the center frequency

can be extended to 90kHz for a 5V

supply or 160kHz for a 12V supply.

Note that the gain error for center

frequencies greater than 70kHz with

a 5V supply and greater than 100kHz

with a 12V supply increases from

1dB to 7dB. Therefore, the value of

resistor R1 for each LTC1264 section

should be increased to reduce the

error to ±1dB (see the table in

Figure 1).

If the power supply for this filter is

a switching regulator, the regulator’s

output noise can appear at the filter’s

output if the center frequency of the

filter is tuned to the noise frequency

of the regulator. This is due to the

filter’s low power-supply rejection

near its center frequency. The

LTC1264 is not a low-power device.

The typical quiescent current is 11mA

with a 5V supply or 18mA with a

12V supply.

1264_2.eps

FREQUENCY (kHz)

10

–80

GAIN (dB)

–30

–40

–50

–60

–70

–10

–20

100 200

= 5V

CLK

= 1MHz

Figure 2. LTC1264 single 5V supply, 50kHz

bandpass response

1264_3.eps

INPUT (V

RMS

)

0.01

THD + NOISE (dB)

–40

–50

–60

–70

–80 0.1 1

= 5V

CLK

= 1MHz

Figure 3. Dynamic range vs. input signal.

LTC1264 single 5V supply, 50kHz bandpass

filter

1264_1.eps

R2b, 10k

R1b, 39.2k

R3b, 39.2k

R2c, 10k

R1c, 39.2k

R3c, 39.2k

LTC1264

R3d, 10k

R2d, 39.2k

R1d, 39.2k

R1a, 39.2k

R3a, 10k

R2a, 39.2k

10k

15k

0.1µF



(5V OR 12V)

1µF

OUT

INV B

HP B

BP B

LP B

SB

GND

V+

SA

LP A

BP A

HP A

INV A

INV C

HP C

BP C

LP C

SC

V–

FCLK

SD

LP D

BP D

HP D

INV D

50k

12V

(USE ONLY FOR

A 12V SUPPLY)

22.1k

CLK



(TTL)

0.1µF

CENTER

5V

12V

12V

80kHz

90kHz

120kHz

140kHz

160kHz

R1

(EACH SECTION)

42.2k

47.5k

40.2k

42.2k

47.5k

Figure 1. Single-supply bandpass filter

by Philip Karantzalis

Linear Technology Magazine • February 1994

DESIGN IDEAS

A Fully Isolated, Quad,

4A High-Side Switch

High-side switching in hostile en-

vironments often requires isolation

to protect the controlling logic from

transients on the “dirty” power

ground. The circuit shown in Figure

1 drives and protects four low R

DS(ON)

power MOSFET switches over a wide

operating supply range. The LT1161

drivers are protected from transients

of up to 60V on the supply pins and

75V on the gate pins. Fault indication

is provided by an inexpensive

logic gate.

Each of the four LT1161 switch

channels has a completely self-con-

tained charge pump, which drives

the gate of the N-channel MOSFET

switch 12V above the supply rail when

the corresponding input pin is taken

high. The specified MOSFET device

types have a maximum R

DS(ON)

28mΩ, resulting in a total switch drop

(including sense resistor) of only 0.15V

at 4A output current.

The LT1161 independently protects

and restarts each MOSFET. It senses

drain current via the voltage drop

across a current shunt R

. When the

current in one switch exceeds ap-

proximately 6A (62mV/0.01Ω), the

switch is turned off without affecting

the other switches. The switch re-

mains off for 50ms (set by external

timing capacitor C

), after which the

LT1161 automatically attempts to re-

start it. If the fault is still present, this

cycle repeats until the fault is re-

moved, thus protecting the MOSFET.

Current shunts are readily available

in both through-hole and surface-

mount case styles. AN53 has

additional information on shunts.

The highest MOSFET dissipation

occurs with a “soft short” (one in

which the current is above the nor-

mal operating level, but still below the

current-limit threshold). This can

cause dissipation in Figure 1’s circuit

to rise, in the worst case, to 2W,

requiring modest heatsinking. When

an output is directly shorted to

ground, the average dissipation is

very low because the MOSFET con-

ducts only during brief restart

attempts.

Fault indication is provided by a

low-cost exclusive-NOR gate. In nor-

mal operation, a low on the LT1161

input forces a low on the output, and

a high forces a high. If an input is

high and the corresponding output is

low (i.e., short circuited), the output

of the exclusive-NOR gate activates

the isolated fault output. Similarly,

by adding resistor R

, the low-in-

put/high-output state can be used to

diagnose an open-load condition. Ad-

justing the value of R

sets the out-

put current at which the load is

considered to be open. For example,

in Figure 1, with V

SUPPLY

= 24V, a fault

would be indicated if the load could

not sink 10mA.

Figure 1’s circuit is ideal for driv-

ing resistive or inductive loads, such

as solenoids. However, the circuit can

be tailored for capacitive or high in-

rush loads as well. Consult the LT1161

data sheet for information on pro-

gramming current limit, delay time,

and automatic-restart period to han-

dle other loads. The LT1161 is

available in both DIP and surface-

mount packaging.

by Milton Wilcox

Figure 1. Protected quad high-side switch has isolated inputs and fault output

1161_1.eps



0.33µF EA.

N-CHANNEL

MOSFETS:

10µF

50V

S

0.01Ω EA.

IRFZ44

OR

MTP50N06E

OR

RFP50N05

IN1

4.7k

IN2

IN3

IN4

DS1

DS2

DS3

DS4

GND GND

100k



2.2kΩ EA.

V+V+

24V

LT1161

4.7k

INPUTS

OUTPUTS

4.7k

NEC PS2501-4

MM74HC266A

4N28

FAULT

OUTPUT