Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com (email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
- © Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and
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Kind regards,
Team Nexperia
PHP191NQ06LT
N-channel TrenchMOS logic level FET
Rev. 02 — 14 January 2010 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industria l applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Suitable for logic level gate drive
sources
1.3 Applications
DC-to-DC convertors
General industrial applications
Motors, lamps and soleno ids
Uninterruptible power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage Tj25 °C; Tj175 °C - - 55 V
IDdrain current Tmb =2C; V
GS =10V;
see Figure 1 and 3--75A
Ptot total power
dissipation Tmb = 25 °C; see Figure 2 - - 300 W
Dynamic characteristics
QGD gate-drain charge VGS =5V; I
D=25A;
VDS =44V; T
j=2C;
see Figure 11
- 37.6 - nC
Static characteristics
RDSon drain-source
on-state resistance VGS =10V; I
D=25A;
Tj= 25 °C; see Figure 10
and 9
-3.13.7m
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Product data sheet Rev. 02 — 14 January 2010 2 of 13
NXP Semiconductors PHP191NQ06LT
N-channel TrenchMOS logic level FET
2. Pinning information
3. Ordering information
4. Limiting values
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1G gate
SOT78 (T O - 22 0 A B )
2D drain
3S source
mb D mounting base; connected to
drain
12
mb
3
S
D
G
m
bb076
Table 3. Orderi ng informatio n
Type number Package
Name Description Version
PHP191NQ06L T T O-220AB plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead
TO-220AB SOT78
Table 4. Limiting values
In accordance with the Absolute Maxi mum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage Tj25 °C; Tj175 °C - 55 V
VDGR drain-gate voltage Tj25 °C; Tj175 °C; RGS =20k-55V
VGS gate-source voltage -15 15 V
IDdrain current VGS =10V; T
mb = 100 °C; see Figure 1 -75A
VGS =10V; T
mb =2C; see Figure 1 and 3-75A
IDM peak drain current tp10 µs; pulsed; Tmb =2C; see Figure 3 -240A
Ptot total power dissipation Tmb =2C; see Figure 2 -300W
Tstg storage temperature -55 175 °C
Tjjunction temperature -55 175 °C
Source-drain diode
ISsource current Tmb =2C - 75 A
ISM peak source current tp10 µs; pulsed; Tmb =2C - 240 A
Avalanche rugg edness
EDS(AL)S non-repetitive
drain-source avalanche
energy
VGS =10V; T
j(init) =2C; I
D=75A; V
sup 55 V;
unclamped; RGS =50; tp0.21 ms -560mJ
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Product data sheet Rev. 02 — 14 January 2010 3 of 13
NXP Semiconductors PHP191NQ06LT
N-channel TrenchMOS logic level FET
Fig 1. Normalized continuous drain current as a
function of mounting base temperature Fig 2. Normalized total power dissipation as a
function of mounting base temperature
Fig 3. Safe operating area; continuous and peak drain curren ts as a function of drain-source voltage
03aq99
0
40
80
120
0 50 100 150 200
Ider
(%)
Tmb (°C) Tmb (°C)
0 20015050 100
03aa16
40
80
120
Pder
(%)
0
03ar01
VDS (V)
1 102
10
102
10
103
ID
(A)
1
DC
100 ms
10 ms
1 ms
tp = 10 μs
100 μs
Limit RDSon = VDS /ID
PHP191NQ06LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 January 2010 4 of 13
NXP Semiconductors PHP191NQ06LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-mb) thermal resistance from junction
to mounting base see Figure 4 --0.5K/W
Rth(j-a) thermal resistance from junction
to ambie nt vertical in still air - 60 - K/W
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
0.2
03ar00
tp (s)
1041101
103102
101
1
Zth(j-mb)
(K/W)
102
δ = 0.5
0.1
0.05
0.02 single pulse
tp
tp
T
P
t
T
δ =
PHP191NQ06LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 January 2010 5 of 13
NXP Semiconductors PHP191NQ06LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage ID=25A; V
GS =0V; T
j=-5C 50 - - V
ID=25A; V
GS =0V; T
j=2C 55 - - V
VGS(th) gate-source threshold
voltage ID=1mA; V
DS = VGS; Tj=-5C;
see Figure 7 and 8--2.2V
ID=1mA; V
DS = VGS; Tj= 175 °C;
see Figure 7 and 80.5 - - V
ID=1mA; V
DS = VGS; Tj=2C;
see Figure 7 and 811.52V
IDSS drain leakage current VDS =55V; V
GS =0V; T
j=25°C --1µA
VDS =55V; V
GS =0V; T
j= 175 °C - - 500 µA
IGSS gate leakage current VGS =15V; V
DS =0V; T
j= 25 °C - 2 100 nA
VGS =-15V; V
DS =0V; T
j= 25 °C - 2 100 nA
RDSon drain-source on-state
resistance VGS =4.5V; I
D=25A; T
j=2C;
see Figure 9 --4.4m
VGS =5V; I
D=25A; T
j=2C;
see Figure 10 and 9-3.54.2m
VGS =10V; I
D=25A; T
j= 175 °C;
see Figure 10 and 9--7.4m
VGS =10V; I
D=25A; T
j=2C;
see Figure 10 and 9-3.13.7m
Dynamic character i stics
QG(tot) total gate charge ID=25A; V
DS =44V; V
GS =5V;
Tj=2C; see Figure 11 - 95.6 - nC
QGS gate-source charge - 17.2 - nC
QGD gate-drain charge - 37.6 - nC
Ciss input capacitance VDS =25V; V
GS = 0 V; f = 1 MHz;
Tj=2C; see Figure 12 - 7665 - pF
Coss output capacitance - 1045 - pF
Crss reverse transfer
capacitance - 465 - pF
td(on) turn-on delay time VDS =30V; R
L=1.2; VGS =5V;
RG(ext) =10; Tj=2C -63-ns
trrise time - 232 - ns
td(off) turn-off delay time - 273 - ns
tffall time - 178 - ns
Source-drain diode
VSD source-drain voltage IS=25A; V
GS =0V; T
j=2C;
see Figure 13 - 0.79 1.2 V
trr reverse recovery time IS=20A; dI
S/dt = -100 A/µs; VGS =0V;
VDS =25V; T
j=2C -78-ns
Qrrecovered charge - 171 - nC
PHP191NQ06LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 January 2010 6 of 13
NXP Semiconductors PHP191NQ06LT
N-channel TrenchMOS logic level FET
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values Fig 6. Transfer characteristics: drain current as a
function of gate-source vo ltage; typical values
Fig 7. Gate-source threshold voltage as a function of
junction temperature Fig 8. Sub-threshold drain current as a function of
gate-source voltage
03ar02
0
80
160
240
0 0.5 1 1.5 2
VDS (V)
ID
(A)
Tj = 25 °C
VGS = 2.4 V
10 V
3.2 V
2.8 V
5 V
3.6 V4 V
03ar04
0
20
40
60
80
0123
VGS (V)
ID
(A)
VDS > ID x RDSon
Tj = 175 °C 25 °C
03aa33
0
0.5
1
1.5
2
2.5
-60 0 60 120 180
Tj (°C)
VGS(th)
(V)
max
typ
min
03aa36
10-6
10-5
10-4
10-3
10-2
10-1
0123
VGS (V)
ID
(A)
maxtypmin
PHP191NQ06LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 January 2010 7 of 13
NXP Semiconductors PHP191NQ06LT
N-channel TrenchMOS logic level FET
Fig 9. Normalized drain-source on-state resistance
factor as a function of junction temperature Fig 10. Drain-source on-state resistance as a function
of drain current; typical values
Fig 11. Gate-source voltage as a function of gate
charge; typical values Fig 12. Sub-threshold drain current as a function of
gate-source voltage
03ne89
0
0.5
1
1.5
2
-60 0 60 120 180
Tj (°C)
a
03ar03
0
2
4
6
8
10
0 80 160 240
ID (A)
RDSon
(mΩ)
VGS = 3.2 VTj = 25 °C
10 V
5 V
3.6 V
4 V
03ar07
0
2
4
6
8
10
0 50 100 150 200
QG
(nC)
VGS
(V)
ID = 25 A
Tj = 25 °C
VDD = 44 V14 V
03ar06
102
103
104
105
101 1 10 102
VDS (V)
C
(pF)
Ciss
Coss
Crss
PHP191NQ06LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 January 2010 8 of 13
NXP Semiconductors PHP191NQ06LT
N-channel TrenchMOS logic level FET
Fig 13. Sourc e current as a function of source-dr ain vo ltage; typical values
03ar05
0
20
40
60
80
0 0.3 0.6 0.9 1.2
VSD (V)
IS
(A)
Tj = 25 °C175 °C
VGS = 0 V
PHP191NQ06LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 January 2010 9 of 13
NXP Semiconductors PHP191NQ06LT
N-channel TrenchMOS logic level FET
7. Package outline
Fig 14. Package outline SOT78 (TO-220AB)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT78 SC-46
3-lead TO-220AB
SOT7
8
08-04-23
08-06-13
Notes
1. Lead shoulder designs may vary.
2. Dimension includes excess dambar.
UNIT A
mm 4.7
4.1
1.40
1.25
0.9
0.6
0.7
0.4
16.0
15.2
6.6
5.9
10.3
9.7
15.0
12.8
3.30
2.79
3.8
3.5
A1
DIMENSIONS (mm are the original dimensions)
P
lastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
0 5 10 mm
scale
b b1(2)
1.6
1.0
c D
1.3
1.0
b2(2) D1E e
2.54
L L1(1) L2(1)
max.
3.0
p q
3.0
2.7
Q
2.6
2.2
D
D1
q
p
L
123
L1(1)
b1(2)
(3×)
b2(2)
(2×)
ee
b(3×)
AE
A1
c
Q
L2(1)
mounting
base
PHP191NQ06LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 January 2010 10 of 13
NXP Semiconductors PHP191NQ06LT
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PHP191NQ06LT_2 20100114 Product data sheet - PHP_PHB191NQ06LT-01
Modifications: The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate .
Type number PHP191NQ06LT separated from data sheet PHP_PHB191NQ06LT-01.
PHP_PHB191NQ06LT-01
(9397 750 13168) 20040505 Product data sheet - -
PHP191NQ06LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 January 2010 11 of 13
NXP Semiconductors PHP191NQ06LT
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest pro duct
status information is available on the Internet at URL http://www.nxp.com.
9.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warrant ies as to t he accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specifica t io n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
9.3 Disclaimers
Limited warranty and liability — Information in this document is be lieved to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability t owards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for useNXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applicati ons where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application /use or t he application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Appl ica tion plann ed. Customer has to do all necessary
testing for the Application in order to avoid a def ault of the Applicat ion and the
product. NXP Semiconductors does not accept any liability in this respect.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property right s.
Document status [1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
PHP191NQ06LT_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 14 January 2010 12 of 13
NXP Semiconductors PHP191NQ06LT
N-channel TrenchMOS logic level FET
Export control — This document as well as the item(s) descri bed herein may
be subject to export control regulat i ons. Export might require a prior
authorization from national authorities.
Non-automotive qualified products — Unless the data sheet of an NXP
Semiconductors product expressly states that the product is automotive
qualified, the product is not suitable for automotive use. It is neither qualified
nor tested in accordan ce with a uto moti ve t estin g or ap plicat ion requiremen ts.
NXP Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in auto motive equipment or applications. In
the event that cust omer uses the product for design-in and use in automot ive
applications to automotive specifica tions and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive application s beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use of
the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
9.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respective ow ners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PHP191NQ06LT
N-channel TrenchMOS logic level FET
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 January 2010
Document identifier: PHP191NQ06LT_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 General description . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .11
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11
9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
10 Contact information. . . . . . . . . . . . . . . . . . . . . .12