TL0134 160-Output LCD Segment/Common Driver IC JUNE. 2000. VER 1.0 TOMATO LSI Inc. TL0134 Version 0.0 160-Output LCD Segment/Common Driver IC TL0134 Specification revision history Content 1. New documentation TOMATO LSI Inc. 2 PRELIMINARY Ver 0.0 Date June. 2000 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 CONTENTS 1. INTRODUCTION ----------------------------------------------------------------------------------------------------------- 4 2. FEATURES --------------------------------------------------------------------------------------------------------------- 4 3. BLOCK DIAGRAM ----------------------------------------------------------------------------------------------------- 5 4. PIN DESCRIPTION ---------------------------------------------------------------------------------------------------4-1. Pin Description 4-2. Pin Connections 6 5. FUNCTIONAL DESCRIPTION ----------------------------------------------------------------------------------8 5-1.Pin Functions ---------------------------------------------------------------------------------------8 a. Pin Functions(Segment mode) b. Pin Functions(Common mode) 5-2. Functional Operations of each block -------------------------------------------------------------------------------11 a. Functional operations of each block 5-3. Functional Operations---------------------------------------------------------------------------------------------------12 a.LCD drive output voltage level b. Relationship between the display data and LCD drive output pins c. Connection Examples of Plural Segment Drivers d. Timing chart of 4-device cascade connection of Segment Drivers e. Connection examples for plural common drivers 5-4. Precautions---------------------------------------------------------------------------------------------------------18 6. SPECIFICATIONS -------------------------------------------------------------------------------------------------------- 19 6-1. Absolute maximum ratings --------------------------------------------------------------------------------------- 19 6-2. Recommended Operating Conditions------------------------------------------------------------------------------ 19 6-3. Electrical Characteristics-------------------------------------------------------------------------------------------------20 a. DC Characteristics(Segment mode/Common mode) b. AC Characteristics(Segment mode) 6-4. Timing Chart of Segment Mode ---------------------------------------------------------------------------------------23 6-5. Timing Chart of Common Mode ------------------------------------------------------------------------------25 6-6. System Configuration Example ----------------------------------------------------------------------------------------26 TOMATO LSI Inc. 3 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 1. INTRODUCTION The TL0134 is a 160-output segment/common driver IC suitable for driving medium scale dot matrix LCD panels. Through the use of SST(Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The TL0134 is good both as a segment driver and a common driver, and it can create a low power consuming, high-resolution LCD. 2. FEATURES -Number of LCD drive outputs : 160 -Supply voltage for LCD drive : +10.0 to +35.0V -Supply voltage for the logic system : +2.4 to +5.5V -Low power consumption -Low output impedance -Operating temperature : -30 to +85 -Package : Super slim TCP (Tape Carrier Package)/Au Bumped chip [Segment mode] -. Shift clock frequency : 8 MHz (MAX) -. Adopts a data bus system -. 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin -. Automatic transfer function of an enable signal -. Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 160 bits of input data -. Line latch circuits are reset when DISPOFFB active [Common mode] -. Shift clock frequency : 4 MHz( MAX) -. Built-in 160-bit bi-directional shift register -. Available in a single mode (160-bit shift register) or in a dual mode (80-bit shift register X 2) * Y1*Y160 Single mode * Y160*Y1 Single mode * Y1*Y80, Y81*Y160 Dual mode * Y160*Y81, Y80*Y1 Dual mode The above 4 shift directions are pin-selectable -. Shift register circuits are reset when DISPOFFB active TOMATO LSI Inc. 4 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 3. BLOCK DIAGRAM Y1 Y2 Y159 Y160 V 5R V 43R V 12R V OR 160 Level Shifter DISPOFFB 160 Bits Level Shifter 160 160 Bits Line Latch / Shifter Register Active Control EIO2 16 XCK 16 8 bits 8 bits x2 x2 Data Data Latch Latch (1) (2) Control Logic LP - - - - - - - - - - - - 16 MD Data Latch Control S/C 8 SP Conversion & Data Control (4 to 8 or 8 to 8) DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 Figure 3-1. block diagram 5 V DD 16 8 bits 8 bits x2 x2 Data Data Latch Latch (19) (20) L/R TOMATO LSI Inc. 5L V 43L V 12L V OL 160 Bits 4 - Level Driver FR EIO1 V V SS TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 4. PIN DESCRIPTION 4-1. Pin Description Table 4-1. Pin description SYMBOL I/O DESCRIPTION Y1 - Y160 O LCD drive output V0L, V0R - Power supply for LCD drive V12L, V12R - Power supply for LCD drive V43L, V43R - Power supply for LCD drive V5L, V5R - Power supply for LCD drive L/R I VDD - Power supply for logic system (+2.4 to +5.5V) S/C I Segment mode/common mode selection EIO2, EIO1 I/O DI0-DI6 I Display data input at segment mode DI7 I Display data input at segment mode/Dual mode data input at common mode XCK I Clock input for taking display data at segment mode DISPOFFB I Control input for output of non-select level LP I FR I AC-converting signal input for LCD drive waveform MD I Mode selection input VSS - Ground(0 V) TOMATO LSI Inc. Input for selecting the reading direction of display data at segment mode/ Input for selecting the shift direction of shift register at common mode Input/output for chip selection at segment mode/ Shift data input/output for shift register at common mode Latch pulse input for display data at segment mode/ Shift clock input for shift register at common mode 6 TL0134 160-Output LCD Segment/Common Driver IC 4-2. Pin Connections **Not fixed TOP VIEW 1 2 3 187-PIN TCP CHIP SURFACE Y1 Y2 Y3 Y 158 Y 159 Y 160 TOMATO LSI Inc. 158 159 160 187 V 0R V 12R V 43 R V 5R Vss MD FR EIO 1 LP DISPOFFB XCK DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 EIO 2 S/C V DD L/R V 5L V 43L V 12L 161 V 0L N OTE : Doesn't prescribe TCP outline 7 PRELIMINARY Ver 0.0 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 5. FUNCTIONAL DESCRIPTION 5-1. Pin Functions Table 5-1. Pin Functions(Segment mode) SYMBOL FUNCTION VDD Logic system power supply pin. (+2.4V to +5.5V) VSS Ground pin. (0V) Bias power supply pins for LCD drive voltage. V0L, V0R -Normally use the bias voltages set by a resistor divider. V12L, V12R -Ensure that voltages are set such that Vss * V5 < V43 < V12 < V0 V43L, V43R -V0L(R), V12L(R), V43L(R), V5L(R) must connect to an external power supply, and supply V5L, V5R regular voltage which is assigned by specification for each power pin. Input pins for display data. -In 4-bit parallel input mode, input data into the 4 pins, DI3-DI0. DI7-DI0 Connect DI7-DI4 to Vss or VDD. -In 8-bit parallel input mode, input data into the 8 pins, DI7-DI0. Clock input pin for taking display data. XCK -Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data. LP -Data is latched at the falling edge of the clock pulse. Input pin for selecting the reading direction of display data. L/R -When set to Vss level "L", data is read sequentially from Y160 to Y1. -When set to VDD level "H", data is read sequentially from Y1 to Y160. Control input pin for output of non-select level. -The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. -When set to Vss level "L", the LCD drive output pins(Y1-Y160)are set to level V5. -When set to "L", the contents of the line latch are reset, but the display data are DISPOFFB read in the data latch regardless of the condition of DISPOFFB. When the DISPOFFB function is canceled, the driver outputs non-select level (V12 or V43), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if DISPOFFB removal time does not correspond to what is shown in AC characteristics, it can not output the reading data correctly. AC signal input pin for LCD drive waveform. -The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. FR -Normally it inputs a frame inversion signal. -The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. Mode selection pin. MD -When set to Vss level "L", 4-bit parallel input mode is set. -When set to VDD level "H", 8-bit parallel input mode is set. Segment mode/common mode selection pin. S/C -When set to VDD level "H", segment mode is set. Input/output pins for chip selection. -When L/R input is at Vss level "L", EIO1 is set for output, and EIO2 is set for input. -When L/R input is at VDD level "H", EIO1 is set for input, and EIO2 is set for output. -During output, set to "H" while LP * XCK is "H" and after 160 bits of data have EIO1, EIO2 been read, set to "L" for one cycle (from falling edge to falling edge of XCK), after which it returns to "H". -During input, the chip is selected while EI is set to "L" after the LP signal is input. The chip is non-selected after 160 bits of data have been read. TOMATO LSI Inc. 8 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 SYMBOL FUNCTION Y1-Y160 LCD drive output pins. -Corresponding directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and output. Table 5-2. Pin Functions(Common mode) SYMBOL FUNCTION VDD Logic system power supply pin.(+2.4 to +5.5V) VSS Ground pin. (0V) Bias power supply pins for LCD drive voltage. -Normally use the bias voltages set by a resistor divider. -Ensure that voltages are set such that Vss * V5 < V43 < V12 < V0. -V0L(R), V12L(R), V43L(R), V5L(R) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin. Shift data input/output pin for bi-directional shift register. -Output pin when L/R is at Vss level "L", input pin when L/R is at VDD level "H". -When L/R = H, EIO1 is used as input pin, it will be pulled down. -When L/R = L, EIO1 is used as output pin, it won't be pulled down. Shift data input/output pin for bi-directional shift register. -Input pin when L/R is at Vss level "L", output pin when L/R is at VDD level "H". -When L/R = H, EIO2 is used as input pin, it will be pulled down. -When L/R = L, EIO2 is used as output pin, it won't be pulled down. V0L, V0R V12L, V12R V43L, V43R V5L, V5R EIO1 EIO2 LP L/R DISPOFFB FR MD TOMATO LSI Inc. Shift clock pulse input pin for bi-directional shift register. -Data is shifted at the falling edge of the clock pulse. Input pin for selecting the shift direction of bi-directional shift register. -Data is shifted from Y160 to Y1 when set to Vss level "L", and data is shifted from Y1 to Y160 when set to VDD level "H". Control input pin for output of non-select level. -The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. -When set to Vss level "L", the LCD drive output pins (Y1-Y160) are set to level V5. -When set to "L", the contents of the shift register are reset to not reading data. When the DISPOFFB function is canceled, the driver outputs non-select level (V12 or V43), and the shift data is read at the next falling edge of the LP. At that time, if DISPOFFB removal time does not correspond to what is shown in AC characteristics, the shift data is not read correctly. AC signal input pin for LCD drive waveform. -The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. -Normally it inputs a frame inversion signal. -The LCD drive output pins' output voltage levels can be set using the shift register output signal and the FR signal. Mode selection pin -When set to Vss level "L", single mode is selected, when set to VDD level "H", dual mode is selected. 9 TL0134 160-Output LCD Segment/Common Driver IC SYMBOL DI7 S/C DI6-DI0 XCK Y1-Y160 TOMATO LSI Inc. PRELIMINARY Ver 0.0 FUNCTION Dual mode data input pin. -According to the data shift direction of the data shift register, data can be input starting from the 81st bit. When the chip is used in dual mode, DI7 will be pulled down. When the chip is used in single mode, DI7 won't be pulled down. Segment mode/common mode selection pin. -When set to Vss level "L", common mode is set. Not used. -Connect DI6-DI0 to Vss or VDD, avoiding floating. Not used. -XCK is pulled down in common mode, so connect to Vss or open. LCD drive output pins. -Corresponding directly to each bit of the shift register, one level(V0, V12, V43, or V5) is selected and output. 10 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 5-2. Functional Operations of each block Table 5-3. Functional operations of each block BLOCK Active Control SP Conversion & Data Control Data Latch Control Data Latch Line Latch/ Shift Register Level shifter 4-Level Driver Control Logic TOMATO LSI Inc. FUNCTION In case of segment mode, controls the selection or non-selection of the chip. Following an LP signal input, and after the chip selection signal is input, a selection signal is generated internally until 160 bits of data have been read in. Once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. In case of common mode, controls the input/output data of bi-directional pins. In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel input mode in latch circuit, after that they are put on the internal data bus 8 bits at a time. In case of segment mode, selects the state of the data latch which reads in the data bus signals. The shift direction is controlled by the control logic. In case of segment mode, latches the data on the data bus. The latch state of each LCD drive output pin is controlled by the control logic and the data latch control, 160 bits of data are read in 20 sets of 8 bits In case of segment mode, all 160 bits which have been read into the data latch are simultaneously latched at the falling edge of the LP signal, and are output to the level shifter block. In case of common mode, shifts data from the data input pin at the falling edge of the LP signal. The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to the driver block. Drives the LCD drive output pins from the line latch/shift register data, and selects one of 4 levels (V0, V12, V43, or V5) based on the S/C, FR and DISPOFFB signals. Controls the operation of each block. In case of segment mode, when an LP signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission is controlled, 160 bits of data are read in, and the chip is non-selected. In case of common mode, controls the direction of data shift. 11 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 5-3. Functional Operations a. LCD drive output voltage level (Segment Mode) FR L L H H X LATCH DATA L H L H X DISPOFFB H H H H L LCD DRIVE OUTPUT VOLTAGE LEVEL(Y1-Y160) V43 V5 V12 V0 V5 (Common Mode) FR L L H H X LATCH DATA L H L H X DISPOFFB H H H H L LCD DRIVE OUTPUT VOLTAGE LEVEL(Y1-Y160) V43 V0 V12 V5 V5 Notes : - Vss * V5 < V43 < V12 < V0, L : Vss(0 V), H : VDD(+2.4 to +5,5V), X : Don't care -"Don't care" should be fixed to "H" or "L", avoiding floating. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage which is assigned by specification for each power pin. TOMATO LSI Inc. 12 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 b. Relationship between the display data and LCD drive output pins (Segment Mode) (a) 4-bit Parallel Input Mode MD L L L/R L H EIO1 Output Input EIO2 Input Output DATA INPUT NUMBER OF CLOCKS 1st 2nd 3rd .. 38th 39th 40th DI0 Y157 Y153 Y149 DI1 Y158 Y154 Y150 .. Y9 Y5 Y1 .. Y10 Y6 Y2 DI2 Y159 Y155 Y151 DI3 Y160 Y156 Y152 .. Y11 Y7 Y3 .. Y12 Y8 Y4 DI0 Y4 Y8 DI1 Y3 Y7 Y12 .. Y152 Y156 Y160 Y11 .. Y151 Y155 Y159 DI2 Y2 DI3 Y1 Y6 Y10 .. Y150 Y154 Y158 Y5 Y9 .. Y149 Y153 Y157 19th 20th (b) 8-bit Parallel Input Mode MD H H L/R L H EIO1 Output Input (Common Mode) MD L/R L L (Single) H H (Dual) L H EIO2 Input Output NUMBER OF CLOCKS DATA INPUT 1st 2nd 3rd .. 18th DI0 Y153 Y145 Y137 .. Y17 Y9 Y1 DI1 Y154 Y146 Y138 .. Y18 Y10 Y2 DI2 Y155 Y147 Y139 .. Y19 Y11 Y3 DI3 Y156 Y148 Y140 .. Y20 Y12 Y4 DI4 Y157 Y149 Y141 .. Y21 Y13 Y5 DI5 Y158 Y150 Y142 .. Y22 Y14 Y6 DI6 Y159 Y151 Y143 .. Y23 Y15 Y7 DI7 Y160 Y152 Y144 .. Y24 Y16 Y8 DI0 Y8 Y16 Y24 .. Y144 Y152 Y160 DI1 Y7 Y15 Y23 .. Y143 Y151 Y159 DI2 Y6 Y14 Y22 .. Y142 Y150 Y158 DI3 Y5 Y13 Y21 .. Y141 Y149 Y157 DI4 Y4 Y12 Y20 .. Y140 Y148 Y156 DI5 Y3 Y11 Y19 .. Y139 Y147 Y155 DI6 Y2 Y10 Y18 .. Y138 Y146 Y154 DI7 Y1 Y9 Y17 .. Y137 Y145 Y153 DATA TRANSFER DIRECTION Y1 Y160 * * Y160 Y1 Y160 * Y81 Y80 * Y1 * Y80 Y1 Y81 * Y160 Notes : - L : Vss(0 V), H : VDD (+2.4 to +5.5V), X : Don't care. - "Don't care" should be fixed to "H" or "L", avoiding floating. TOMATO LSI Inc. 13 EIO1 Output Input EIO2 Input Output DI7 X X Output Input Input Input Output Input TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 c. Connection examples of cascade segment drivers (a) When L/R = "L" Top data Last data Data direction Y1 EIO 1 Y1 EIO 2 EIO 1 Y1 EIO 2 EIO 1 DI7 -DI0 L/R MD FR XCK LP MD FR L/R DI7 -DI0 MD FR XCK LP L/R Y 160 XCK LP EIO 2 Y 160 DI7 -DI0 Y 160 XCK LP MD FR 8 / DI7- DI0 Vss (b) When L/R = "H" V DD 8 / DI7 -DI 0 FR MD LP L/R Vss EIO 1 Y1 Top data TOMATO LSI Inc. L/R EIO 2 EIO 1 Y 160 Y1 Data direction 14 XCK LP FR MD DI7 -DI0 XCK LP FR MD DI7 -DI0 XCK LP MD FR DI7 -DI0 XCK L/R EIO 2 Y 160 EIO 1 Y1 EIO 2 Y 160 Last data TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 d. Timing chart of 4-device cascade connection of segment drivers FR LP XCK TOP DATA DI7 -DI 0 n* 1 2 n* 1 device A EI (device A) LAST DATA 2 n* 1 device B 2 n* 1 device C (L= VSS) Eo (device A) Eo (device B) Eo (device C) *n = 40 in 4-bit parallel input mode. n = 20 in 8-bit parallel input mode. TOMATO LSI Inc. 15 2 n* 1 device D 2 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 e. Connection examples of cascade common drivers (a) Single Mode (L/R = "L") First EIO 1 EIO 2 Y1 Y 160 Y1 EIO 1 EIO 2 EIO 1 LP DI7 MD L/R DISPOFFB FR EIO 2 Y 160 LP DI7 MD L/R DISPOFFB FR DI Y1 LP DI7 MD LR DISPOFFB FR Y 160 Last LP Vss(V DD ) V SS V SS DISPOFFB FR (b) Single Mode( L/R = "H") FR DISPOFFB V DD V SS Vss(V DD ) DI EIO 1 EIO 2 EIO 1 EIO 2 EIO 1 EIO 2 Y1 Y 160 Y1 Y 160 Y1 Y 160 Last First TOMATO LSI Inc. FR DISPOFFB L/R MD DI7 LP FR DISPOFFB LR MD DI7 LP FR DISPOFFB L/R MD DI7 LP LP 16 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 (c) Dual Mode (L/R = "L") First 1 EIO 1 Y 160 Y 81 Y 80 Y 1 Y 160 Y1 EIO 2 EIO 2 EIO 1 EIO 1 LP DI7 MD L/R DISPOFFB FR EIO 2 LP DI7 MD L/R DISPOFFB FR DI1 Y1 LP DI7 MD LR DISPOFFB FR Y 160 Last 2 Last 1 First 2 DI2 LP V SS( V DD) V DD Vss DISPOFFB FR (d)Dual Mode(L/R = "H") FR DISPOFFB V DD V SS Vss(V DD ) LP FR DISPOFFB L/R MD DI7 LP EIO 1 EIO 1 EIO 2 Y1 Y 160 FR DISPOFFB L/R MD DI7 LP FR DISPOFFB LR MD DI7 LP DI2 DI1 EIO 1 Y1 EIO 2 Y 160 Y1 First1 TOMATO LSI Inc. EIO 2 Y 80 Y 81 Y 160 Last 1 First 2 17 Last2 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 5-4. Precautions -Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. The details are as follows. -When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power. -It is advisable to connect the serial resistor (50 to 100*) or fuse to the LCD drive power V0 of the system as a current limiter. Set up a suitable value of the resistor in consideration of the display grade. And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on DISPOFFB function. After that, cancel the DISPOFFB function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level V5 on DISPOFFB function. Then, disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here. V DD V DD Vss DISPOFFB V DD Vss V0 V0 Vss TOMATO LSI Inc. 18 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 6. SPECIFICATIONS 6-1. Absolute Maximum Ratings PARAMETER Supply voltage(1) Supply voltage (2) Input voltage Storage temperature SYMBOL APPLICABLE PINS RATING UNIT VDD V0 V12 V43 V5 VDD V0L, V0R V12L, V12R V43L, V43R V5L, V5R DI0-DI7, XCK, LP, L/R, FR, MD, S/C, EIO1 EIO2, DISPOFFB -0.3 to +7.0 -0.3 to +38.0 -0.3 to V0 + 0.3 -0.3 to V0 + 0.3 -0.3 to V0 + 0.3 V V V V V -0.3to VDD+ 0.3 V -45 to +125 * VI TSTG NOTE 1, 2 Notes : 1. Ta = +25* 2. The maximum applicable voltage on any pin with respect to Vss( 0 V) 6-2. Recommended Operating Conditions PARAMETER Supply voltage (1) Supply voltage (2) Operating temperature SYMBOL APPLICABLE PINS MIN. VDD V0 Ta VDD V0L, V0R +2.4 +10.0 -30 Notes : 1. The applicable voltage on any pin with respect to Vss (0 V) 2. Ensure that voltage are set such that Vss * V5 < V43 < V12 < V0 TOMATO LSI Inc. 19 TYP. MAX. UNIT +5.5 +35.0 +85 V V * NOTE 1, 2 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 6-3. Electrical Characteristics a. DC Characteristics (Segment Mode) PARAMETER Input "LOW" voltage Input "HIGH" voltage Output "LOW" voltage Output "HIGH" voltage Input leakage current Output resistance Standby current Supply current(1) (Non-selection) Supply current(2) (Selection) Supply current(3) (Vss = V5 = 0 V, VDD = +2.4 to +5.5V, V0 = +10.0 to +35.0 V, Ta = -30 to +85*) SYMBOL CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE DI7-DI0, XCK, LP, VIL 0.2VDD V L/R, FR, MD, S/C, EIO1, EIO2, 0.8VDD VIH V DISPOFFB, VOL IOL=+0.4mA +0.4 EIO1, EIO2 VOH IOH=-0.4mA ILIL VI = Vss ILIH VI RON l*VON l =0.5V = VDD VDD0.4 Y1-Y160 V0=20V -10.0 A +10.0 A 1.0 1.5 1.5 2.0 k* ISTB Vss 50.0 A 1 IDD1 VDD 2.0 mA 2 IDD2 VDD 7.0 mA 3 I0 V0L, V0R 0.9 mA 4 Notes : 1. VDD = +5.0 V, V0 = +35.0 V, VIH = VDD, VIL = Vss. 2. VDD = +5.0 V, V0 = +35.0 V, fXCK = 8MHz, no-load, EI = VDD. 3. VDD = +5.0 V, V0 = +35.0 V, fXCK= 8MHz, no-load, EI = Vss. The input data is turned over by data taking clock (4-bit parallel input mode). 4. VDD = +5.0 V, V0 = +35.0 V, fXCK = 8MHz, fLP = 19.2kHz, fFR = 80Hz, no-load. The input data is turned over by data taking clock(4-bit parallel input mode). TOMATO LSI Inc. V DI7-DI0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFFB V0=30V V 20 TL0134 (Common Mode) PARAMETER Input "LOW" voltage Input "HIGH" voltage Output "LOW" voltage Output "HIGH" voltage 160-Output LCD Segment/Common Driver IC (Vss = V5 = 0 V, VDD = +2.4 to +5.5V, V0 = +10.0 to +35.0 V, Ta = -30 to +85*) SYMBOL CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE DI7-DI0, XCK, LP, VIL 0.2VDD V L/R, FR, MD, S/C, EIO1, EIO2, VIH 0.8VDD V DISPOFFB, VOL IOL=+0.4mA +0.4 EIO1, EIO2 VOH IOH=-0.4mA ILIL VI = Vss ILIH VI = VDD Input pull-down current IPD VI = VDD Output resistance RON Standby current Supply current(1) Supply current(2) ISTB IDD I0 Input leakage current PRELIMINARY Ver 0.0 VDD0.4 V DI7-DI0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFFB DI7,XCK,EIO1,EIO2 l*VON l V0=30V =0.5V V0=20V Y1-Y160 A +10.0 A 100.0 A 1.5 1.5 2.0 50.0 80.0 130.0 Vss VDD V0L, V0R 21 -10.0 1.0 Notes : 1. VDD = +5.0 V, V0 = +35.0 V, VI = Vss. 2. VDD = +5.0 V, V0 = +35.0 V, fLP = 19.2 kHz, fFR= 80Hz, 1/240 duty operation, no-load. TOMATO LSI Inc. V k* A A A 1 2 2 TL0134 b. 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 AC Characteristics ( Segment Mode ) (Vss = V5 = 0 V, VDD = +2.4 to +5.5 V, V0 = +10.0 to +35V, Ta= -30 to +85*) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Shift clock period twck TR, TF * 11ns 125 ns Shift clock "H" pulse width tWCKH 51 ns Shift clock "L" pulse width tWCKL 51 ns Data setup time tDS 30 ns Data hold time tDH 40 ns tWLPH 51 ns Shift clock rise to latch pulse rise time tLD 0 ns Shift clock fall to latch pulse fall time tSL 51 ns Latch pulse rise to shift clock rise time tLS 51 ns Latch pulse fall to shift clock fall time tLH 51 ns Enable setup time ts 36 ns Input signal rise time tR 50 ns Input signal fall time tF 50 ns Latch pulse "H" pulse width DISPOFFB removal time DISPOFFB "L" pulse width tSD 100 ns tWDL 1.2 s Output delay time(1) tD CL = 15 pF 78 ns Output delay time(2) tPD1, tPD2 CL = 15 pF 1.2 s Output delay time (3) tPD3 CL = 15 pF 1.2 s Notes : 1. Takes the cascade connection into consideration 2. (TWCK - TWCKH - TWCKL)/2 is maximum in the case of high speed operation. TOMATO LSI Inc. 22 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 6-4. Timing Chart of Segment Mode tWLPH LP tSL tLD tLH tLS tWCKH tWCKL XCK tR tF tWCK DI7 -DI 0 tDS LAST DATA tDH TOP DATA tWDL tSD DISPOFFB Fig. 6 Timing Characteristics (1) LP 1 XCK 2 n* ts EI tD EO * n=40 In case of 4-bit parallel input mode n=20 In case of 8-bit parallel input mode Fig. 7 Timing Characteristics (2) TOMATO LSI Inc. 23 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 FR tPD1 LP tPD2 DISPOFFB tPD3 Y 1 -Y 160 Fig. 8 Timing Characteristics (3) (Common Mode ) (Vss = V5 = 0V, VDD = +2.4 to +5.5V, V0 = +10.0 to +35.0V, Ta= -30 to +85*) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Shift clock period Shift clock "H" pulse width twLP tWLPH tR, tF * 20ns 250 ns VDD = +5.00.5V 15 ns VDD = +2.4 to +4.5V 30 ns Data setup time tsu 30 ns Data hold time tH 50 ns Input signal rise time tR 50 ns Input signal fall time tF 50 ns DISPOFFB removal time DISPOFFB "L" pulse width tSD 100 ns tWDL 1.2 s Output delay time(1) tDL CL = 15 pF 200 ns Output delay time(2) tPD1, tPD2 CL = 15 pF 1.2 s Output delay time (3) tPD3 CL = 15 pF 1.2 s TOMATO LSI Inc. 24 TL0134 160-Output LCD Segment/Common Driver IC 6-5. Timing Chart of Common Mode tWLP LP tR tWLPH tsu tF tH EIO 2 (DI7 ) tDL EIO 1 tSD tWDL DISPOFFB FR tPD1 LP tPD2 DISPOFFB tPD3 Y 1 -Y 160 TOMATO LSI Inc. 25 PRELIMINARY Ver 0.0 TL0134 160-Output LCD Segment/Common Driver IC PRELIMINARY Ver 0.0 EIO1 TL0134 XCK LP FR XCK LP VSS EIO2 EIO1 TL0134 EIO2 TL0134 FR LP Common Data 2 EIO2 V0-V5 EIO1 DI7 FR EIO2 LP MPU LP XCK LP FR 26 TL0134 Power Supply EIO1 EIO2 FR Common Data 1 160 TL0134 TL0134 EIO1 80 FR 80 160 TOMATO LSI Inc. XCK LP EIO1 160 FR EIO2 160 XCK LP EIO1 160 TL0134 VGA LCD PANEL 640 X 480 DOT MATRIX TL0134 TL0134 EIO1 EIO2 TL0134 160 160 VSS XCK LP 160 160 FR EIO2 FR 160 TL0134 XCK LP EIO2 EIO1 FR EIO1 XCK LP EIO2 FR EIO EIO11 XCK LP EIO1 FR EIO2 6-6. System Configuration Example