TL0134 - Tomato LSI, Inc. - Datasheet.Directory

160-Output LCD Segment/Common Driver IC

JUNE. 2000.

VER 1.0

TOMATO LSI Inc.

TL0134

TL0134 160-Output LCD Segment/Common Driver IC PR ELIM IN ARY Ver 0.0

TOMATO LSI Inc. 2

TL0134 Specification revision history

Version Content Date

0.0 1. New documentation June. 2000

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 3

CONTENTS

1. INTRODUCTION -----------------------------------------------------------------------------------------------------------

2. FEATURES ---------------------------------------------------------------------------------------------------------------

3. BLOCK DIAGRAM -----------------------------------------------------------------------------------------------------

4. PIN DESCRIPTION ----------------------------------------------------------------------------------------------------

4-1. Pin Description

4-2. Pin Connections

5. FUNCTIONAL DESCRIPTION -----------------------------------------------------------------------------------

5-1.Pin Functions ----------------------------------------------------------------------------------------

a. Pin Functions(Segment mode)

b. Pin Functions(Common mode)

5-2. Functional Operations of each block -------------------------------------------------------------------------------

a. Functional operations of each block

5-3. Functional Operations---------------------------------------------------------------------------------------------------

a.LCD drive output voltage level

b. Relationship between the display data and LCD drive output pins

c. Connection Examples of Plural Segment Drivers

d. Timing chart of 4-device cascade connection of Segment Drivers

e. Connection examples for plural common drivers

5-4. Precautions----------------------------------------------------------------------------------------------------------

6. SPECIFIC ATIONS --------------------------------------------------------------------------------------------------------

6-1. Absolute maximum ratings ---------------------------------------------------------------------------------------

6-2. Recommended Operating Conditions------------------------------------------------------------------------------

6-3. Electrical Characteristics--------------------------------------------------------------------------------------------------

a. DC Characteristics(Segment mode/Common mode)

b. AC Characteristics(Segment mode)

6-4. Timing Chart of Segment Mode ----------------------------------------------------------------------------------------

6-5. Timing Chart of Common Mode -------------------------------------------------------------------------------

6-6. System Configuration Example -----------------------------------------------------------------------------------------

4

5

6

8

11

12

18

19

20

23

25

26

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 4

1. INTRODUCTION

The TL0134 is a 160-output segment/common driver IC suitable for driving medium scale dot matrix

LCD panels. Through the use of SST(Super Slim TCP) technology, it is ideal for substantially

decreasing the size of the frame section of the LCD module. The TL0134 is good both as a segment

driver and a common driver, and it can create a low power consuming, high-resolution LCD.

2. FEATURES

-Number of LCD drive outputs : 160

-Supply voltage for LCD drive : +10.0 to +35.0V

-Supply voltage for the logic system : +2.4 to +5.5V

-Low power consumption

-Low output impedance

-Operating temperature : -30 to +85 

-Package : Super slim TCP (Tape Carrier Package)/Au Bumped chip

[Segment mode]

-. Shift clock frequency : 8 MHz (MAX)

-. Adopts a data bus system

-. 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin

-. Automatic transfer function of an enable signal

-. Automatic counting function which, in the chip selection mode, causes the internal clock to be

stopped by automatically counting 160 bits of input data

-. Line latch circuits are reset when DISPOFFB active

[Common mode]

-. Shift clock frequency : 4 MHz( MAX)

-. Built-in 160-bit bi-directional shift register

-. Available in a single mode (160-bit shift register) or in a dual mode (80-bit shift register X 2)

• Y1•Y160 Single mode

• Y160•Y1 Single mode

• Y1•Y80, Y81•Y160 Dual mode

• Y160•Y81, Y80•Y1 Dual mode

The above 4 shift directions are pin-selectable

-. Shift register circuits are reset when DISPOFFB active

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 5

3. BLOCK DIAGRAM

Figure 3-1. block diagram

Level

Shifter

FR

DISPOFFB

Active

Control

EIO1

EIO2

Control

Logic

LP

XCK

Data Latch Control

SP Conversion & Data Control

(4 to 8 or 8 to 8)

160 Bits Line Latch / Shifter Register

16 - - - - - - 16 16

8 bits

x2

Data

Latch

(1)

8 bits

x2

Data

Latch

(2)

- - - - - -

8 bits

x2

Data

Latch

(19)

8 bits

x2

Data

Latch

(20)

160 Bits Level Shifter

160

160 Bits 4 - Level Driver

Y1 Y2 Y

160

Y

159

¡¥¡¥¡¥¡¥¡¥¡¥¡¥¡¥¡¥¡¥¡¥¡¥¡¥¡¥¡¥

V

OR

V

12R

V

43R

V

5R

160

8

16

L/R

MD

S/C

V

5L

V

43L

V

12L

V

OL

DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7

V

DD

V

SS

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 6

4. PIN DESCRIPTION

4-1. Pin Description

Table 4-1. Pin description

SYMBOL I/O DESCRIPTION

Y1 – Y160 O LCD drive output

V0L, V0R - Power supply for LCD drive

V12L, V12R - Power supply for LCD drive

V43L, V43R - Power supply for LCD drive

V5L, V5R - Power supply for LCD drive

L/R I Input for selecting the reading direction of display data at segment mode/

Input for selecting the shift direction of shift register at comm on mode

VDD - Power supply for logic system (+2.4 to +5.5V)

S/C I Segment mode/common mode selection

EIO2, EIO1I/O Input/output for chip selection at segment mode/

Shift data input/output for shift registe r at common mode

DI0-DI6I Display data input at segment mode

DI7I Display data input at segment mode/Dual mode data input at common mode

XCK I Clock input for taking display data at segment mode

DISPOFFB I Control input for output of non-select level

LP I Latch pulse input for display data at segment mode/

Shift clock input for shift register at common mode

FR I AC-converting signal input for LCD drive waveform

MD I Mode selection input

VSS - Ground(0 V)

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 7

4-2. Pin Connections

**Not fixed

187

161

1

160

Y

1

Y

2

Y

3

Y

160

Y

159

Y

158

187-PIN TCP

V

0R

V

12R

V

0L

V

43R

V

5R

Vss

MD

FR

EIO

1

LP

DISPOFFB

XCK

DI

7

DI

6

DI

5

DI

4

DI

1

DI

2

DI

3

DI

0

EIO

2

S/C

V

DD

L/R

V

5L

V

43L

V

12L

N OTE :

Doesn't prescribe

TCP outline

2

3

158

159

TOP VIEW

CHIP SURFACE

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 8

5. FUNCTIONAL DESCRIPTIO N

5-1. Pin Functions

Table 5-1. Pin Functions(Segment mode)

SYMBOL FUNCTION

VDD Logic system power supply pin. (+2.4V to +5.5V)

VSS Ground pin. (0V)

V0L, V0R

V12L, V12R

V43L, V43R

V5L, V5R

Bias power supply pins for LCD drive voltage.

-Normally use the bias voltages set by a resistor divider.

-Ensure that voltages are set such that Vss • V5 < V43 < V12 < V0

-V0L(R), V12L(R), V43L(R), V5L(R) must connect to an external power supply, and supply

regular voltage which is assigned by specification for each power pin.

DI7-DI0

Input pins for display data.

-In 4-bit parallel input mode, input data into the 4 pins, DI3-DI0.

Connect DI7-DI4 to Vss or VDD.

-In 8-bit parallel input mode, input data into the 8 pins, DI7-DI0.

XCK Clock input pin for taking display data.

-Data is read at the falling edge of the clock pulse.

LP Latch pulse input pin for display data.

-Data is latched at the falling edge of the clock pulse.

L/R Input pin for selecting the reading direction of display data.

-When set to Vss level “L”, data is read sequentially from Y160 to Y1.

-When set to VDD level “H”, data is read sequentially from Y1 to Y160.

DISPOFFB

Control input pin for output of non-select level.

-The input signal is level-shifted from logic voltage level to LCD drive voltage level,

and controls the LCD drive circuit.

-When set to Vss level “L”, the LCD drive output pins(Y1-Y160)are set to level V5.

-When set to “L”, the contents of the line latch are reset, but the display data are

read in the data latch regardless of the condition of DISPOFFB.

When the DISPOFFB function is canceled, the driver outputs non-select level

(V12 or V43), then outputs the contents of the data latch at the next falling edge of

the LP. At that time, if DISPOFFB removal time does not correspond to what is

shown in AC character istic s , it can not out put the read ing data correctly.

FR

AC signal input pin for LCD drive waveform.

-The input signal is level-shifted from logic voltage level to LCD drive voltage level,

and controls the LCD drive circuit.

-Normally it inputs a frame inversion signal.

-The LCD drive output pins’ output voltage levels can be set using the line latch

output signal and the FR signal.

MD Mode selection pin.

-When set to Vss level “L”, 4-bit parallel input mode is set.

-When set to VDD level “H”, 8-bit parallel input mode is set.

S/C Segment mode/common mode selection pin.

-When set to VDD level “H”, segment mode is set.

EIO1, EIO2

Input/output pins for chip selection.

-When L/R input is at Vss level “L”, EIO1 is set for output, and EIO2 is set for input.

-When L/R input is at VDD leve l “H” , EIO 1 is set for input, and EIO2 is set for output.

-During output, set to “H” while LP • XCK is “H” and after 160 bits of data have

been read, set to “L” for one cycle (from falling edge to falling edge of XCK), after

which it returns to “H”.

-During input, the chip is selected while EI is set to “L” after the LP signal is input.

The chip is non-selected after 160 bits of data have been read.

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

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SYMBOL FUNCTION

Y1-Y160 LCD drive output pins.

-Corres pond ing directly to each bit of the d ata latc h , one level (V0, V12, V43, or V5) is

selected and output.

Table 5-2. Pin Functions(Common mode)

SYMBOL FUNCTION

VDD Logic system power supply pin.(+2.4 to +5.5V)

VSS Ground pin. (0V)

V0L, V0R

V12L, V12R

V43L, V43R

V5L, V5R

Bias power supply pins for LCD drive voltage.

-Normally use the bias voltages set by a resistor divider.

-Ensure that voltages are set such that Vss • V5 < V43 < V12 < V0.

-V0L(R), V12L(R), V43L(R), V5L(R) must connect to an external power supply, and supply

regular voltage which is assigned by specification for each power pin.

EIO1

Shift data input/output pin for bi-directional shift register.

-Output pin when L/R is at Vss level “L”, input pin when L/R is at VDD level “H”.

-When L/R = H, EIO1 is used as input pin, it will be pulled down.

-When L/R = L, EIO1 is used as output pin, it won’t be pulled down.

EIO2

Shift data input/output pin for bi-directional shift register.

-Input pin when L/R is at Vss level “L”, output pin when L/R is at VDD level “H”.

-When L/R = H, EIO2 is used as input pin, it will be pulled down.

-When L/R = L, EIO2 is used as output pin, it won’t be pulled down.

LP Shift clock pulse input pin for bi-directional shift register.

-Data is shifted at the falling edge of the clock pulse.

L/R Input pin for selecting the shift direction of bi-directional shift register.

-Data is shifted from Y160 to Y1 when set to Vss level “L”, and data is shifted from Y1

to Y160 when set to VDD level “H” .

DISPOFFB

Control input pin for output of non-select level.

-The input signal is level-shifted from logic voltage level to LCD drive voltage level,

and controls the LCD drive circuit.

-When set to Vss level “L”, the LCD drive output pins (Y1-Y160) are set to level V5.

-When set to “L”, the contents of the shift register are reset to not reading data.

When the DISPOFFB function is canceled, the driver outputs non-select level (V12

or V43), and the shift data is read at the next falling edge of the LP. At that time, if

DISPOFFB removal time does not correspond to what is shown in AC

characteristics, the shift data is not read correctly.

FR

AC signal input pin for LCD drive waveform.

-The input signal is level-shifted from logic voltage level to LCD drive voltage level,

and controls the LCD drive circuit.

-Normally it inputs a frame inversion signal.

-The LCD drive output pins’ output voltage levels can be set using the shift register

output signal and the FR signal.

MD Mode selection pin

-When set to Vss level “L”, single mode is selected, when set to VDD level “H”, dual

mode is selected.

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

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SYMBOL FUNCTION

DI7

Dual mode data input pin.

-According to the data shift direction of the data shift register, data can be input

starting from the 81st bit.

When the chip is used in dual mode, DI7 wi ll be pul led down.

When the chip is used in single mode, DI7 won’t be pull e d down.

S/C Segment mode/common mode selection pin.

-When set to Vss level “L”, common mode is set.

DI6-DI0Not used.

-Connect DI6-DI0 to Vss or VDD, avoiding float in g.

XCK Not used.

-XCK is pulled down in common mode, so connect to Vss or open.

Y1-Y160 LCD drive output pins.

-Corresponding directly to each bit of the shift register, one level(V0, V12, V43, or V5)

is selected and output.

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 11

5-2. Functional Operations of each block

Table 5-3. Functional operations of each block

BLOCK FUNCTION

Active Control

In case of segment mode, controls the selection or non-selection of the chip.

Following an LP signal input, and after the chip selection signal is input, a selection

signal is generated internally until 160 bits of data have been read in.

Once data input has been completed, a selection signal for cascade connection is

output, and the chip is non-selected.

In case of common mode, controls the input/output data of bi-directional pins.

SP Conversi on

& Data Control

In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel

input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel

input mode in latch circuit, after that they are put on the internal data bus 8 bits at a

time.

Data Latch Contro l In case of segment mode, selects the state of the data latch which reads in the data bus

signals. The shift direction is controlled by the control logic.

Data Latch In case of segment mode, latches the data on the data bus. The latch state of each

LCD drive output pin is controlled by the control logic and the data latch control, 160 bits

of data are read in 20 sets of 8 bits

Line Latch/

Shift Register

In case of segment mode, all 160 bits which have been read into the data latch are

simultaneously latched at the falling edge of the LP signal, and are output to the level

shifter block. In case of common mode, shifts data from the data input pin at the falling

edge of the LP signal.

Level shifter The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to

the driver block.

4-Level Dri ver Drives the LCD drive output pins from the line latch/shift register data, and selects one

of 4 levels (V0, V12, V43, or V5) based on the S/C, FR and DISPOFFB signals.

Control Logic

Controls the operation of each block. In case of segment mode, when an LP signal

has been input, all blocks are reset and the control logic waits for the selection signal

output from the active control block. Once the selection signal has been output,

operation of the data latch and data transmission is controlled, 160 bits of data are read

in, and the chip is non-selected. In case of common mode, controls the direction of

data shift.

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 12

5-3. Functional Operations

a. LCD drive output voltage level

(Segment Mode)

FR LATCH DATA DISPOFFB LCD DRIVE OUTPUT VOLTAGE LEVEL(Y1-Y160)

LLH V

43

LHH V

5

HLH V

12

HHH V

0

XXL V

5

(Common Mode)

FR LATCH DATA DISPOFFB LCD DRIVE OUTPUT VOLTAGE LEVEL(Y1-Y160)

LLH V

43

LHH V

0

HLH V

12

HHH V

5

XXL V

5

Notes : - Vss • V5 < V43 < V12 < V0, L : Vss(0 V), H : VDD(+2.4 to +5,5V), X : Don’t care

-“Don’t care” should be fixed to “H” or “L”, avoiding floating.

There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver.

Supply regular voltage which is assigned by specification for each power pin.

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 13

b. Relationship between the display data and LCD drive output pins

(Segment Mode)

(a) 4-bit Para llel Inp u t Mode

NUMBER OF CLOCKS

MD L/R EIO1 EIO2 DATA

INPUT 1st 2nd 3rd .. 38th 39th 40th

DI0Y157 Y153 Y149 .. Y9Y5Y1

DI1Y158 Y154 Y150 .. Y10 Y6Y2

DI2Y159 Y155 Y151 .. Y11 Y7Y3

L L Output Input

DI3Y160 Y156 Y152 .. Y12 Y8Y4

DI0Y4Y8Y12 .. Y152 Y156 Y160

DI1Y3Y7Y11 .. Y151 Y155 Y159

DI2Y2Y6Y10 .. Y150 Y154 Y158

L H Input Output

DI3Y1Y5Y9.. Y149 Y153 Y157

(b) 8-bit Para llel Inp u t Mode NUMBER OF CLOCKS

MD L/R EIO1 EIO2 DATA

INPUT 1st 2nd 3rd .. 18th 19th 20th

DI0Y153 Y145 Y137 .. Y17 Y9Y1

DI1Y154 Y146 Y138 .. Y18 Y10 Y2

DI2Y155 Y147 Y139 .. Y19 Y11 Y3

DI3Y156 Y148 Y140 .. Y20 Y12 Y4

DI4Y157 Y149 Y141 .. Y21 Y13 Y5

DI5Y158 Y150 Y142 .. Y22 Y14 Y6

DI6Y159 Y151 Y143 .. Y23 Y15 Y7

H L Output Input

DI7Y160 Y152 Y144 .. Y24 Y16 Y8

DI0Y8Y16 Y24 .. Y144 Y152 Y160

DI1Y7Y15 Y23 .. Y143 Y151 Y159

DI2Y6Y14 Y22 .. Y142 Y150 Y158

DI3Y5Y13 Y21 .. Y141 Y149 Y157

DI4Y4Y12 Y20 .. Y140 Y148 Y156

DI5Y3Y11 Y19 .. Y139 Y147 Y155

DI6Y2Y10 Y18 .. Y138 Y146 Y154

H H Input Output

DI7Y1Y9Y17 .. Y137 Y145 Y153

(Common Mode)

MD L/R DATA TRANSFER DIRECTION EIO1 EIO2 DI7

L Y160 • Y1Output Input X

L

(Single) H Y1 • Y160 Input Output X

L Y160 • Y81

Y80 • Y1Output Input Input

H

(Dual) H Y1 • Y80

Y81 • Y160 Input Output Input

Notes : - L : Vss(0 V), H : VDD (+2.4 to +5.5V), X : Don’t care.

- “Don’t care” shou ld be fixed to “H” or “L”, avoiding floating.

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

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c. Connection examples of cascade segment drivers

(a) When L/R = “L”

(b) When L/R = “H”

EIO

2

EIO

1

EIO

2

EIO

1

LP

MD

FR

DI

7

-DI

0

EIO

2

EIO

1

XCK

LP

MD

FR

DI

7

-DI

0

L/R L/R L/R

Y

160

Y

1

Y

160

Y

1

Y

160

Y

1

Top data

Data direction

Last data

XCK

LP

MD

FR

DI

7

-DI

0

XCK

LP

MD

FR

DI

7-

DI

0

Vss

8

/

Vss

Last data

EIO

2

EIO

1

EIO

2

EIO

1

LP

MD

FR

EIO

2

EIO

1

XCK

LP

MD

FR

DI

7

L/RL/RL/R

Y

160

Y

1

Y

160

Y

1

Y

160

Y

1

Top data

Data direction

XCK

LP

MD

FR

DI

7

-DI

0

XCK

-DI

0

DI

7

-DI

0

8

/

V

DD

XCK

LP

MD

FR

DI

7

-DI

0

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

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d. Timing chart of 4-device cascade connection of segment drivers

EI

(device A)

Eo

(device A)

Eo

(device B)

Eo

(device C)

n* 1 2 n* 1 2 n* 1 2 n* 1 2 n* 1 2

FR

LP

XCK

DI

7

-DI

0

TOP DATA LAST DATA

device A device B device C device D

*n = 40 in 4-bit parallel input mode.

n = 20 in 8-bit parallel input mode.

(L= V

SS)

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

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e. Connection examples of cascade common drivers

(a) Single Mode (L/R = “L”)

(b) Single Mode( L/R = “H”)

EIO

2

EIO

1

EIO

2

EIO

1

DI

7

MD

LR

DISPOFFB

FR

EIO

2

EIO

1

LP

DI

7

MD

L/R

DISPOFFB

FR

Y

160

Y

1

Y

160

Y

1

Y

160

Y

1

Last

LP

DI

7

MD

L/R

DISPOFFB

FR

LP

Vss(V

DD

)

V

SS

V

SS

DISPOFFB

First

DI

FR

EIO

2

EIO

1

EIO

2

EIO

1

DI

7

MD

LR

DISPOFFB

FR

EIO

2

EIO

1

LP

DI

7

MD

L/R

DISPOFFB

FR

Y

160

Y

1

Y

160

Y

1

Y

160

Y

1

First

LP

DI

7

MD

L/R

DISPOFFB

FR

LP

Last

DI

LP

FR

DISPOFFB

V

SS

Vss(V

DD

)

V

DD

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

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(c) Dual Mode (L/R = “L”)

(d)Dual Mode(L/R = “H”)

EIO

2

EIO

1

EIO

2

EIO

1

DI

7

MD

LR

DISPOFFB

FR

EIO

2

EIO

1

LP

DI

7

MD

L/R

DISPOFFB

FR

Y

160

Y

1

Y

160

Y

1

Y

160

Y

1

Last 2

LP

DI

7

MD

L/R

DISPOFFB

FR

LP

DI

2

V

SS(

V

DD)

V

DD

DISPOFFB

First

1

DI

1

FR

Vss

Y

81

Y

80

Last 1 First 2

EIO

2

EIO

1

EIO

2

EIO

1

DI

7

MD

LR

DISPOFFB

FR

EIO

2

EIO

1

LP

DI

7

MD

L/R

DISPOFFB

FR

Y

160

Y

1

Y

160

Y

1

Y

160

Y

1

First

1

LP

DI

7

MD

L/R

DISPOFFB

FR

LP

Last2

DI

1

LP

FR

DISPOFFB

V

SS

Vss(V

DD

)

V

DD

DI

2

Y

80

Y

81

Last 1 First 2

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 18

5-4. Precautions

-Precautions when connecting or disconnecting the power supply

This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may

flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating.

The details are as follows.

-When connecting the power supply, connect the LCD drive power after connecting the logic system

power. Furthermore, when disconnecting the power, disconnect the logic system power after

disconnecting the LCD drive power.

-It is advisable to connect the serial resistor (50 to 100•) or fuse to the LCD drive power V0

of the system as a current limiter. Set up a suitable value of the resistor in consideration of the display

grade.

And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore

connect the LCD drive power supply after resetting logic condition of this IC inside on DISPOFFB function.

After that, cancel the DISPOFFB function after the LCD drive power supply has become stable.

Furthermore, when disconnecting the power, set the LCD drive output pins to level V5 on DISPOFFB

function. Then, disconnect the logic system power after disconnecting the LCD drive power.

When connecting the power supply, follow the recommended sequence shown here.

DISPOFFB

V

DD

V

DD

Vss

V

DD

Vss

V

0

Vss

V

0

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

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6. SPECIFICATIONS

6-1. Absolute Maximum Ratings

PARAMETER SYMBOL APPLICABLE PINS RATING UNIT NOTE

Suppl y voltag e( 1) VDD VDD -0.3 to +7.0 V

V0V0L, V0R -0.3 to +38.0 V

V12 V12L, V12R -0.3 to V0 + 0.3 V

V43 V43L, V43R -0.3 to V0 + 0.3 V

Supply voltage (2)

V5V5L, V5R -0.3 to V0 + 0.3 V

Input voltage VIDI0-DI7, XCK, LP, L/R, FR, MD,

S/C, EIO1 EIO2, DISPOFFB -0.3to VDD+ 0.3 V

1, 2

Storage temperature TSTG -45 to +125 •

Notes : 1. Ta = +25•

2. The maximum applicable voltage on any pin with respect to Vss( 0 V)

6-2. Recommended Operating Conditions

PARAMETER SYMBOL APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE

Supply voltage (1) VDD VDD +2.4 +5.5 V

Supply voltage (2) V0V0L, V0R +10.0 +35.0 V 1, 2

Operating temperature Ta-30 +85 •

Notes : 1. The applicable voltage on any pin with respect to Vss (0 V)

2. Ensure that voltage are set such that Vss • V5 < V43 < V12 < V0

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 20

6-3. Electrical Charac teristics

a. DC Characteristics

(Segment Mode) (Vss = V5 = 0 V, VDD = +2.4 to +5.5V, V0 = +10.0 to +35.0 V, Ta = -30 to +85•)

PARAMETER SYMBOL CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE

Input “LOW”

voltage VIL 0.2VD

D

V

Input “HIGH”

voltage VIH

DI7-DI0, XCK, LP,

L/R, FR, MD, S/C,

EIO1, EIO2,

DISPOFFB, 0.8VD

D

V

Output “LOW”

voltage VOL IOL=+0.4mA +0.4 V

Output “HIGH”

voltage VOH IOH=-0.4mA EIO1, EIO2VDD-

0.4 V

ILIL VI = Vss -10.0 µA

Input leakage

current ILIH VI = VDD

DI7-DI0, XCK, LP,

L/R, FR, MD, S/C,

EIO1, EIO2,

DISPOFFB +10.0 µA

V0=30V 1.0 1.5

Output

resistance RON l•VON l

=0.5V V0=20V Y1-Y160 1.5 2.0 k•

Standby current ISTB Vss 50.0 µA1

Supply current(1)

(Non-selection) IDD1 VDD 2.0 mA 2

Supply current(2)

(Selection) IDD2 VDD 7.0 mA 3

Supply current(3) I0V0L, V0R 0.9 mA 4

Notes : 1. VDD = +5.0 V, V0 = +35.0 V, VIH = VDD, VIL = Vss.

2. VDD = +5.0 V, V0 = +35.0 V, fXCK = 8MHz, no-load, EI = V DD.

3. VDD = +5.0 V, V0 = +35.0 V, fXCK= 8MHz, no-load, EI = Vss.

The input data is turned over by data taking clock (4-bit parallel input mode).

4. VDD = +5.0 V, V0 = +35.0 V, fXCK = 8MHz, fLP = 19.2kHz, fFR = 80Hz, no-load.

The input data is turned over by data taking clock(4-bit parallel input mode).

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 21

(Common Mode) (Vss = V5 = 0 V, VDD = +2.4 to +5.5V, V0 = +10.0 to +35.0 V, Ta = -30 to +85•)

PARAMETER SYMBOL CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE

Input “LOW”

voltage VIL 0.2VD

D

V

Input “HIGH”

voltage VIH

DI7-DI0, XCK, LP,

L/R, FR, MD, S/C,

EIO1, EIO2,

DISPOFFB, 0.8VD

D

V

Output “LOW”

voltage VOL IOL=+0.4mA +0.4 V

Output “HIGH”

voltage VOH IOH=-0.4mA EIO1, EIO2VDD-

0.4 V

ILIL VI = Vss -10.0 µA

Input leakage

current ILIH VI = VDD

DI7-DI0, XCK, LP,

L/R, FR, MD, S/C,

EIO1, EIO2,

DISPOFFB +10.0 µA

Input pull-down

current IPD VI = VDD DI7,XCK,EIO1,EIO2100.0 µA

V0=30V 1.0 1.5

Output

resistance RON l•VON l

=0.5V V0=20V Y1-Y160 1.5 2.0 k•

Standby current ISTB Vss 50.0 µA1

Supply current(1) IDD VDD 80.0 µA2

Supply current(2) I0V0L, V0R 130.0 µA2

Notes : 1. VDD = +5.0 V, V0 = +35.0 V, VI = Vss.

2. VDD = +5.0 V, V0 = +35.0 V, fLP = 19.2 kHz, fFR= 80Hz, 1/240 duty operation, no-load.

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 22

b. AC Characteristics

( Segment Mode ) (Vss = V5 = 0 V, VDD = +2. 4 to +5.5 V, V0 = +10.0 to +35V, Ta= -30 to +85•)

PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT

Shift clock period twck TR, TF • 11ns 125 ns

Shift clock “H” pulse width tWCKH 51 ns

Shift clock “L” pulse width tWCKL 51 ns

Data setup time tDS 30 ns

Data hold tim e tDH 40 ns

Latch pulse “H” pulse width tWLPH 51 ns

Shift clock rise to latch pulse rise time tLD 0ns

Shift clock fall to latch pulse fall time tSL 51 ns

Latch pulse rise to shift clock rise time tLS 51 ns

Latch pulse fall to shift clock fall time tLH 51 ns

Enable setup time ts 36 ns

Input signal rise time tR50 ns

Input signal fall time tF50 ns

DISPOFFB removal time tSD 100 ns

DISPOFFB “L” pulse width tWDL 1.2 µs

Output delay time(1) tDCL = 15 pF 78 ns

Output delay time(2) tPD1, tPD2 CL = 15 pF 1.2 µs

Output delay time (3) tPD3 CL = 15 pF 1.2 µs

Notes : 1. Takes the cascade connection into consideration

2. (TWCK - TWCKH – TWCKL)/2 is maximum in the case of high speed operation.

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 23

6-4. Timing Chart of Segment Mode

Fig. 6 Timing Characteristics (1)

Fig. 7 Timing Characteristics (2)

t

R

t

LD

t

WLPH

t

F

t

LS

t

SL

t

WCKH

t

LH

t

WCKL

t

WCK

t

DS

t

DH

t

WDL

t

SD

LAST DATA TOP DATA

LP

XCK

DI

7

-DI

0

DISPOFFB

LP

ts

t

D

12 n*

XCK

EI

EO

* n=40 In case of 4-bit parallel input mode

n=20 In case of 8-bit parallel input mode

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 24

Fig. 8 Timing Characteristics (3)

(Common Mode ) (Vss = V5 = 0V, VDD = +2.4 to +5.5V, V0 = +10.0 to +35.0V, Ta= -30 to +85•)

PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT

Shift clock period twLP tR, tF • 20ns 250 ns

VDD = +5.0±0.5V 15 ns

Shift clock “H” pulse width tWLPH VDD = +2.4 to +4.5V 30 ns

Data setup time tsu 30 ns

Data hold tim e tH50 ns

Input signal rise time tR50 ns

Input signal fall time tF50 ns

DISPOFFB removal time tSD 100 ns

DISPOFFB “L” pulse width tWDL 1.2 µs

Output delay time(1) tDL CL = 15 pF 200 ns

Output delay time(2) tPD1, tPD2 CL = 15 pF 1.2 µs

Output delay time (3) tPD3 CL = 15 pF 1.2 µs

t

PD1

t

PD2

t

PD3

FR

LP

DISPOFFB

Y

1

-Y

160

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 25

6-5. Timing Chart of Common Mode

DISPOFFB

t

WLP

tsu t

H

t

DL

t

WDL

t

SD

t

R

t

WLPH

t

F

LP

EIO

2

(DI

7

)

EIO

1

DISPOFFB

t

PD1

t

PD2

t

PD3

FR

LP

Y

1

-Y

160

TL0134 160-Output LCD Segment/Common Driver IC PREL IMINARY Ver 0.0

TOMATO LSI Inc. 26

6-6. System Conf iguration Example

640 X 480 DOT MATRIX

VGA LCD PANEL

EIO1

160

XCK

LP

EIO1EIO2

TL0134

160

XCK

LP

EIO1EIO2

TL0134

EIO1

160

XCK

LP

EIO2

TL0134

EIO1

160 XCK

LP

EIO1

EIO2

TL0134

160 XCK

LP

EIO1

EIO2

TL0134

160 XCK

LP

EIO1

EIO2

TL0134

160 XCK

LP

EIO2

TL0134

EIO1

160

XCK

LP

EIO2

TL0134

160

LP

EIO1

TL0134

EIO2 EIO1

TL0134

EIO2

LP

EIO1

TL0134

EIO2

DI

7

LP

80 80 160

Common Data 1

Common Data 2

VSS

V0-V5

FR

MPU XCK

LP

FR

Power

Supply