EFP01 Energy Friendly PMIC Family Data

The EFP01 Energy Friendly Power Management IC (PMIC) is an

extremely flexible, highly efficient, multi-output power management

IC, providing complete system power and primary cell battery Cou-

lomb counting for EFM32 and EFR32 devices. The EFP01 can op-

erate over a wide input voltage range (0.8 to 5.5 V) with quiescent

current as low as 300 nA (EM2 mode, single output enabled).

EFP01 can be configured to support the following battery types:

• Single lithium ion/lithium polymer (typically LiCoO2) rechargeable batteries (2.7 to

4.35 V)

• Single lithium iron phosphate (LiFePO4) rechargeable battery (2.5 to 3.65 V)

• USB (< 5.5 V)

ENERGY FRIENDLY FEATURES

• Provides 4 supply outputs:

• One Buck/Boost DC-DC Converter

• One Buck-only DC-DC Converter +

• One LDO

• Health and Wellness

• Wearables

• Smart Accessories

• Human Interface Devices

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1. Feature List

The EFP01 highlighted features are listed below.

• Output Voltage: 1.7 V to 5.2 V

• DCDC A can be configured in Buck/Boost, Buck-only, or

• Output Voltage:

• DCDC B can be used only in Buck configuration

• Dedicated internal linear regulator in parallel provides more

Feature List

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2. Ordering Information

Table 2.1. Ordering Information

Orderable Part Number

Supported Input

Voltage Range

Device Configuration VOB Configuration

at Startup

Package Top Mark

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3. System Overview

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VOA Out-

put at

Mode at

VOB Out-

put at

VOB Pro-

ble Range

VOC Out-

put at

EM4 Sup-

Wired Buck with LDO C

with LDO

OFF 0.8 V -1.26

Not availa-

ble (Paired

with VOA)

Single-Cell Boost

OFF 0.8 V -1.26

OFF Not sup-

Wired Boost

1.858 V 0.8 V -3.3

1.870 V Supported Yes, on

Wired Boost

OFF 0.8 V -1.26

1.870 V Supported,

ted Ena-

>= 2.5V.

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3.2 Power

The EFP01 can provide up to three voltage rails for EFR32 and EFM32 devices from a single input supply voltage.

The EFP01 has two independent DCDC converters: DCDC A and DCDC B, each requiring an external inductor. DCDC A can use buck/

boost, wired buck, or wired boost configurations, while DCDC B only supports buck configuration.

In addition, the EFP01 has two integrated LDOs supplied from the VDDB pin: LDO B and LDO C. LDO B is internally wired in parallel

with DCDC B. LDO C can be used independently or externally wired in parallel with DCDC A.

The EFP01's DCDC A can be configured for buck/boost, wired buck, or wired boost modes.

Table 3.2. DCDC A Configuration and Modes Summary

Hardware Configuration DCDC A Operat-

ing Mode

Required Register Setting Compatible OPNs

Buck with LDO Wired Buck with

BB_CTRL3.BB_MODE = 5 EFP0104

BB_CTRL3.BB_MODE = 1 (typi-

Single-Cell Boost Wired Boost BB_CTRL3.BB_MODE = 7 EFP0108

Note that in Boost modes it is possible to program the VOA output voltage to a voltage higher than the Maximum Output Voltage in the

Electrical Characteristics table. Firmware should ensure that the Maximum Output Voltage isn't exceeded.

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3.2.1.7 NTM Buck/Boost Transitional Mode

When DCDC A is in the Buck/Boost configuration and programmed to Autonomous (or Buck/Boost) mode, (i.e, BB_CTRL3.BB_MODE

= 1), the DCDC converter will automatically switch between one of three operating modes:

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3.2.1.9 DCDC A with LDO C in Parallel

In certain configurations, DCDC A is connected in parallel with LDO C on the printed circuit board, such as 4.1.2 Wired Buck with LDO

C Configuration (EFP0104) . This configuration is advantageous when the minimum input supply voltage approaches the VOA output

voltage (e.g., VDDBMIN - VOA ≤ 300mV) as it allows EFP01 to continue to regulate the output voltage over a wider input voltage range

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3.2.2.2 Peak Current Configuration

DCDC B has configurable peak current adjustment, set by the BK_IPK and BK_IPK_EM2 fields in the BK_IPK register.

In EM0, IPK_BASE is determined by: IPK _BASE = 0.090A+ (0.009A×BK _IPK )

Typically, the peak current can be lowered in EM2 for improved efficiency.

Note: The Maximum Output Current formula below provides useful guidance but is not a guarantee of performance. The final authority

for the Maximum Output Current will be the Output Load Current specifications in the Electrical Characteristics tables.

The DCDC B buck converter maximum output current is determined by: Maximum Output Current (A) = 0.5 × IPK _BASE

3.2.2.3 Current Limiting

When powering EFP01 from weak power sources or sources with a high internal impedance, peak load currents at the converter output

can cause a large supply voltage droop at the input, increasing the risk of an unintended power-on reset. To alleviate these issues, it

DCDC B inductor value (LB), peak current (IPK, set by BK_IPK), and the desired limited battery current (IBATT_LIMIT) as follows:

VDDB -VOB

where TSW is programmed by BK_IRI_CON as follows:

2 × BK_IRI_CON + 1

The maximum output load current is going to be limited accordingly, and can be determined by:

VOB ). As VDDB approaches VOB, the resulting TON can become quite large, resulting in large output ripple voltage or, in the worst

case, the DCDC stalling altogether.

When the BK_TON_MAX field in the BK_CTRL1 register is set to a non-zero value, the PFM pulse TON is limited to no more than 70 ns

× (1 + 4 × BK_TON_MAX), which terminates the inductor charging before the programmed peak current value is reached. When oper-

ating in this TON limiting mode, the maximum available load current and the actual peak current values are reduced from the otherwise

expected value.

Because the time measuring mechanism costs some power, BK_TON_MAX should be set to set a nonzero value only under specific

• If the subsequent reduction in max available load current can be tolerated and the reduction in ripple voltage is desired.

• When operating with low input voltage headroom (i.e., VDDB - VOB is very small) and there is no LDO enabled in parallel with the

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3.2.2.5 DCDC B with LDO B in Parallel

DCDC B is internally connected in parallel with LDO B, and the two can optionally be used in parallel. This configuration is advanta-

geous when the minimum input supply voltage approaches the VOA output voltage (e.g., VDDBMIN - VOB ≤ 300mV) as it allows EFP01

3.2.3 LDO B and LDO C Overview

The EFP01 has two integrated LDOs supplied from the VDDB pin. Instead of being continously on, each LDO operates in a pulsed-

current mode that minimizes quiescent current and is compatible with the internal Coulomb counter.

3.2.3.1 LDO B

LDO B is hard-wired in parallel with DCDC B, with an output sharing the VOB pin. When used in parallel with DCDC B, DCDC B will

automatically switch to LDO B to provide better efficiency as the input voltage approaches the output voltage. LDO B can also be used

as a standalone LDO (i.e. without DCDC B).

LDO B shares the DCDC B output voltage target registers, VOB_EM0_V and VOB_EM2_V.

Table 3.4. LDO B Summary

Mode Required Register Configuration(s) Output Pin Output Target Voltage Registers

LDO C's output voltage register depends on the mode:

• In standalone mode, the output voltage target is set in the VOC_V register.

• In parallel mode, the LDO C shares DCDC A's output voltage register, VOA_V.

Table 3.5. LDO C Summary

Mode Required Register Configuration(s) Output Pin Output Target Voltage Regis-

In parallel with

DCDC A

BB_CTRL3.BB_MODE = 5 VOA = VOC (must be shorted to-

gether on PCB)

Standalone, no

LDOC_CTRL.LDOC_ENA_SA = 1 and

BB_CTRL3.BB_MODE != 5

VOC VOC_V

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3.2.3.3 Maximum Output Current

After startup, the maximum output current for LDO B and LDO C is set by the LDOB_IGAIN and LDOC_IGAIN fields in the

LDOB_CTRL and LDOC_CTRL registers, respectively. The LDOx_IGAIN fields should be set to the required output current plus mar-

gin, but no higher than necessary. LDOx_IGAIN can be computed as follows:

Note: The Maximum Output Current formula below provides useful guidance but is not a guarantee of performance. The final authority

for the Maximum Output Current will be the Output Load Current specifications in the Electrical Characteristics tables.

at startup is always at least the desired amount (as configured by LDOx_IGAIN, above), the settings for the LDOx_VMIN fields should

be programmed based on the output target voltage as shown below:

Table 3.6. LDOx_VMIN Settings

VOUT Range LDOx_VMIN Setting

VOUT ≥ 2.7V 3

2.4V ≤ VOUT < 2.7V 2

2.0V ≤ VOUT < 2.4V 1

VOUT < 2.0V 0

Table 3.7 Example LDOx_IGAIN and LDOx_VMIN settings on page 20 shows the recommended LDOx_IGAIN and LDOx_VMIN set-

tings for some example applications. Note that in the calculations below, IOUT_MAX has been increased by 20% to provide some margin.

1.2 (LDO B only) 50 10 0

3.2.3.4 LDO Current Limiting

On EFP01, the current limit is controlled by forcing a minimum time between the start of pulse events (TSW_MIN) and is configured by

the BK_IRI_CON bitfield in the BK_CTRL2 register (for LDO B) or the VOC_IRI_CON bitfield in the LDOC_BB_CTRL register (for LDO

C). The (IBATT_LIMIT) can be determined from the IRI_CON setting as follows:

where IOUT_MAX is determined by LDOx_IGAIN as shown in 3.2.3.3 Maximum Output Current.

Because the current limit is essentially current-starving the output, most applications will likely want to disable the current limit after the

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3.2.3.5 LDO Startup

In some configurations, the LDO input supply (i.e., the VDDB pin) is powered from the VOA output. The VOA output may see momenta-

ry voltage droops when the LDO is enabled due to instantaneous current required to charge the 10µF capacitors on the LDO outputs.

To avoid this, the current limit can be enabled before the LDO is enabled and then disabled after the LDO output is stable. Consult

3.2.3.4 LDO Current Limiting for more information.

3.2.3.7 Bypass Mode

Both LDO B and LDO C support a bypass mode, in which the VDDB pin input voltage is shorted directly to the corresponding output pin

(VOB and VOC, respectively). By default, both LDOs automatically enter bypass mode when the input supply voltage at VDDB drops

too low to maintain regulation accuracy. This behavior can be disabled for both LDOs by setting the LDO_NO_AUTO_BYP bit in the

LDOB_CTRL register.

In addition, both LDO B and LDO C can be forced into bypass mode by setting the BYP bit in the LDOB_CTRL and LDOC_CTRL regis-

ters, respectively. When forcing bypass mode, care must be taken to ensure that any loads attached to the LDO output pins (VOB and

VOC) are tolerant of the VDDB pin input voltage.

3.2.4 Coarse Regulators

Each EFP01 output (VOA, VOB, VOC) has its own coarse regulator in parallel for use in EM4. The coarse regulators have very low

mode. For this reason, the VOB coarse regulator and VOB coarse regulator bypass features are disabled on these OPNs.

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3.3 Energy Modes

The EFP01 operates in 3 different energy modes to optimize efficiency based on the expected load.

Energy Mode Maximum Out-

put Current (per

Coarse Regula-

DCDCs and

ADC Coulomb Coun-

rent (value de-

pends on mode

and configuration)

and configuration)

ing to setting of

bits in

LDOs disabled

3.3.1 Energy Mode Control

The EFP01's internal pull up resistors on I2C_SDA and I2C_SCL pins will continue to be enabled in EM2 and EM4 modes when using

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3.3.1.2 Direct Mode Control

In direct mode, the internal pull-ups on the I2C_SDA and I2C_SCL pins are disabled, and the pins become high-impedance inputs that

the host processor can drive to quickly change energy modes.

Once enabled by setting the EM_DIRECTEN bit in the EM_CRSREG_CTRl register, direct mode allows the energy mode to be selec-

ted by driving the I2C_SDA and I2C_SCL pins according to Table 3.9 Direct Mode Energy Mode States on page 23. When I2C_SCL

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3.3.4 EM4

In EM4, the EFP01 disables all enabled DCDCs and LDOs, and enables any desired coarse regulators (i.e., those with their

CRSREG_EN_x bits set in the EM_CRSREG_CTRL register). ADC voltage and temperature measurements are disabled in EM4. Cou-

lomb counting is not supported in EM4.

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Factors Affecting the Charge-Per-Pulse

The charge-per-pulse (CPP) may vary depending on the operating mode of the converter. For example, if DCDC B is configured in

buck with LDO mode (i.e., the converter automatically switches between buck and LDO modes depending on input voltage), the CPP

when the converter is in buck can differ from the CPP when the converter is operating in LDO mode. For this reason, it may be neces-

sary to calibrate a given DCDC converter in each of its expected operating modes. Thus if DCDC B is in buck with LDO mode, and the

The current DCDC operating modes of DCDC A and DCDC B are reported by the CCA_MODE and CCB_MODE fields of the

CC_FULL flag. Note that the CC_FULL_UNMASK bit in the STATUS_GM register must be written to 1 so that an interrupt can be re-

quested when the CC_FULL flag is set. When firmware receives an interrupt, and discovers that CC_FULL is set, all relevant Coulomb

counter result registers should be read and added to local variable counts. Additionally,each converter's operating mode should be de-

termined (by reading the CCA_MODE or CCB_MODE field in the CC_MODE register for DCDC A or DCDC B, respectively) in order to

perform battery life calculations using the relevant CPP value. Clear the Coulomb counter result registers after reading them by writing

a 1 to the CC_CLR bit in the CMD register.

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4.1.3 Buck/Boost Configuration (EFP0107)

The buck/boost configuration is suitable for applications where the battery voltage may be above or below the required VOA output

voltage. Although very flexible, this configuration has worse efficiency than wired boost or wired buck configurations due to the losses in

the additional power FETs required to support both modes of operation. Typical power supply connections for a buck/boost configura-

tion are show in the following figure.

The supported operating mode settings for each converter in this configuration are shown below:

Table 4.3. Supported Operating Mode Settings

Converter / LDO Operating Mode Bitfield Supported Modes

DCDC A BB_CTRL3.BB_MODE Autonomous (ForceBuck, ForceBoost, ForceNTM can be used in

DCDC B BK_CTRL1.BK_MODE Disabled, BuckOnly, BuckLDO, or LDOOnly

LDO C LDOC_CTRL.LDOC_ENA_SA Enabled or Disabled

Typical Connection Diagrams

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4.1.4 Single-Cell Boost Configuration (EFP0108)

The single-cell boost configuration is a variant of the wired boost configuration intended primarily for use cases where the battery nomi-

nal voltage may be below the VDDB pin minimum voltage (1.8V) at startup. In this configuration, the EFP01 uses low-voltage supply

circuitry powered from the VDDA pin at startup to generate a voltage output on the VOA supply sufficient to meet the VDDB minimum

supply input requirement. After startup and once the VDDB voltage is above this minimum, standard boost operation resumes. Note

Single-cell boost configuration is suitable for the following:

Table 4.4. Supported Operating Mode Settings

Converter / LDO Operating Mode Bitfield Supported Modes

DCDC A BB_CTRL3.BB_MODE WiredBoost

DCDC B BK_CTRL1.BK_MODE Disabled, BuckOnly, BuckLDO, or LDOOn-

LDO C LDOC_CTRL.LDOC_ENA_SA Enabled or Disabled

In the single-cell boost configuration, up to 3 outputs are available. Typical power supply connections for a single-cell boost configura-

tion are shown below.

I2C SCL

10µF

VOC output