74F433SPC - Fairchild Semiconductor

April 1988

Revised August 1999

74F433 Fir st-In First-Out (FIFO) Buffer Memory

74F433

First-In First-Out (FIFO) Buffer Memory

General Descript ion

The 74F 433 i s an expandable fal l-th rou gh type high-speed

First-In First-Out (FIFO) Buffer Memory that is optimized for

high-speed disk or tape controller and communication

buffer applications. It is organized as 64-words by 4-bits

and may be expanded to any number of words or any num-

ber of bits in multiples of four. Data may be entered or

extracted asynchronously in serial or parallel, allowing eco-

nomical implementation of buffer memories.

The 74F4 33 has 3-STATE out puts that pr ovide ad ded ver-

satility, and is fully compatible with all TTL families.

Features

■Serial or parallel inpu t

■Serial or parallel out put

■Expandable without additional logic

■3-STATE outputs

■Fully compatible with all TTL families

■Slim 24-pin package

■9423 replacement

Ordering Code:

Logic Symbol Connection Diagram

Order Number Package Number Package Description

74F433SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

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74F433

Unit Loading/Fan Out

Block Diagram

Pin Names Description U.L. Input IIH/IIL

HIGH/LOW Output IOH/IOL

PL Parallel Load Input 1.0/0.66 20 µA/400 µA

CPSI Serial Input Clock 1.0/0.66 20 µA/400 µA

IES Serial Input Enable 1.0/0.66 20 µA/400 µA

TTS Transfer to Stack Input 1.0/0.66 20 µA/400 µA

MR Master Reset 1.0/0.66 20 µA/400 µA

OES Serial Output Enable 1.0/0.66 20 µA/400 µA

TOP Transfer Out Parallel 1.0/0.66 20 µA/400 µA

TOS Transfer Out Serial 1.0/0.66 20 µA/400 µA

CPSO Serial Output Clock 1.0/0.6 6 20 µA/400 µA

OE Output Enable 1.0/0.66 20 µA/400 µA

D0–D3Parallel Data Inputs 1.0/0.66 20 µA/400 µA

DSSerial Data Input 1.0/0.66 20 µA/400 µA

Q0–Q3Parallel Data Outputs 285/10 5.7 mA/16 mA

QSSeri al Data Output 285/10 5.7 µA/16 mA

IRF Input Register Full 20/5 400 µA/8 mA

ORE Output Register Empty 20/5 400 µA/8 mA

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74F433

Functional Description

As shown in the block diagram, the 74F433 consists of

three sectio ns:

1. An Input Register with parallel and serial data inputs,

as well as control inputs and outputs for input hand-

shaking and expansion.

2. A 4-bit-wi de, 6 2-word -deep fall-thr ough s tack with sel f-

contained control logic.

3. An Output Register with parallel and serial data out-

puts, as well as control inputs and outputs for output

handshaking and expansion.

These three sections operate asynchronously and are vir-

tually independent of one another.

Input Register (Data Entry)

The Input Register can receive data in either bit-serial or 4-

bit parallel fo rm. It sto re s t his data u ntil it is sent to the f all-

through stack, and also generates the necessary status

and control signals.

This 5-bit register (see Figure 1) is initialized by setting flip-

flop F3 and resetting the other flip-flops. The Q-output of

the last flip-flop (FC) is brought out as the Input Register

Full (IRF) signal. After initialization, this output is HIGH.

Parallel Entry—A HIGH on the Parallel Load (PL) input

loads the D0–D3 inputs into the F0–F3 flip-flops and sets

the FC fli p-f lop. Th i s f orces the IRF outp ut LOW, indica ting

that the input register is full. During parallel entry, the Serial

Input Clock (CPSI) input must be LOW.

Serial Entry—Data on the Serial Data (DS) input is serially

entered into the shift register (F3, F2, F 1, F0, FC) on each

HIGH-to-LOW transition of the CPSI input when the Serial

Input Enable (IES) signal is LOW. During serial entry, the

PL input should be LOW.

After the fourth clock transition, the four data bits are

located in flip-flops F0–F3. The FC flip-flop is set, forcing

the IRF output LOW and internally inhibiting CPSI pulses

from affecting the register. Figure 2 illustrates the final posi-

tions in an 74F433 resulting from a 256-bit serial bit train

(B0 is the first bit, B255 the last).

FIGURE 1. Conceptual Input Section

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74F433

FIGURE 2. Final Positions in an 74F433

Resulting from a 256-Bit Seri al Train

Fall-Through Stack—The outputs of flip-flops F0–F3 feed

the stack. A LOW level on the Transfer to Stack (TTS) input

initiates a fall-through action; if the top location of the stack

is empty, data is loaded into the stack and the input register

is re-initialized. (Note that this initialization is delayed until

PL is LOW). Thus, automatic FIFO action is achieved by

connecting the IRF output to the TTS inpu t.

An RS-type flip-flop (the initialization flip-flop) in th e control

section records the fact that data has been transferred to

the stack. This prevents multiple entry of the same word

into th e stack even th ough IRF a nd T TS may still be LOW;

the initialization flip-flop is not cleared until PL goes LOW.

Once in the stack, data falls through automatically, pausing

only when it is necessary to wait for an empty next location.

In the 74F433, the master reset (MR) input only initializes

the stack control section and does not clear the data.

Output Register

The Output Register (see Figure 3) receives 4-bit data

words from the bottom stack location, stores them, and out-

puts data on a 3-STATE, 4 -bit parallel d ata bus or on a 3-

STATE serial dat a bus. The output section generates and

receives the necessary status and control signals.

Parallel Extra ction —Whe n th e FIFO i s e m pt y a fte r a LO W

pulse is applied to the MR input, the Output Register Empty

(ORE) output is LOW. After data has b een en ter ed in to th e

FIFO and has fallen through to the bottom stack location, it

is transferred into the output register, if the Transfer Out

Paralle l (TOP) inpu t is HIGH. As a r esult of the da ta tran s-

fer, ORE goe s HIGH, indicating val id data on the data out-

puts (provided that the 3-STATE buffer is enabled). The

TOP input can then be used to clock out the next word.

When TOP goes LOW, ORE also goes LOW, indicating

that the output data has been extracted; however, the data

itself remains on th e output b us until a HIG H level on TOP

permits the transfer of the next word (if available) into the

output register. During parallel data extraction, the serial

output clock (CPSO) line sh ou ld be LO W. The Transfe r Ou t

Seria l (TOS) line sh ould be grou nded fo r sin gle-sli ce ope r-

ation or connected to the appropriate ORE line for

expanded operation (refer to the “Expansion” section).

The TOP signal is not edge-triggered. Therefore, if TOP

goes HIGH before data is available from the stack but data

becomes ava ilable before TOP again go es LOW, that d ata

is transferred into the output register. However, internal

control circuitry prevents the same data from being trans-

ferred twice. If TOP goes HIGH and returns to LOW before

data is available from the stack, ORE remains LOW, indi-

cating that there is no valid data at the outputs.

Serial Ex traction—When the FIFO is empty after a LOW

is applied to the MR input, the ORE output is LOW. After

data has been entered into the FIFO and has fallen through

to the bottom stack location, it is transferred into the output

result of the data transfer, ORE goes HIGH , indicat ing t hat

valid data is in the register.

The 3-STATE Serial Data Output (QS) is automatically

enable d and puts th e first d ata bit on the outpu t bus. Data

is serially shifted out on the HIGH-to-LOW transition of

CPSO. To prevent false shifting, CPSO should be LOW

when the new word is being loaded into the output register.

The fou rth tr ansit ion em pties the s hift reg ister, forces O RE

LOW, and disab les the serial output, QS. For serial oper a-

tion, the ORE output may be tied to the TOS input, request-

ing a new word from the stack as soon as the previous one

has been shifted out.

Expansion

Vertical Expansion—The 74F433 may be vertically

expanded, without external components, to store more

words. The interconnections necessary to form a 190-word

by 4-bit FIF O are sho wn in Fi gure 4. Using the sam e tech-

nique, a ny FIFO of (63 n+1)-words by 4-bi ts can be conf ig-

ured, where n is the number of devices. Note that

expansion does not sacrifice any of the 74F433 flexibility

for serial/parallel input and output.

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74F433

FIGURE 3. Conceptual Output Section

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74F433

FIGURE 4. A Vertical Expansion Scheme

Horizontal Expansion—The 74F433 can be horizontally

expanded, without external logic, to store long words (in

multiples of 4-bits). The interconnections necessary to form

a 64-word by 12-bit FIFO are shown in Figure 5. Using the

same technique, any FIFO of 64-words by 4n-bits can be

constructed, where n is the number of devices.

The right-most (most significant) device is connected to the

TTS inputs of al l devices. Similarl y, the ORE output of the

most significant device is connected to the TOS inputs of

all devices. As in the vertical expansion scheme, horizontal

expansion does not sacrifice any of the 74F433 flexibility

for serial/parallel input and output.

It should be noted that the horizontal expansion scheme

shown in Figure 5 exacts a penalty in speed.

Horizontal and Vertical Expansion—The 74 F433 can be

expanded in both the horizontal and vertical directions

without any external components and without sacrificing

any of its FIFO flexibility for serial/para llel input and output.

The inte rconne ctions nece ssary to for m a 127-wo rd by 16-

bit FIF O ar e sh own in Fig ur e 6. Using t he same techniq ue,

any FIFO o f (63m+1)-words by 4n-bits can be configured,

where m is th e n um ber of de vices i n a co lumn an d n i s the

number of devices in a row. Figure 7 and Figure 8 illustrate

the tim ing diagra ms for ser ial data entry and ext raction for

the FIFO shown in Figure 6. Figure 9 illustrates the final

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74F433

positions of bits in an expanded 74F433 FIFO resulting

from a 2032-bit serial bit train.

Interlocking Circuitry—Most conventional FIFO designs

provide status signal analogous to IRF and ORE. However,

when these devices are operated in arrays, variations in

unit-to-unit operating speed require external gating to

ensure that a ll devices have completed an operation. The

74F433 incorporates simple but effective 'master/slave'

interlockin g circuitr y to eliminat e the need for external ga t-

ing.

In the 74F433 array of Figure 6, devices 1 and 5 are the

row masters; th e other devices are slave s to the master in

their rows. No slave in a given row initializes its input regis-

ter unti l it has rec eived a LOW on its IES input f rom a row

master or a slave of higher priority.

Similarly, the ORE output s of slaves do not go HIGH until

their inputs have gone HIGH. This interlocking scheme

ensures tha t new input da ta may b e accept ed by the array

when the IRF output of the final slave in that row goes

HIGH and that output data for the array may be extracted

when the ORE output of the final slave in the output row

goes HIGH.

The row mas ter is established by connecting its IES input

to ground, while a slave receives its IES input from the IRF

output of the next- higher priority devic e. When an array of

74F433 FIFOs is initialized with a HIGH on the MR inputs

of all devices, the IRF outputs of all devices are HIGH.

Thus, only the row master receives a LOW on the IES input

during initialization.

Figure 10 is a conceptua l logic diagram of the internal cir-

cuitry that determines master/slave operation. When MR

and I ES are LOW, the master latch is set. When TTS goes

LOW, the initialization flip-flop is set. If the master latch is

HIGH, the input register is immediately initialized and the

initialization flip-flop reset. If the master latch is reset, the

input register is not initialized until IES goes LO W. In ar ray

operation, activating TTS initiates a ripple input register ini-

tialization from the row master to the last slave.

A similar operation takes place for the output register.

Either a TO S or TOP input initiates a load-from-stack oper-

ation and sets the ORE re que st flip- fl op. If the m aste r latch

is set, the last output register flip-flop is set and the ORE

line goes HIGH. If the master latch is reset, the ORE output

is LOW until a Serial Output Enable (OES) input is

received.

FIGURE 5. A Horizontal Expansion Scheme

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74F433

FIGURE 6. A 127 x 16 FIFO Array

FIGURE 7. Serial Data Entry for Array of Figure

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74F433

FIGURE 8. Serial Data Extraction for Array of Figure

FIGURE 9. Final Position of a 2032-Bit Serial Input

FIGURE 10. Conceptual Diagram, Interlocking Circuitry

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74F433

Absolute Maximum Ratings(No te 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under th es e cond iti ons is not im plied.

Note 2: Eith er v oltage lim it or c urrent limit is sufficien t to prot ect input s .

DC Electrical Characteristics

Storage Temperature −65°C to +150°C

Ambient Temperature under Bias −55°C to +125°C

Junction Temperature under Bias −55°C to +150°C

VCC Pin Potential to

Ground Pin −0.5V to +7.0V

Input Voltage (Note 2) −0.5V to +7.0V

Input Current (Note 2) −30 mA to +5.0 mA

Voltage Applied to Output

in HIGH State (with VCC = 0V)

Standard Output −0.5V to VCC

3-STATE Output −0.5V to +5.5V

Current Applied to Output

in LOW State (Max) twice the rated IOL (mA)

Free Air Ambient Temperature 0°C to +70°C

Supply Voltage +4.5V to +5.5V

Symbol Parameter Min Typ Max Units VCC Conditions

VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal

VCD Input Clamp Diode Voltage −1.5 V Min IIN = −18 mA

VOH Output HIGH 10% VCC 2.4

VMin

IOH = 400 µA (ORE, IRF)

Voltage 10% VCC 2.4 IOH = 5.7 mA (Qn, Qs)

5% VCC 2.7 IOH = 400 µA (ORE, IRF)

5% VCC 2.7 IOH = 5.7 mA (Qn, Qs)

VOL Output LOW Voltage 10% VCC 0.50 V Min IOL = 16 mA (Qn, Qs)

IIH Input HIGH Current 5.0 µAMaxV

IN = 2.7V

IBVI Input HIGH Current 7.0 µAMax

VIN = 7.0V

Breakdown Te st

ICEX Output HIGH 50 µAMax

VOUT = VCC

Leakage Current

VID Input Leakage 4.75 V 0.0 IID = 1.9 µA

Test All Other Pins Grounded

IOD Output Leakage 3.75 µA0.0

VIOD = 150 mV

Circuit Current All Other Pins Grounded

IIL Input LOW Current −0.4 mA Max VIN = 0.5V

IOZH Output Leakage Current 50 µAMaxV

OUT = 2.7V (Qn, Qs)

IOZL Output Leakage Current −50 µAMaxV

OUT = 0.5V (Qn, Qs)

IOS Output Short-Circuit Current −20 −130 mA Max VOUT = 0V

ICC Power Supply Current 150 215 mA Max

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74F433

AC Electrical Characteristics

Symbol Parameter

TA = +25°CT

A = 0°C to +70°C

Units Figure

Number

VCC = +5.0V VCC = +5.0V

CL = 50 pF CL = 50 pF

Min Max Min Max

tPHL Propagation Delay, Negative-Going 2.0 17.0 2.0 18.0

ns Figure 11

Figure 12

CPSI t o IRF Output

tPLH Propagation Delay, 9.0 34.0 8.0 38.0

Negative-Going T TS to IRF

tPLH Propagation Delay, Negative-Going 4.0 25.0 3.0 27.0 ns Figure 13

Figure 14

tPHL CPSO to QS Output 5.0 20.0 5.0 21.0

tPLH Propagation Delay, Positive-Going 8.0 35.0 7.0 38.0 ns Figure 15

tPHL TOP to Q0–Q3 Outputs 7.0 30.0 7.0 32.0

tPHL Propagation Delay, 7.0 25.0 6.0 28.0 ns Figure 13

Figure 14

Negative-Going C PS O to ORE

tPHL Propagation Delay, 6.0 26.0 6.0 28.0

ns Figure 15

Negative-Going TOP to ORE

tPLH Propagation Delay, Positive-Going 13.0 48.0 12.0 51.0

TOP to ORE

tPLH Propagation Delay, Negative-Going 13.0 45.0 12.0 50.0 ns Figure 13

Figure 14

TOS to Positive-Going ORE

tPHL Propagation Delay, Positive- 4.0 22.0 4.0 23.0

ns Figure 17

Figure 18

Going PL to Negative-Going IRF

tPLH Propagation Delay, Negative- 7.0 31.0 6.0 35.0

Going PL to Positive-Going IRF

tPLH Propagation Delay, 9.0 38.0 8.0 44.0 ns

Positive-Going OES to ORE

tPLH Propagation Delay Positive-IRF 5.0 25.0 5.0 27.0 ns Figure 18

Going IES to Positive-Going

tPHL Propagation Delay 7.0 28.0 7.0 31.0 ns

MR to ORE

tPLH Propagation Delay 5.0 27.0 5.0 30.0 ns

MR to IRF

tPZH Enable Time 1.0 16.0 1.0 18.0

tPZL OE to Q0–Q31.0 14.0 1.0 16.0

tPHZ Disable Time 1.0 10.0 1.0 12.0

tPLZ OE to Q0–Q31.0 23.0 1.0 30.0

tPZH Enable Time 1.0 10.0 1.0 12.0

tPZL Negative-Going OES to QS1.0 14.0 1.0 15.0

tPHZ Disable Time 1.0 10.0 1.0 12.0

tPLZ Negative-Going O ES to QS1.0 14.0 1.0 16.0

tPZH Enable Time 1.0 35.0 1.0 42.0 ns

tPZL TOS to QS1.0 35.0 1.0 39.0

tDFT Fall-Through Time 0.2 0.9 0.2 1.0 ns Figure 16

tAP Parallel Appearance Time −20.0 −2.0 −20.0 −2.0

ORE to Q0–Q3

tAS Serial Appearance Time −20.0 5.0 −20.0 5.0

ORE to QS

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74F433

AC Operating Requirements

Symbol Parameter

TA = +25°CT

A = 0°C to +70°C

Units Figure

Number

VCC = +5.0V VCC = +5.0V

Min Max Min Max

tS(H) Setup Time, HIGH or LOW 7.0 7.0

ns Figure 11

Figure 12

tS(L) DS to Negative CPSI 7.0 7.0

tH(H) Hold Time, HIGH or LOW 2 .0 2.0

tH(L) DS to CPSI 2.0 2.0

tS(L) Setup Time, LOW TTS to IRF,

0.0 0.0 ns

Figure 11

Figure 12

Figure 17

Figure 18

Serial or Parallel Mode

tS(L) Setup Time, LOW Negative-Going 0.0 0.0 ns Figure 13

Figure 14

ORE to Negative-Going TOS

tS(L) Setup Time, LOW Negative-Going 8.0 9.0

ns Figure 12

IES to CPSI

tS(L) Setup Time, LOW Negative-Going 30.0 33.0

TTS to CPSI

tS(H) Setup Time, HIGH or LOW 0.0 0.0 ns

tS(L) Parallel Inputs to PL 0.0 0.0

tH(H) Hold Time, HIGH or LOW 4 .0 4.0

tH(L) Parallel Inputs to PL 4.0 4.0

tW(H) CPSI Pulse Width 10.0 11.0 ns Figure 11

Figure 12

tW(L) HIGH or LOW 5.0 6.0

tW(H) PL Pulse Width, HIGH 7.0 9.0 ns Figure 17

Figure 18

tW(L) TTS Pulse Width, LOW

7.0 9.0 ns

Figure 11

Figure 12

Figure 13

Figure 14

Serial or Parallel Mode

tW(L) MR Pulse Width, LOW 7.0 9.0 ns Figure 16

tW(H) TOP Pulse Width 14.0 16.0 ns Figure 15

tW(L) HIGH or LOW 7.0 7.0

tW(H) CPSO Pulse Width 14.0 16.0 ns Figure 13

Figure 14

tW(L) HIGH or LOW 7.0 7.0

tREC Recovery Time 8.0 15.0 ns Figure 16

MR to Any Input

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74F433

Timing Waveforms

Conditions: St ac k not f ull, I ES , P L LOW

FIGURE 11. Serial Input, Unexpanded or Master Operation

Conditions: St ac k not f ull, I ES HIGH when initiat ed, PL LOW

FIGURE 12. Serial Input, Expanded Slave Operation

Conditions: Data in stack, TOP HIGH, IES LOW when initiated, OES LOW

FIGURE 13. Serial Output, Unexpanded or Master Operation

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74F433

Timing Waveforms (Continued)

Conditions: Data in stack, TOP HIGH, IES HIGH when initiated

FIGURE 14. Serial Output, Slave Operation

Cond it ions: IES LOW whe n initiated, OE, CPSO LOW; da t a av ailable in stack

FIGURE 15. Parallel Output, 4-Bit Word or Master in Parallel Expansion

Conditions: TTS connected to IRF, TOS connected to ORE, IES, OES, OE, CPSO LOW, TOP HIGH

FIGURE 16. Fall Through Time

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74F433

Timing Waveforms (Continued)

Conditions: St ac k not f ull, I ES LOW when initialized

NOTE A: TTS normally con nect ed to IRF.

NOTE B: If stack is full, IRF will stay LOW.

FIGURE 17. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion

Conditions: St ac k not f ull, device ini ti aliz ed (No te 3) w it h I ES HIGH

Note 3: In it ializ ation requires a m as t er reset to oc c ur after po w er has bee n applied .

FIGURE 18. Parallel Load, Slave Mode

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74F433 First-In First-Out (FIFO) Bu ffer Memory

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

Package Number N24C

Fairchild does no t assume any responsibility for use of any circuitry de scribed, no circuit patent licenses ar e implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

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which, (a) are intended for surgical implant into the

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to perform when properly used in accordance with

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user.

2. A critical compon ent i n any compon ent of a life su pport

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device or system, or to affect its safety or effectiveness.