CMOS SRAMK6T2008V2A, K6T2008U2A Family
Revision 2.0
July 1999
Document Title
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
0.0
1.0
2.0
Remark
Advance
Final
Final
History
Design target
Finalize
Revised
- Add FBGA type package
Draft Data
May 26, 1998
October 8, 1998
July 21, 1999
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
CMOS SRAMK6T2008V2A, K6T2008U2A Family
Revision 2.0
July 1999
256Kx8 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
The K6T2008V2A and K6T2008U2A families are fabricated by
SAMSUNG′s advanced CMOS process technology. The fam-
ily support various operating temperature ranges and have
various package types for user flexibility of system design. The
family also support low data retention voltage for battery back-
up operation with low data retention current.
FEATURES
• Process Technology: TFT
• Organization: 256Kx8
• Power Supply Voltage
K6T2008V2A Family: 3.0V~3.6V
K6T2008U2A Family: 2.7V~3.3V
• Low Data Retention Voltage: 2V(Min)
• Three state output and TTL Compatible
• Package Type: 32-TSOP1-0820F, 32-TSOP1-0813.4F
48-FBGA-6.00x7.00
PIN DESCRIPTION
Name Function Name Function
CS1,CS2Chip Select Inputs I/O1~I/O8Data Inputs/Outputs
OE Output Enable Input Vcc Power
WE Write Enable Input Vss Ground
A0~A17 Address Inputs N.C. No Connection
PRODUCT FAMILY
1. The parameters are tested with 30pF test load
2. K6T2008V2A Family = 35mA
Product Family Operating Temperature Vcc Range Speed Power Dissipation PKG Type
Standby
(ISB1, Max) Operating
(ICC2,Max)
K6T2008V2A-B Commercial(0~70°C) 3.0~3.6V 70/85ns 10µA
30mA2) 32-TSOP1-0820F
32-TSOP1-0813.4F
48-FBGA-6.00x7.00
K6T2008U2A-B 2.7~3.3V 701)/85/100ns
K6T2008V2A-F Industrial(-40~85°C) 3.0~3.6V 701)/85/100ns 15µA
K6T2008U2A-F 2.7~3.3V
FUNCTIONAL BLOCK DIAGRAM
A11
A9
A8
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32-sTSOP1
Type - Forward
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
A2
Precharge circuit.
Memory array
1024 rows
256×8 columns
I/O Circuit
Column select
Clk gen.
Row
select
A0 A1 A17 A6 A5 A3A4
A16
A15
A14
A13
A12
A11
A9
I/O1Data
cont
Data
cont
I/O8
A10
A8
A7
CS1
WE
OE
CS2Control
logic
32-TSOP1
48-FBGA: Top View (Ball Down)
A0 A1 CS2 A3 A6 A8
I/O5 A2 WE A4 A7 I/O1
I/O6 NC A5 I/O2
Vss Vcc
Vcc Vss
I/O7 NC A17 I/O3
I/O8 OE CS1A16 A15 I/O4
A9 A10 A11 A12 A13 A14
1 23456
A
B
C
D
E
F
G
H
CMOS SRAMK6T2008V2A, K6T2008U2A Family
Revision 2.0
July 1999
PRODUCT LIST
Commercial Temperature Products(0~70°C) Industrial Temperature Products(-40~85°C)
Part Name Function Part Name Function
K6T2008V2A-TB70
K6T2008V2A-TB85
K6T2008U2A-TB70
K6T2008U2A-TB85
K6T2008U2A-TB10
K6T2008V2A-YB70
K6T2008V2A-YB85
K6T2008U2A-YB70
K6T2008U2A-YB85
K6T2008U2A-YB10
32-TSOP1 F, 70ns, 3.3V,LL
32-TSOP1 F, 85ns, 3.3V,LL
32-TSOP1 F, 70ns, 3.0V, LL
32-TSOP1 F, 85ns, 3.0V, LL
32-TSOP1 F, 100ns, 3.0V, LL
32-sTSOP1 F, 70ns, 3.3V,LL
32-sTSOP1 F, 85ns, 3.3V,LL
32-sTSOP1 F, 70ns, 3.0V, LL
32-sTSOP1 F, 85ns, 3.0V, LL
32-sTSOP1 F, 100ns, 3.0V, LL
K6T2008V2A-TF70
K6T2008V2A-TF85
K6T2008V2A-TF10
K6T2008U2A-TF70
K6T2008U2A-TF85
K6T2008U2A-TF10
K6T2008V2A-YF70
K6T2008V2A-YF85
K6T2008V2A-YF10
K6T2008U2A-YF70
K6T2008U2A-YF85
K6T2008U2A-YF10
K6T2008V2A-FF70
K6T2008V2A-FF85
K6T2008U2A-FF70
K6T2008U2A-FF85
32-TSOP1 F, 70ns, 3.3V, LL
32-TSOP1 F, 85ns, 3.3V, LL
32-TSOP1 F, 100ns, 3.3V, LL
32-TSOP1 F, 70ns, 3.0V, LL
32-TSOP1 F, 85ns, 3.0V, LL
32-TSOP1 F, 100ns, 3.0V, LL
32-sTSOP1 F, 70ns, 3.3V, LL
32-sTSOP1 F, 85ns, 3.3V, LL
32-sTSOP1 F, 100ns, 3.3V, LL
32-sTSOP1 F, 70ns, 3.0V, LL
32-sTSOP1 F, 85ns, 3.0V, LL
32-sTSOP1 F, 100ns, 3.0V, LL
48-FBGA, 70ns, 3.3V, LL
48-FBGA, 85ns, 3.3V, LL
48-FBGA, 70ns, 3.0V, LL
48-FBGA, 85ns, 3.0V, LL
FUNCTIONAL DESCRIPTION
1. X means don′t care (Must be in high or low states)
CS1CS2OE WE I/O Mode Power
HX1) X1) X1) High-Z Deselected Standby
X1) LX1) X1) High-Z Deselected Standby
LH H H High-Z Output Disabled Active
LHLHDout Read Active
LHX1) LDin Write Active
ABSOLUTE MAXIMUM RATINGS1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Item Symbol Ratings Unit Remark
Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5 V-
Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V-
Power Dissipation PD1.0 W-
Storage temperature TSTG -65 to 150 °C-
Operating Temperature TA0 to 70 °CK6T2008V2A-L, K6T2008U2A-L
-40 to 85 °CK6T2008V2A-P, K6T2008U2A-P
CMOS SRAMK6T2008V2A, K6T2008U2A Family
Revision 2.0
July 1999
RECOMMENDED DC OPERATING CONDITIONS1)
Note:
1. Commercial Product : TA=0 to 70°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : Vcc+2.0V in case of pulse width≤30ns
3. Undershoot : -2.0V in case of pulse width≤30ns
4. Overshoot and undershoot are sampled, not 100% tested.
Item Symbol Product Min Typ Max Unit
Supply voltage Vcc K6T2008V2A Family
K6T2008U2A Family 3.0
2.7 3.3
3.0 3.6
3.3 V
Ground Vss All Family 000V
Input high voltage VIH K6T2008V2A, K6T2008U2A Family 2.2 -Vcc+0.3 V
Input low voltage VIL K6T2008V2A, K6T2008U2A Family -0.33) -0.6 V
CAPACITANCE1) (f=1MHz, TA=25°C)
1. Capacitance is sampled, not 100% tested
Item Symbol Test Condition Min Max Unit
Input capacitance CIN VIN=0V -8pF
Input/Output capacitance CIO VIO=0V -10 pF
DC AND OPERATING CHARACTERISTICS
1. K6T2008V2A Family = 35mA
2. Industrial product = 15µA
Item Symbol Test Conditions Min Typ Max Unit
Input leakage current ILI VIN=Vss to Vcc -1 -1µA
Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 -1µA
Operating power supply current ICC IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL - - 5mA
Average operating current ICC1 Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V, CS2≥Vcc-0.2V, VIN≤0.2V - - 4mA
ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL -25 301) mA
Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current(TTL) ISB CS1=VIH, CS2=VIL, Other inputs=VIH or VIL - - 0.3 mA
Standby Current(CMOS) ISB1 CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V, Other inputs=0~Vcc -0.2 102) µA
CMOS SRAMK6T2008V2A, K6T2008U2A Family
Revision 2.0
July 1999
AC CHARACTERISTICS (K6T2008V2A Family: VCC=3.0~3.6V, K6T2008U2A Family: VCC=2.7~3.3V
Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C)
Parameter List Symbol Speed Bins Units
70ns 85ns 100ns
Min Max Min Max Min Max
Read
Read cycle time tRC 70 -85 -100 -ns
Address access time tAA -70 -85 -100 ns
Chip select to output tCO1, tCO2 -70 -85 -100 ns
Output enable to valid output tOE -35 -40 -50 ns
Chip select to low-Z output tLZ 10 -10 -10 -ns
Output enable to low-Z output tOLZ 5-5-5-ns
Chip disable to high-Z output tHZ 025 025 030 ns
Output disable to high-Z output tOHZ 025 025 030 ns
Output hold from address change tOH 10 -15 -15 -ns
Write
Write cycle time tWC 70 -85 -100 -ns
Chip select to end of write tCW 60 -70 -80 -ns
Address set-up time tAS 0-0-0-ns
Address valid to end of write tAW 60 -70 -80 -ns
Write pulse width tWP 55 -60 -70 -ns
Write recovery time tWR 0-0-0-ns
Write to output high-Z tWHZ 025 030 030 ns
Data to write time overlap tDW 30 -35 -40 -ns
Data hold from write time tDH 0-0-0-ns
End write to output low-Z tOW 5-5-5-ns
CL1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : CL=100pF+1TTL
CL=30pF+1TTL
DATA RETENTION CHARACTERISTICS
1. CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or CS2≤0.2V(CS2 controlled)
2. Industrial Products = 15µA
Item Symbol Test Condition Min Typ Max Unit
Vcc for data retention VDR CS1≥Vcc-0.2V1) 2.0 -3.6 V
Data retention current IDR Vcc=3.0V, CS1≥Vcc-0.2V1) -0.2 102) µA
Data retention set-up time tSDR See data retention waveform 0- - ms
Recovery time tRDR 5- -
CMOS SRAMK6T2008V2A, K6T2008U2A Family
Revision 2.0
July 1999
Address
Data Out Previous Data Valid Data Valid
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tAA
tRC
tOH
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Data Valid
High-Z
CS1
Address
OE
Data out
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
CS2
tOH
tAA
tOLZ
tLZ tOHZ
tHZ(1,2)
tRC
tCO2tOE
tCO1
CMOS SRAMK6T2008V2A, K6T2008U2A Family
Revision 2.0
July 1999
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
Address
CS1
tCW(2) tWR(4)
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
Address
CS1
tWC
tWR(4)
tAS(3)
CS2tCW(2)
tWP(1)
tDW tDH
tOW
tWHZ
Data Undefined
Data Valid
WE
Data in
Data out
tDW tDH
Data Valid
WE
Data in
Data out High-Z High-Z
CS2
tWC
tAW
tAS(3)
tCW(2)
tWP(1)
tAW
CMOS SRAMK6T2008V2A, K6T2008U2A Family
Revision 2.0
July 1999
DATA RETENTION WAVE FORM
CS1 controlled
VCC
3.0/2.7V1)
2.2V
VDR
CS1
GND
Data Retention Mode
CS1≥VCC - 0.2V
tSDR tRDR
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
Address
CS1
tAW
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.
CS2
tCW(2)
WE
Data in Data Valid
Data out High-Z High-Z
tCW(2) tWR(4)
tWP(1)
tDW tDH
tAS(3)
tWC
CS2 controlled
VCC
3.0/2.7V1)
0.4V
VDR
CS2
GND
Data Retention Mode
tSDR tRDR
1. 3.0V for K6T2008V2A Family, 2.7V for K6T2008U2A Family
CS2≤0.2V
CMOS SRAMK6T2008V2A, K6T2008U2A Family
Revision 2.0
July 1999
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
#32
1.00±0.10
0.039±0.004
MAX
8.40
0.331
0.10 MAX
0.004MAX
#1
0.50
( )
0.020
18.40±0.10
0.724±0.004
0.45 ~0.75
0.018 ~0.030
20.00±0.20
0.787±0.008
#17
+0.10
0.15 -0.05
+0.004
0.006
-0.002
0~8°
+0.10
0.20 -0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8.00
0.315
TYP
0.25
0.010
#16
PACKAGE DIMENSIONS Units: millimeter(inch)
32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
1.00±0.10
0.039±0.004
MAX
8.40
0.331
1.10 MAX
0.004 MAX
#1
0.50
( )
0.020
11.80±0.10
0.465±0.004
0.45 ~0.75
0.018 ~0.030
13.40±0.10
0.528±0.008
+0.10
0.15 -0.05
+0.004
0.006
-0.002
0~8°
+0.10
0.20 -0.05
+0.004
0.008
-0.002
0.50
0.0197
0.25
( )
0.010
MIN
0.05
0.002
MAX
1.20
0.047
8.00
0.315
TYP
0.25
0.010
#16
#32
#17
CMOS SRAMK6T2008V2A, K6T2008U2A Family
Revision 2.0
July 1999
PACKAGE DIMENSIONS Units: millimeters
C1/2
654321
A
B
C
D
E
F
G
H
C
B/2
B
C1
B
C
Bottom ViewTop View
D
E2
E1
E
C
Side View
0.85/Typ.
0.25/Typ.
A
Y
Detail A
Min Typ Max
A-0.75 -
B5.90 6.00 6.10
B1 -3.75 -
C6.90 7.00 7.10
C1 -5.25 -
D0.30 0.35 0.40
E-1.10 1.20
E1 -0.85 -
E2 0.20 0.25 0.30
Y- - 0.08
0.50
0.50
B1
#A1
0.30
A1 INDEX MARK
Notes.
1. Bump counts: 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity: 0.08(Max)
48 BALL FINE PITCH BALL GRID ARRAY(6.00X7.00)
