SL74HCT273 Octal D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS The SL74HCT273 is identical in pinout to the LS/ALS273. The SL74HCT273 may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active low. * TTL/NMOS Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A ORDERING INFORMATION SL74HCT273N Plastic SL74HCT273D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE PIN 20=VCC PIN 10 = GND Inputs Output Reset Clock D Q L X X L H H H H L L X no change X no change H L H X = don't care SLS System Logic Semiconductor SL74HCT273 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin 20 mA DC Output Current, per Pin 35 mA ICC DC Supply Current, VCC and GND Pins 75 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 C 260 C VOUT IIN IOUT Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter DC Supply Voltage (Referenced to GND) VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) Min Max Unit 4.5 5.5 V 0 VCC V -55 +125 C 0 500 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor IN74HCT273 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit Test Conditions V 25 C to -55C 85 C 125 C Unit Minimum High-Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT 20 A 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V VIN=VIH or VIL IOUT 4.0 mA 4.5 3.98 3.84 3.7 VIN= VIL or VIH IOUT 20 A 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 VIN= VIL or VIH IOUT 4.0 mA 4.5 0.26 0.33 0.4 Symbol Parameter VIH VOL Maximum Low-Level Output Voltage V IIN Maximum Input Leakage Current VIN=VCC or GND 5.5 0.1 1.0 1.0 A ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0A 5.5 4.0 40 160 A ICC Additional Quiescent Supply Current VIN=2.4 V, Any One Input VIN=VCC or GND, Other Inputs -55C 25C to 125C mA 2.9 2.4 IOUT=0A 5.5 SLS System Logic Semiconductor SL74HCT273 AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V 10%, CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit 25 C to -55C 85C 125C Unit Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 30 24 20 MHz tPLH, t PHL Maximum Propagation Delay, Clock to Q (Figures 1 and 4) 25 28 35 ns tPHL Maximum Propagation Delay , Reset to Q (Figures 2 and 4) 25 28 35 ns Maximum Output Transition Time, Any Output (Figures 1 and 4) 18 20 22 ns Maximum Input Capacitance 10 10 10 pF Power Dis sipation Capacitance (Per Gate) Typical @25C,VCC=5.0 V Symbol fmax tTLH, t THL CIN CPD Parameter Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 30 pF TIMING REQUIREMENTS (VCC =5.0 V 10%, CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol Parameter 25 C to -55C 85C 125C Unit tSU Minimum Setup Time, Data to Clock (Figure 3) 10 12 15 ns th Minimum Hold Time, Clock to Data (Figure 3) 3.0 3.0 3.0 ns trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 5.0 5.0 5.0 ns tw Minimum Pulse Width, Clock (Figure 1) 12 15 18 ns tw Minimum Pulse Width, Reset (Figure 2) 12 15 18 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 500 500 500 ns SLS System Logic Semiconductor IN74HCT273 Figure 1. Switching waveforms Figure 2. Switching waveforms Figure 3. Switching waveforms Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor