IDT71V256SA10PZI - Integrated Device Technology, Inc.

FEBRUARY 2001

DSC-3101/06

1

Features

◆◆

◆Ideal for high-performance processor secondary cache

◆◆

◆Commercial (0°C to +70°C) and Industrial (–40°C to +85°C)

temperature range options

◆◆

◆Fast access times:

– Commercial and Industrial: 10/12/15/20ns

◆◆

◆Low standby current (maximum):

– 2mA full standby

◆◆

◆Small packages for space-efficient layouts:

– 28-pin 300 mil SOJ

– 28-pin TSOP Type I

◆◆

◆Produced with advanced high-performance CMOS

technology

◆◆

◆Inputs and outputs are LVTTL-compatible

◆◆

◆Single 3.3V(±0.3V) power supply

Description

The IDT71V256SA is a 262,144-bit high-speed static RAM organized

as 32K x 8. It is fabricated using IDT’s high-performance, high-reliability

CMOS technology.

The IDT71V256SA has outstanding low power characteristics while

at the same time maintaining very high performance. Address access

times of as fast as 10ns are ideal for 3.3V secondary cache in 3.3V

desktop designs.

When power management logic puts the IDT71V256SA in standby

mode, its very low power characteristics contribute to extended battery life.

By taking CS HIGH, the SRAM will automatically go to a low power standby

mode and will remain in standby as long as CS remains HIGH. Further-

more, under full standby mode (CS at CMOS level, f=0), power consump-

tion is guaranteed to always be less than 6.6mW and typically will be much

smaller.

The IDT71V256SA is packaged in a 28-pin 300 mil SOJ and a 28-pin

300 mil TSOP Type I.

Functional Block Diagram

A0

ADDRESS

DECODER 262,144 BIT

MEMORY ARRAY

I/O CONTROL

3101 drw 01

INPUT

DATA

CIRCUIT

WE

CS

VCC

GND

A14

I/O0

I/O7

CONTROL

CIRCUIT

OE ,

Lower Power

3.3V CMOS Fast SRAM

256K (32K x 8-Bit)

IDT71V256SA

2

IDT71V256SA

3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage

Pin Configurations

Absolute Maximum Ratings(1)

Capacitance

(TA = +25°C, f = 1.0MHz, SOJ package)

Truth Table(1)

DIP/SOJ

Top View

Pin Descriptions

TSOP

Top View

3101 drw 02

5

6

7

8

9

10

11

12

A12

1

2

3

424

23

22

21

20

19

18

17

SO28-5

13

14

28

27

26

25

A7

A6

A5

A4

A3

A2

A1

A0

I/O0

I/O1

VCC

WE

A8

A9

A11

OE

A10

CS

I/O7

16

15

I/O2

GND

I/O6

I/O5

I/O4

I/O3

A14

A13

,

3101 drw 03

22

23

24

25

26

27

28

1

2

3

4

5

7

6

21

20

19

18

17

16

15

14

13

12

11

10

9

8

A10

CS

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

A0

A1

A2

SO28-8

OE

A11

A9

A8

A13

A14

A7

A6

A5

A4

A3

A12

WE

VCC

,

Name

Description

A0 - A14 Addresses

I/O0 - I/O7Data Inp ut/ Outp ut

CS Chip Se lect

WE Write Enab le

OE Outp ut Enab le

GND Ground

VCC Power

3 101 tbl 01

NOTE:

1 . H = VIH, L = VIL, X = Don’t Care

WE CS OE I/O Function

X H X Hig h-Z Stand by (ISB)

XV

HC X Hig h-Z Stand by (ISB1)

H L H High-Z Output Disable

HLLD

OUT Read

LLXD

IN Write

3101 tbl 02

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect

reliability.

2. Input, Output, and I/O terminals; 4.6V maximum.

Symbol

Rating

Com'l.

Unit

VCC Supply Voltage

Re lativ e to GND -0.5 to +4.6 V

VTERM(2) Te rmi nal Vo ltage

Re lativ e to GND -0.5 to VCC+0.5 V

TBIAS Te mpe rature Und e r Bi as -55 to +125 oC

TSTG Storag e Temp e rature -55 to +125 oC

PTPo we r Di s si p atio n 1. 0 W

IOUT DC Outp ut Curre nt 50 mA

3 101 t bl 03

NOTE:

1. This parameter is determined by device characterization, but is not production

tested.

Symbol Parameter

(1)

Conditions Max. Unit

CIN Input Cap ac itanc e V IN = 3dV 6 pF

COUT Output C ap ac itanc e V OUT = 3dV 7 pF

3101 tbl 04

Grade Temperature GND Vcc

Commercial 0

O

C to + 70

O

C0V 3.3V ± 0.3V

Industrial -40

O

C to + 85

O

C0V 3.3V ± 0.3V

3 101 t bl 05

6.42

IDT71V256SA

3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

3

Recommended DC Operating

Conditions

NOTE:

1. VIL (min.) = –2.0V for pulse width less than 5ns, once per cycle.

Symbol

Parameter

Min.

Typ.

Max.

Unit

VCC Sup p ly Vo ltag e 3.0 3.3 3.6 V

GND Ground 0 0 0 V

VIH Inp ut Hi g h Vo ltag e - Inp uts 2. 0 ____ 5.0 V

VIH Inp ut Hig h Vo l tag e - I/ O 2. 0 ____ VCC +0.3 V

VIL Input Lo w Voltage -0.3(1) ____ 0.8 V

3 101 t bl 06

DC Electrical Characteristics

(VCC = 3.3V± 0.3V)

DC Electrical Characteristics(1)

(VCC = 3.3V ± 0.3V, VLC = 0.2V, VHC = VCC - 0.2V, Commercial and Industrial Temperture Ranges)

NOTES:

1. All values are maximum guaranteed values.

2. fMAX = 1/tRC, only address inputs cycling at fMAX; f = 0 means that no inputs are cycling.

Symbol

Parameter

71V256SA10

71V256SA12

71V256SA15

71V256SA20

Unit

ICC Dy nam ic Op e rating Curre nt CS < VIL, Outputs

Ope n, VCC = Max., f = fMAX(2) 100 90 85 85 mA

ISB Stand b y P owe r Sup p ly Curre nt (TTL Lev el)

CS = VIH, VCC = Max., O utp uts Ope n , f = fMAX(2) 20 20 20 20 mA

ISB1 F ull Stand b y Po wer Sup ply Curre nt (CMOS Le ve l)

CS > VHC, VCC = Max., Outputs Open , f = 0(2),

VIN < VLC or VIN > VHC

2222mA

3101 t bl 07

Symbol Param eter Test Conditions

IDT71V256SA

UnitMin. Typ. Max.

|ILI| Input Leak age Current VCC = Max., VIN = GND to VCC

___

2µA

|ILO| Outp ut Le ak age Curre nt VCC = Max., CS = VIH, VOUT = GND to V CC

___

2µA

VOL Outp ut Lo w Voltag e IOL = 8mA, VCC = Min.

___

0.4 V

VOH Outp ut Hig h Vo ltag e IOH = -4mA, VCC = Min. 2.4

___

V

3101 t bl 08

4

IDT71V256SA

3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

(VCC = 3.3V ± 0.3V, Commercial and Industrial Temperature Ranges)

Figure 1. AC Test Load Figure 2. AC Test Load

(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)

*Includes scope and jig capacitances

AC Test Conditions

3101 drw 04

320Ω

30pF*

350Ω

DATAOUT

3.3V

,

3101 drw 05

320Ω

5pF*

350Ω

DATAOUT

3.3V

,

Inp ut P ul s e Lev e ls

Inp ut Ris e / Fal l Tim e s

Inp ut Timi ng Re fe re nce Le v els

Outp ut Re fere nce Lev els

AC Test Load

GND to 3.0V

3ns

1.5V

S ee F igures 1 and 2

3 101 t bl 09

NOTE:

1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.

Symbol

Parameter

71V256SA10

71V256SA12

71V256SA15

71V256SA20

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Read Cycl e

t

RC

Re ad Cyc le Time

10

____

12

____

15

____

20

____

ns

t

AA

Address Access Time

____

10

____

12

____

15

____

20

ns

t

ACS

Chip Select Access Time

____

10

____

12

____

15

____

20

ns

t

CLZ(1)

Chip S elect to Output in Low-Z

5

____

5

____

5

____

5

____

ns

t

CHZ(1)

Chip S ele ct to Output in Hig h-Z

0

8

0

8

0

9

0

10

ns

t

OE

Output Ena bl e to Outp ut Val id

____

6

____

6

____

7

____

8

ns

t

OLZ(1)

Outp ut E nab le to Outp ut in Lo w-Z

3

____

3

____

0

____

0

____

ns

t

OHZ(1)

Outp ut Dis ab le to O utp ut i n Hig h-Z

2

6

2

6

0

7

0

8

ns

t

OH

Output Hold from Address Change

3

____

3

____

3

____

3

____

ns

Wri te Cycl e

t

WC

Write Cycle Time

10

____

12

____

15

____

20

____

ns

t

AW

Address Valid to End-of-Write

9

____

9

____

10

____

15

____

ns

t

CW

Chip Select to End-of-Write

9

____

9

____

10

____

15

____

ns

t

AS

Address Set-up Time

0

____

0

____

0

____

0

____

ns

t

WP

Write Pulse Width

9

____

9

____

10

____

15

____

ns

t

WR

Write Recovery Time

0

____

0

____

0

____

0

____

ns

t

DW

Da ta to Wri te Ti me Ov e rlap

6

____

6

____

7

____

8

____

ns

t

DH

Data Hold from Write Time

0

____

0

____

0

____

0

____

ns

t

OW(1)

Output Active from End-of-Write

4

____

4

____

4

____

4

____

ns

t

WHZ(1)

Write E nab le to Outp ut in High-Z

1

8

1

8

1

9

1

10

ns

3 101 t bl 10

6.42

IDT71V256SA

3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

5

Timing Waveform of Read Cycle No. 1(1)

NOTES:

1. WE is HIGH for Read cycle.

2. Transition is measured ±200mV from steady state.

ADDRESS

CS

DATAOUT

OE

3101 drw 06

tRC

tAA tOH

tACS

tCLZ tCHZ (2)

tOE

tOLZ

(2)

(2) tOHZ (2)

DATA VALID ,

Timing Waveform of Read Cycle No. 2(1,2,4)

Timing Waveform of Read Cycle No. 3(1,3,4)

NOTES:

1. WE is HIGH for Read cycle.

2. Device is continuously selected, CS is LOW.

3. Address valid prior to or coincident with CS transition LOW.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

DATAOUT

CS

3101 drw 08

tACS

(5)

tCLZ (5)

CHZ

t

DATA VALID ,

ADDRESS

DATAOUT

3101 drw 07

tRC

tAA tOH

tOH

DATA VALIDPREVIOUS DATA VALID ,

6

IDT71V256SA

3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,4)

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the

spectified tWP.

CS

DATAIN

ADDRESS

WE

tWR

3101 drw 10

tAW

tDW

tWC

tCW

tDH

AS

t t

(5)

DATA VALID ,

NOTES:

1. A write occurs during the overlap of a LOW CS and a LOW WE.

2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

3 . During this period, I/O pins are in the output state so that the input signals must not be applied.

4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the

spectified tWP.

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4,6)

CS

DATAIN

ADDRESS

WE

DATAOUT

OE

3101 drw 09

tAW

tWR

tDW

tWC

tWP

tDH

tWHZ tOW

(3)

(6)

tAS

(5)

(3)

tOHZ (5)

DATA VALID

(5)

,

6.42

IDT71V256SA

3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

7

Ordering Information  Commercial and Industrial

300 mil SOJ (SO28-5)

TSOP Type I (SO28-8)

SA

Power

XX

Speed

X

Package

X

Process/

Temperature

Range

Blank

ICommercial (0°C to +70°C)

Industrial (–40°C to +85°C)

Y

PZ

IDT

Speed in nanoseconds

3101 drw 11

71V256

Device

Type

* Available in SOJ package only.

8

IDT71V256SA

3.3V CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 sramhelp@idt.com

Santa Clara, CA 95054 fax:408-492-8674 800 544-7726, x4033

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History

1/7/00 Updated to new format

Pg. 1, 3, 4, 7 Expanded Industrial Temperature offerings

Pg. 1, 2, 7 Removed 28-pin 300 mil plastic DIP package offering

Pg. 6 Removed Note No. 1 from Write Cycle No. 1 diagram; renumbered notes and footnotes

Pg. 7 Revised Ordering Information

Pg. 8 Added Datasheet Document History

08/09/00 Not recommended for new designs

02/01/01 Removed "Not recommended for new designs"