ACFL-5212T
Automotive R2CouplerTM Wide Operating Temperature 20kBd Digital
Optocoupler Congurable as Low Power, Low Leakage Phototransistor
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD. The components
featured in this datasheet are not to be used in military or aerospace applications or environments.
Description
The ACFL-5212T is an automotive grade dual channel, bi-
directional, high CMR, 20kBd digital optocoupler, congu-
rable as a low power, low leakage phototransistor, spe-
cically for use in automotive applications. The stretched
SO-12 package outline is designed to be compatible with
standard surface mount processes and occupies the same
land area as the single channel equivalent, ACPL-K49T, in
stretched SO8 package.
This digital optocoupler uses an insulating layer between
the light emitting diode and an integrated photo detector
to provide electrical insulation between input and output.
Separate connections for the photodiode bias and output
transistor collector increase the speed up to a hundred
times over that of a conventional photo-transistor coupler
by reducing the base-collector capacitance.
Each channel is also galvanically isolated from each other
with no cross-talk.
Avago R2Coupler provides reinforced insulation and reli-
ability that delivers safe signal isolation critical in automo-
tive and high temperature industrial applications.
Functional Diagram
Features
• Qualied to AEC Q100 Grade 1 Guidelines
• Wide Temperature Range: -40°C to +125°C
• Low LED Drive Current: 4mA (typ)
• Low Power, Low Leakage Phototransistor in a “4-pin
Conguration” (I(CEO) < 5µA)
• 30 kV/µs High Common-Mode Rejection at VCM = 1500
V (typ)
• Low Propagation Delay: 20µs (max)
• Compact, Auto-Insertable Stretched SO12 Packages
• Worldwide Safety Approval:
- UL 1577 recognized, 5kVRMS/1 min.
- CSA Component Acceptance Notice#5A
- IEC/EN/DIN EN 60747-5-5
Applications
• Automotive Low Speed Digital Signal Isolation Interface
• Inverter Fault Feedback Signal Isolation
• Switching Power Supplies Feedback Circuit
Truth Table
LED VO
ON LOW
OFF HIGH
Note: The connection of a 1 μF bypass
capacitor between pins 1 and 3 and
pins 8 and 10 is recommended.
1
2
3
4
5
6
VCC1
VOUT1
GND1
AN2
CA2
CA2
12
11
10
9
8
7
VCC2
VOUT2
GND2
AN1
CA1
GND2
1
2
3
4
5
6
12
11
10
9
8
7
VCC2
VOUT2
GND2
AN1
CA1
GND2
VCC1
VOUT1
GND1
AN2
CA2
CA2
Note: Pins 1 and 2 and pins 9 and 10 are externally
shorted for 4-pin conguration. Do not connect
bypass capacitors in this conguration.
2
Pin Description
Pin No. Pin Name Description Pin No. Pin Name Description
1 VCC1 Primary Side Power Supply 7 GND2 Secondary Side Ground
2 VOUT1 Output 1 8 GND2 Secondary Side Ground
3 GND1 Primary Side Ground 9 VOUT2 Output 2
4 AN2 Anode 2 10 VCC2 Secondary Side Power Supply
5 CA2 Cathode 2 11 AN1 Anode 1
6 CA2 Cathode 2 12 CA1 Cathode 1
Ordering Information
Part number
Option
(RoHS Compliant) Package
Surface
Mount
Tape
& Reel
UL 5000 Vrms/
1 Minute rating
IEC/EN/DIN
EN 60747-5-5 Quantity
ACFL-5212T -000E Stretched
SO-12
X X 80 per tube
-060E X X X 80 per tube
-500E X X X 1000 per reel
-560E X X X X 1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACFL-5212T-560E to order product of SSO-12 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
3
Package Outline Drawing
12-Lead Surface Mount
Dimensions in inches (millimeters)
Lead coplanarity = 0.004 inches (0.1mm)
Recommended Pb-Free IR Prole
Recommended reow condition as per JEDEC Standard, J-STD-020 (latest revision).
Note: Non-halide ux should be used
LAND PATTERN RECOMMENDATION
0.080 (2.030)
0.458 (11.630)
0.020 (0.500)
0.015
(0.381)
0.125 ± 0.005
(3.180 ± 0.127)
7°
0.015
(0.381)
0.032
(0.800)
1 2 3 4 5 6
12 11 10 9 8 7
5212T
YYWW
EE
0.230
( 5.842
0.295
( 7.493
TYPE NUMBER
DATECODE
EXTENDED
DATECODE FOR
LOT TRACKING
+ 0.005
− 0
+ 0.127
− 0 )
+ 0.005
− 0
+ 0.127
− 0 )
45°
0.326 ± 0.010
(8.284 ± 0.254)
0.029 ± 0.004
(0.731 ± 0.100)
0.408 ± 0.010
(10.363 ± 0.250)
0.010 ± 0.002
(0.254 ± 0.050)
7°
0.008 ± 0.004
(0.200 ± 0.100)
0.063 ± 0.005
(1.590 ± 0.127)
RoHS-COMPLIANCE
INDICATOR
0° to 7°
4
Regulatory Information
The ACFL-5212T is approved by the following organizations:
UL Approved under UL 1577, component recognition program up to VISO = 5kVRMS
CSA Approved under CSA Component Acceptance Notice #5A
IEC/EN/DIN EN 60747-5-5 Approved under IEC/EN/DIN EN 60747-5-5
Insulation and Safety Related Specications
Parameter Symbol ACFL-5212T Units Conditions
Minimum External Air Gap
(Clearance)
L(101) 8.3 mm Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking
(Creepage)
L(102) 8.5 mm Measured from input terminals to output terminals,
shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
0.08 mm Through insulation distance conductor to conductor,
usually the straight line distance thickness between
the emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
CTI 175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group (DIN VDE0109) IIIa Material Group (DIN VDE 0109)
IEC / EN / DIN EN 60747-5-5 Insulation Related Characteristic (Option 060E and 560E)
Description Symbol Characteristic Units
Installation classication per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 600 V rms
for rated mains voltage < 1000 V rms
I-III
I-III
Climatic Classication 40/125/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 1140 VPEAK
Input to Output Test Voltage, Method b
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC
VPR 2137 VPEAK
Input to Output Test Voltage, Method a
VIORM x 1.6 = VPR, Type and sample test, tm = 10 sec, Partial Discharge < 5 pC
VPR 1824 VPEAK
Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec) VIOTM 6000 VPEAK
Safety Limiting Values (Maximum values allowed in the event of a failure)
Case Temperature
Input Current
Output Power
TS
IS,INPUT
PS,OUTPUT
175
230
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V RS109W
5
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Condition
Storage Temperature TS-55 150 °C
Operating Temperature TA-40 125 °C
Junction Temperature TJ150 °C
Lead Soldering Cycle Temperature 260 °C
Time 10 s
Average Forward Input Current IF(avg) 20 mA
Peak Forward Input Current
(50% duty cycle, 1ms pulse width)
IF(peak) 40 mA
Peak Transient Input Current
(≤1µs pulse width, 300ps)
IF(trans) 100 mA
Reversed Input Voltage VR5 V
Input Power Dissipation PIN 30 mW
Output Power Dissipation PO100 mW
Average Output Current IO8 mA
Peak Output Current IO(pk) 16 mA
Supply Voltage VCC1/VCC2 -0.5 30 V
Output Voltage VOUT1/VOUT2 -0.5 20 V
Solder Reow Temperature Prole See Reow Temperature Prole
Recommended Operating Conditions
Parameter Symbol Min. Max. Units Note
Supply Voltages VCC1/VCC2 20.0 V
Operating Temperature TA-40 125 °C
6
Electrical Specications (DC) for 5-Pin Conguration
Over recommended operating conditions, unless otherwise specied. All typical specications are at TA=25°C, VCC= 5V.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Current Transfer Ratio CTR 32 65 100 % TA=25°C, VCC=4.5V, VO=0.5V,
IF=10mA
1,2,3 1
24 65 VCC=4.5V, VO=0.5V, IF=10mA
65 110 150 TA=25ºC, VCC=4.5V, VO=0.5V,
IF=4mA
1,2, 3 1
50 110 VCC=4.5V, VO=0.5V, IF=4mA
Logic Low Output Voltage VOL 0.1 0.5 V TA=25ºC, IF=10mA, VCC=4.5V,
IO=2.4mA,
3
0.1 0.5 IF=4mA, VCC=4.5V, IO=2.0mA,
Logic High Output Current IOH 0.003 0.5 µATA=25ºC, VO=VCC=5.5V, IF=0mA 7
0.01 5 VO=VCC=20V, IF=0mA
Logic Low Supply Current ICCL 35 100 µAIF=4mA, VO=open, VCC=20V
Logic High Supply Current ICCH 0.02 1 µA TA=25°C, IF=0mA, VO=open,
VCC=20V
2.5 µAIF=0mA, VO=open, VCC=20V
Input Forward Voltage VF1.2 1.5 1.8 V IF=4mA 6
Input Reversed Breakdown
Voltage
BVR5 V IR=10µA
Temperature Coecient
of Forward Voltage
ΔV/ΔTA-1.5 mV/°CIF=10mA
Input Capacitance CIN 90 pF F=1MHz, VF=0
Switching Specications (AC) for 5-Pin Conguration
Over recommended operating conditions, unless otherwise specied. All typical specications are at TA=25°C, VCC= 5V.
Parameter Sym. Min. Typ. Max. Units Conditions Fig. Note
Propagation Delay Time
to Logic Low at Output
tPHL 20 μs Pulse: f=10kHz, Duty cycle = 50%,
IF = 4mA, VCC = 5.0 V, RL = 8.2kW,
CL = 15pF VTHHL=1.5V
2
Propagation Delay Time
to Logic High at Output
tPLH 20 μs Pulse: f=10kHz, Duty cycle = 50%,
IF = 4mA, VCC=5.0 V, RL=8.2kW,
CL=15pF, VTHLH=2.0V
2
Common Mode Transient
Immunity at Logic High Output
|CMH| 15 30 kV/ μs IF=0mA VCM=1500Vp-p,
TA=25°C,
RL=1.9kΩ
3
Common Mode Transient
Immunity at Logic Low Output
|CML| 15 30 kV/ μs IF=10mA
Common Mode Transient
Immunity at Logic Low Output
|CML| 15 kV/ μs IF=4mA VCM=1500Vp-p,
TA=25°C,
RL=8.2kΩ
7
Electrical Specications (DC) for 4-Pin Conguration
Over recommended operating conditions, unless otherwise specied. All typical specications are at TA=25°C, VCC= 5V.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Current Transfer Ratio CTR 120 % TA=25°C, VCC=VO=5V, IF=5mA 4 5, 8
70 130 250 TA=25°C, VCC=VO=5V, IF=4mA
Current Transfer Ratio CTR(Sat) 24 60 IF=10mA, VCC=VO=0.5V 5 5, 8
35 110 IF=4mA, VCC=VO=0.5V
Logic Low Output Voltage VOL 0.1 0.5 V IF=10mA, VCC=4.5V, IO=2.4mA, 5 8
0.1 0.4 IF=4mA, VCC=4.5V, IO=2.4mA,
O-State Current I(CEO) 4x10-
4
5µAVO=VCC=20V, IF=0mA 8 8
Input Forward Voltage VF1.2 1.5 1.8 V IF=4mA 6
Input Reversed Breakdown
Voltage
BVR5 V IR=10µA
Temperature Coecient
of Forward Voltage
ΔV/ΔTA-1.5 mV/oC IF=10mA
Input Capacitance CIN 90 pF F=1MHz, VF=0
Output Capacitance CCE 35 pF F=1MHz, VF=0, VO=VCC =0V
Switching Specications (AC) for 4-Pin Conguration
Over recommended operating conditions, unless otherwise specied. All typical specications are at TA=25°C, VCC= 5V.
Parameter Sym. Min. Typ. Max. Units Conditions Fig. Note
Propagation Delay Time
to Logic Low at Output
tPHL 2 100 μs Pulse: f=1kHz, Duty cycle = 50%,
IF = 4mA, VCC = 5.0 V, RL = 8.2kW,
CL = 15pF, VTHHL=1.5V
8
Propagation Delay Time
to Logic High at Output
tPLH 19 100 μs Pulse: f=1kHz, Duty cycle = 50%,
IF = 4mA, VCC = 5.0 V, RL = 8.2kW,
CL = 15pF, VTHLH=2.0V
8
Common Mode Transient
Immunity at Logic High Output
|CMH| 15 30 kV/ μs IF=0mA VCM=1500Vp-p, TA=25°C
RL=8.2kΩ
8, 9
Common Mode Transient
Immunity at Logic Low Output
|CML| 15 30 kV/ μs IF=4mA VCM=1500Vp-p, TA=25°C
RL=8.2kΩ
Package Characteristics
All Typical at TA = 25°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary
Withstand Voltage*
VISO 5000 VRMS RH ≤ 50%, t = 1 min;
TA = 25°C
6, 7
Input-Output Resistance RI-O 1014 Ω VI-O = 500 Vdc 6
Input-Output Capacitance CI-O 0.6 pF f = 1 MHz; VI-O = 0 VDC 6
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating.
Notes:
1. Current Transfer Ratio in percent is dened as the ratio of output collector current, IO, to the forward LED input current, IF, times 100.
2. Use of 1µF bypass capacitors connected between pins 1 and 3 and pins 8 and 10 for 5-pin conguration.
3. Common transient immunity in a Logic High level is the maximum tolerable (positive) dVCM/dt on the rising edge of the common mode pulse, VCM,
to assure that the ouput will remain in a Logic High state (i.e., VO > 2.0V). Common mode transient immunity in a Logic Low level is the maximum
tolerable (negative) dVCM/dt on the falling edge of the common mode pulse signal, VCM to assure that the output will remain in a Logic Low state
(i.e., VO < 0.8V).
4. Device considered a two terminal device: pins 1 to 6 shorted together, and pins 7 to 12 shorted together.
5. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 6000VRMS for 1 second.
8
Typical Performance Plots
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 1 10 100
NORMALIZED CURRENT TRANSFER RATIO
IF - INPUT CURRENT - mA
0.6
0.7
0.8
0.9
1.0
1.1
-40 -20 0 20 40 60 80 100 120 140
NORMALIZED CURRENT TRANSFER RATIO
TA - TEMPERATURE - °C
IF=10mA
IF=4mA
0
2
4
6
8
10
12
14
16
0.0 0.2 0.4 0.6 0.8 1.0
IO - OUTPUT CURRENT - mA
VO - OUTPUT VOLTAGE - V
0
5
10
15
20
25
30
35
0 5 10 15 20
IO - OUTPUT CURRENT - mA
VO - OUTPUT VOLTAGE - V
0
2
4
6
8
10
12
14
16
0.0 0.2 0.4 0.6 0.8 1.0
IO - OUTPUT CURRENT - mA
VO - OUTPUT VOLTAGE - V
0.1
1.0
10.0
1.1 1.2 1.3 1.4 1.5 1.6 1.7
IF - FORWARD CURRENT - mA
VF - FORWARD VOLTAGE - V
Temp=-40°C
Temp=25°C
Temp=125°C
VO=0.4V, VCC=5V,
Normalized: TA=25°C
IF=40mA
IF=35mA
IF=30mA
IF=25mA
IF=20mA
IF=15mA
IF=10mA
IF=5mA
IF=4mA
IF=40mA
IF=35mA
IF=30mA
IF=25mA
IF=20mA
IF=15mA
IF=10mA
IF=5mA
IF=4mA
IF=40mA
IF=35mA
IF=30mA
IF=25mA
IF=20mA
IF=15mA
IF=10mA
IF=5mA
IF=4mA
VO=0.4V, VCC=5V, TA=25°C
Normalized: IF=4mA
Figure 1. Current Transfer Ratio vs. Input Current Figure 2. Normalized Current Transfer Ratio vs. Temperature
Figure 3. Typical Low Level Output Current vs Output Voltage Figure 4. Output Current vs Output Voltage (4-Pin Conguration)
Figure 5. Typical Low Level Output Current vs Output Voltage (4-Pin Congu-
ration)
Figure 6. Typical Input Current vs Forward Voltage
9
Figure 7. Typical High Level Output Current vs Temperature Figure 8. Typical O-State Current vs Temperature (4-Pin Conguration)
Test Circuits
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
25 50 75 100 125
IOH - LOGIC HIGH OUTPUT CURENT - uA
TA - TEMPERATURE - °C
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
25 50 75 100 125
ICEO - OFF-STATE CURENT - uA
TA - TEMPERATURE - °C
VCC=15V
VCC=12V
VCC=3.3V
VCC=5V
VIN
0
VO
2V
VOL
1.5V
tPHL tPLH
OUTPUT
MONITORING
NODE
PULSE
GENERATOR
ZO=50 Ω
tr=tf=5ns
INPUT
MONITORING
NODE
RMONITOR
=100 Ω
VCC
CL*
GND1
GND2
1
2
3
4
5
6
12
11
10
9
8
7
RL
*CL IS APPROXIMATELY 15pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE
IF
VIN
0
VO
2V
VOL
1.5V
tPHL tPLH
INPUT
MONITORING
NODE
100Ω
VCC
CL*
GND1
GND2
RL
OUTPUT
MONITORING
NODE
1
2
3
4
5
6
12
11
10
9
8
7
PULSE
GENERATOR
ZO=50 Ω
tr=tf=5ns
*CL IS APPROXIMATELY 15pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE
1uF
Figure 9. Switching Test Circuit (5-pin Conguration)
Figure 10. Switching Test Circuit (4-pin Conguration)
10
trtf
1500V
0V 10%
90% 90%
SWITCH AT A: IF = 0mA
SWITCH AT B: IF = 4mA
5V
VOL
10%
VCM
VO
VO
trtf
1500V
0V 10%
90% 90%
SWITCH AT A: IF = 0mA
SWITCH AT B: IF = 10mA
5V
VOL
10%
OUTPUT
MONITORING
NODE
1µF
BYPASS
CAPACITOR
B
A
HIGH VOLTAGE PULSE
VCM=1500V
+ -
1
2
3
4
5
6
12
11
10
9
8
7
IFVCC
RL
VCM
VO
RLIMIT
VIN
VO
OUTPUT
MONITORING
NODE
VCC
IF
B
A
VIN
+ -
RL
RLIMIT
HIGH VOLTAGE PULSE
VCM=1500V
1
2
3
4
5
6
12
11
10
9
8
7
Figure 12. Test Circuit for Transient Immunity and Typical Waveforms (4-Pin Conguration)
Figure 11. Test Circuit for Transient Immunity and Typical Waveforms (5-Pin Conguration)
11
Thermal Resistance Measurement
The diagram of ACFL-5212T for measurement is shown in Figure 13. This is a multi-chip package with four heat sources,
the eect of heating of one die due to the adjacent dice are considered by applying the theory of linear superposition.
Here, one die is heated rst and the temperatures of all the dice are recorded after thermal equilibrium is reached. Then,
the 2nd die is heated and all the dice temperatures are recorded and so on until the 4th die is heated. With the known
ambient temperature, the die junction temperature and power dissipation, the thermal resistance can be calculated.
The thermal resistance calculation can be cast in matrix form. This yields a 4 by 4 matrix for our case of two heat sources.
Figure 13. Diagram of ACFL-5212T for measurement
R11: Thermal Resistance of Die1 due to heating of Die1 (˚C/W)
R12: Thermal Resistance of Die1 due to heating of Die2 (˚C/W)
R13: Thermal Resistance of Die1 due to heating of Die3 (˚C/W)
R14: Thermal Resistance of Die1 due to heating of Die4 (˚C/W)
R21: Thermal Resistance of Die2 due to heating of Die1 (˚C/W)
R22: Thermal Resistance of Die2 due to heating of Die2 (˚C/W)
R23: Thermal Resistance of Die2 due to heating of Die3 (˚C/W)
R24: Thermal Resistance of Die2 due to heating of Die4 (˚C/W)
R31: Thermal Resistance of Die3 due to heating of Die1 (˚C/W)
R32: Thermal Resistance of Die3 due to heating of Die2 (˚C/W)
R33: Thermal Resistance of Die3 due to heating of Die3 (˚C/W)
R34: Thermal Resistance of Die3 due to heating of Die4 (˚C/W)
R41: Thermal Resistance of Die4 due to heating of Die1 (˚C/W)
R42: Thermal Resistance of Die4 due to heating of Die2 (˚C/W)
R43: Thermal Resistance of Die4 due to heating of Die3 (˚C/W)
R44: Thermal Resistance of Die4 due to heating of Die4 (˚C/W)
P1: Power dissipation of Die1 (W)
P2: Power dissipation of Die2 (W)
P3: Power dissipation of Die3 (W)
P4: Power dissipation of Die4 (W)
T1: Junction temperature of Die1 due to heat from all dice (°C)
T2: Junction temperature of Die2 due to heat from all dice (°C)
T3: Junction temperature of Die3 due to heat from all dice (°C)
T4: Junction temperature of Die4 due to heat from all dice (°C)
Ta: Ambient temperature.
∆T1: Temperature dierence between Die1 junction and ambient (°C)
∆T2: Temperature deference between Die2 junction and ambient (°C)
∆T3: Temperature dierence between Die3 junction and ambient (°C)
∆T4: Temperature deference between Die4 junction and ambient (°C)
T1 = (R11 x P1 + R12 x P2 + R13 x P3 + R14 x P4 ) + Ta -- (1)
T2 = (R21 x P1 + R22 x P2 + R23 x P3 + R24 x P4) + Ta -- (2)
T3 = (R31 x P1 + R32 x P2 + R33 x P3 + R34 x P4) + Ta -- (3)
T4= (R41 x P1 + R42 x P2 + R43 x P3 + R44 x P4 ) + Ta -- (4)
Measurement data on a low K (conductivity) board:
R11 = 181 °C/W
R21 = 103 °C/W
R31 = 82 °C/W
R41 = 110 °C/W
R12 = 91 °C/W
R22 = 232 °C/W
R32 = 97 °C/W
R42 = 86 °C/W
R13 = 85 °C/W
R23 = 109 °C/W
R33 = 180 °C/W
R43 = 101 °C/W
R14 = 112 °C/W
R24 = 91 °C/W
R34 = 91 °C/W
R44 = 277 °C/W
Measurement data on a high K (conductivity) board:
R11 = 117 °C/W
R21 = 37 °C/W
R31 = 35 °C/W
R41 = 47 °C/W
R12 = 42 °C/W
R22 = 161 °C/W
R32 = 53°C/W
R42 = 30 °C/W
R13 = 32 °C/W
R23 = 39 °C/W
R33 = 114 °C/W
R43 = 29 °C/W
R14 = 60 °C/W
R24 = 33 °C/W
R34 = 34 °C/W
R44 = 189 °C/W
1
2
3
4
5
6
12
11
10
9
8
7
Die 1:
IC1
Die 4:
LED2
Die 2:
LED1
Die 3:
IC2
R11 R12 R13 R14
•
P1
=
∆T1
R21 R22 R23 R24 P2 ∆T2
R31 R32 R33 R34 P3 ∆T3
R41 R42 R43 R44 P4 ∆T4
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved.
AV02-4893EN - August 11, 2015
