STR-Y6700 Series Quasi-Resonant Of f-Line Switching Regulators
Figure 1. STR-Y6700 series packages are fully molded SIPs, A
copper heat dissipation heatsink can be mounted at the rear surface
of the case.
Application Information
STR-Y6700-AN Rev. 2.0
The product lineup for the STR-Y6700 series provides the
following options:
Part
Number
MOSFET POUT
(W)*
VDSS(min)
(V)
RDS(on)(max)
(Ω)
STR–Y6735 500 0.8 VIN = 100 VAC
120
VIN =
380 VDC
VIN =
Universal
STR–Y6753 650 1.9 100 60
STR–Y6754 1.4 120 67
STR–Y6763
800
3.5 80 50
STR–Y6765 2.2 120 70
STR–Y6766 1.7 140 80
*Based on the thermal rating; the allowable maximum output
power can be up to 120% to 140% of this value. However, maxi-
mum output power may be limited in such an application with low
output voltage or short duty cycle.
General Description
The STR-Y6700 series products comprise a power MOSFET
and a multifunctional monolithic integrated circuit (MIC)
controller designed for controlling switch mode power supplies.
The quasi-resonant mode of operation, coupled with the
bottom-skip function, allows high efficiency and low noise at
low to high operational levels, while burst oscillation mode
ensures minimum power consumption at standby. In order to
sustain low power consumption under low load and in standby
mode, the controller has built-in startup and standby circuits.
The compact 7-pin full mold package (TO-220F-7L) reduces
board space by requiring a minimum of external components,
thus simplifying circuit design. This IC, including various
protection functions, is an excellent choice for standardized,
compact power supplies.
Features and Benefits
• TO–220F–7L package
• Lead (Pb) free compliance
• The built-in startup circuit reduces the number of external
components and lowers standby power consumption
• Multi-mode control allows high efficiency operation
across the full range of loads
• Auto burst oscillation mode for standby mode, for
improving low standby power at no load: input power
< 30 mW at 100 VAC and < 50 mW at 230 VAC
• Bottom-skip mode minimizes switching loss at medium to
low loads
• Built-in soft start function reduces stress applied to the
incorporated power MOSFET and peripheral components
• Step-on burst oscillation minimizes transformer
audible noise
• Built-in leading edge blanking (LEB) function eliminates
external filter components
• Built-in Bias Assist function enables stable startup
operation
• VCC operational range expanded
• Internal power MOSFET is avalanche energy guaranteed;
two-chip structure
• Protection functions
Overcurrent protection (OCP): pulse by pulse basis, low
dependence on input voltage
Overload protection (OLP): latched shutoff*
Overvoltage protection (OVP): latched shutoff*
Maximum on-time limitation
Thermal shutdown protection (TSD): latched shutoff*
*Latched shutoff means the output is kept in a shutoff mode
for protection, until reset.
2
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115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
STRY6700-AN
Table of Contents
Package Diagram 3
Electrical Characteristics 4
Absolute Maximum Ratings 4
MOSFET Electrical Characteristics 4
MIC Electrical Characteristics 5
Typical Application Circuit 6
Functional Description 7
Startup Operation 7
Startup Period 7
Bias Assist Function 8
Auxiliary Winding 8
Soft Start Function 10
Operational Mode at Startup 10
Constant Voltage Control Operation 11
Quasi-Resonant Operation and Bottom-On Timing 12
Quasi-Resonant Operation 12
Bottom-On Timing 12
RBD1 and RBD2 Setup 13
CBD Setup 13
BD Pin Blanking Time 14
Bottom Skip Quasi-Resonant Operation 15
Auto Standby with Burst Oscillation Function 17
Protection Functions 18
Undervoltage Lockout Function (UVLO) 18
Overvoltage Protection Function (OVP) 18
Overload Protection Function (OLP) 18
Thermal Shutdown (TSD) 19
Overcurrent Protection Function (OCP) 19
Overcurrent Input Compensation Function 19
BD Pin Peripheral Components Value Selection
Reference Example 22
When Overcurrent Input Compensation is
Not Required 22
Overcurrent Detection Threshold Voltage 22
Maximum On-Time Limitation Function 23
Design Notes 24
External Components 24
Transformer Design 24
Phase Compensation 26
Circuit Trace Layout 26
VCC
GND
D/ST
S/OCP
FB/OLP
BD
UVLO
Reg/Iconst
Latch
OSC
Startup
Logic
DRV
OCP/BS
FB/STB
OLP
BD
NF
3 1
2
5
6
4
7
MIC
STR-Y6700
Pin List Table
Name Number Function
1 D/ST MOSFET drain and Startup circuit input
2 S/OCP MOSFET source and overcurrent detection signal
input
3 VCC Control circuit power supply input
4 GND Ground
5 FB/OLP Constant Voltage Control signal input, Standby
control, and overload detection signal input
6BD
Bottom Detection signal input, Input Compensation
detection signal input
7NF
For stable operation, connect to GND pin, using
the shortest possible path
Functional Block Diagram
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115 Northeast Cutoff
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STRY6700-AN
Package Diagram
TO-220F-7L package, Leadform No. LF 3051
STR
a
b
0.5
(max)
0.5
(max)
0.5
(max)
0.5
(max)
5.08±0.6
2.54±0.6
0.45 +0.2
-0.1
R-end
5±0.5
R-end
2.6±0.1
2.6
4.2
3.2
+0.2
2.8
±0.15
2
±0.15
7-0.62
-0.1
+0.2
7-0.55
10.4 ±0.5 15
10
Gate Burr
71 23456
±0.2
（1.1）
±0.2
5±0.5
±0.2
5×P1.17±0.15
＝5.85±0.15
±0.3
(Measured at
pin base)
(Measured at
pin base)
(Measured at
pin tip)
(Measured at
pin tip)
(Front view) (Side view)
(Measured at
pin tip)
(Measured at
pin base)
±0.2
（5.6）
Pin material: Cu
Pin treatment: Solder dip
Product weight: Approximately1.45 g
Unit: Millimeters (mm)
Note: "Gate Burr" shows area where 0.3 mm (max.)
gate burr may be present
a. Product name label: Y67××
b. Lot #:
First letter, year manufactured: last number of year
Second letter, Month manufactured:
Jan. to Sep.: 0 to 9
October: O
November: N
December: D
Third and fourth letters: Date manufactured: 01 to 31
Fifth letter: Sanken control number
Pin treatment Pb-free. Device composition
compliant with the RoHS directive.
4
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115 Northeast Cutoff
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STRY6700-AN
Electrical Characteristics
• These data are from the STR-Y6763 which is representative of the series, except as noted.
• The polarity value for current specifies a sink as "+ ," and a source as “,” referencing the IC.
• Please refer to the datasheet of each product for additional details.
Absolute Maximum Ratings Unless specifically noted, TA = 25°C and VCC = 20 V
Characteristic Symbol Notes Pins Rating Unit
Drain Current1IDPEAK Single pulse 1 – 2 6.7 A
Maximum Switching Current1IDMAX TA = 20°C to 125°C 1 – 2 6.7 A
Single Pulse Avalanche Energy1EAS
Single pulse, VDD = 99 V, L= 20 mH,
ILPEAK= 2.3 A 1 – 2 60 mJ
Input Voltage in Control Part (MIC) VCC 3 – 4 35 V
Startup (D/ST) Pin Voltage VSTARTUP 1 – 4 1.0 to VDSS V
OCP Pin Voltage VOCP 2 – 4 2.0 to 6.0 V
FB Pin Voltage VFB 5 – 4 0.3 to 7.0 V
FB Pin Sink Current IFB 5 – 4 10.0 mA
BD Pin Voltage VBD 6 – 4 6.0 to 6.0 V
Power Dissipation in MOSFET1PD1
With an infinite heatsink 1 – 2 19.9 W
Without heatsink 1 – 2 1.8 W
Power Dissipation in Control Part (MIC) PD2 – 0.8 W
Internal Frame Temperature in Operation2TF–20 to 115 °C
Operating Ambient Temperature TOP –20 to 115 °C
Storage Temperature Tstg –40 to 125 °C
Channel Temperature Tch – 150 °C
1Please refer to each individual product datasheet for details.
2Recommended internal frame temperature is TF = 105°C (max).
Electrical Characteristics of MOSFET Unless specifically noted, TA = 25°C and VCC = 20 V
Characteristic Symbol Test Conditions Pins Min. Typ. Max. Unit
Voltage Between Drain and Source1VDSS 1 – 2 800 – – V
Drain Leakage Current IDSS 1 – 2 – – 300 A
On-Resistance1RDS(on) 1 – 2 – – 3.5
Switching Time1tf1 – 2 – – 250 ns
Thermal Resistance1,2 Rch-F – – 2.8 3.2 °C/W
1Please refer to each individual product datasheet for details.
2Thermal resistance between a channel of the MOSFET and the internal leadframe.
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STRY6700-AN
Electrical Characteristics of Control Part (MIC) Unless specifically noted, TA = 25°C and VCC = 20 V
Characteristic Symbol Test Conditions Pins Min. Typ. Max. Unit
Power Supply Startup Operation
Operation Start Voltage VCC(ON) 3 – 4 13.8 15.1 17.3 V
Operation Stop Voltage1VCC(OFF) 3 – 4 8.4 9.4 10.7 V
Circuit Current in Operation ICC(ON) 3 – 4 – 1.3 3.7 mA
Circuit Current in Non-Operation ICC(OFF) VCC = 13 V 3 – 4 – 4.5 50 A
Startup Circuit Operation Voltage VSTART(ON) 1 – 4 42 57 72 V
Startup Current ICC(STARTUP) VCC = 13 V 3 – 4 4.5 3.1 1.0 mA
Startup Current Supply Threshold
Voltage1VCC(BIAS) 3 – 4 9.5 11.0 12.5 V
Operation Frequency fOSC 1 – 4 18.4 21.0 24.4 kHz
Soft Start Operation Duration tSS 1 – 4 – 6.05 – ms
Normal Operation
Bottom-Skip Operation Threshold
Voltage 1 VOCP(BS1) 2 – 4 0.487 0.572 0.665 V
Bottom-Skip Operation Threshold
Voltage 2 VOCP(BS2) 2 – 4 0.200 0.289 0.380 V
Quasi-Resonant Operation Threshold
Voltage 12VBD(TH1) 6 – 4 0.14 0.24 0.34 V
Quasi-Resonant Operation Threshold
Voltage 22VBD(TH2) 6 – 4 – 0.17 – V
Maximum Feedback Current IFB(MAX) 5 – 4 320 205 120 A
Standby Operation
Standby Operation Threshold Voltage VFB(STBOP) 5 – 4 0.45 0.80 1.15 V
Protected Operation
Maximum On-Time tON(MAX) 1 – 4 30.0 40.0 50.0 s
Leading Edge Blanking Time tON(LEB) 1 – 4 – 470 – ns
Overcurrent Detection Threshold
Voltage (Normal Operation) VOCP(H) VBD = 0 V 2 – 4 0.820 0.910 1.000 V
Overcurrent Detection Threshold
Voltage (Input Compensation in
Operation)
VOCP(L) VBD = –3 V 2 – 4 0.560 0.660 0.760 V
Overcurrent Detection Threshold
Voltage (Latched shutoff) VOCP(La.OFF) 2 – 4 1.65 1.83 2.01 V
BD Pin Source Current IBD(O) VBD = –3 V 6 – 4 250 83 30 A
OLP Bias Current IFB(OLP) 5 – 4 15 10 5A
OLP Threshold Voltage VFB(OLP) 5 – 4 5.50 5.96 6.40 V
OVP Threshold Voltage VCC(OVP) 3 – 4 28.5 31.5 34.0 V
FB Pin Maximum Voltage in Feedback
Operation VFB(MAX) 5 – 4 3.70 4.05 4.40 V
Thermal Shut Down Temperature TJ(TSD) – 135 – – °C
1The relation of VCC(BIAS) > VCC(OFF) is maintained in each product.
2The relation of VBD(TH1) > VBD(TH2) is maintained in each product.
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STRY6700-AN
Typical Application Circuit
The NF pin (No. 7) should be connected to the GND pin (No. 4), which
should be at a stable ground potential, to ensure stability of operation.
NF
GND
FB/OLP
S/OCP
VCC
D/ST
2
17
5423
STR-Y6700
6
BD
VAC
C1
D2 R2
C2
T1 D3
C6
R3
R4
U2
R6
R8
C7
D
P
S
PC1
PC1
C4
ROCP
C5
D1
R5
R7
L1
C8
CV
VOUT
GND
C3
RBD2
RBD1
DZBD
CBD
R1
U1
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STRY6700-AN
Functional Description
VCC
Figure 2. D/ST and VCC pin peripheral circuits
Figure 3. VCC versus ICC
V pin voltage
CC
= 3.7mA
I
CC(ON)
(max)
Start
Stop
I
CC
V
CC(ON)
15.1 V
V
CC(OFF)
9.4 V
All of the parameter values used in these descriptions are typical
values, unless they are specified as minimum or maximum.
With regard to current direction, "+" indicates sink current
(toward the IC) and "–" indicates source current (from the IC).
Startup Operation
Startup Period
Typical D/ST and VCC pin peripheral circuits are shown in fig-
ure 2. This IC has a built-in Startup circuit which is connected to
the D/ST pin.
The Startup Current, ICC(STARTUP) = –3.1 mA, is constant-current
controlled inside the IC. When the electrolytic capacitor C2, con-
nected to the VCC pin, is fully charged and the VCC pin voltage
rises to the Operation Start Voltage, VCC(ON) = 15.1 V, the IC
Control Part (MIC) starts operation.
After switching operation begins, the startup circuit automatically
turns off (shuts off) to zero its current consumption.
The startup time is determined by the rating of C2, which is usu-
ally in the range of 10 to 47 F.
The approximate value of the startup time is calculated by the
following formula:
=
tSTART C2|ICC(STARTUP)|
VCC(ON) – VCC(INT)
×
(1)
where:
tSTART is the startup time in s, and
VCC(INT) is the initial voltage of the VCC pin in V.
Figure 3 shows the relation of the VCC pin voltage versus the
circuit current, ICC
. When the VCC pin voltage reaches the
Operation Start Voltage, VCC(ON) = 15.1 V, the Control Part (MIC)
starts operation and the circuit current increases. The voltage from
the auxiliary winding (D in figure 2) becomes a power source to
the Control Part after operation start. The turns ratio of auxiliary
winding D must be adjusted so that the VCC pin voltage becomes
the following range in the power supply specification for input
and output deviation:
VCC(BIAS)(max) < VCC < VCC(OVP)(min) (2)
12.5 (V) < VCC < 28.5 (V)
An auxiliary winding voltage of approximately 20 V is recom-
mended.
8
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STRY6700-AN
Bias Assist Function
Figure 4 shows the VCC voltage behavior during the startup
period. When VCC pin voltage reaches VCC (ON) = 15.1 V, the IC
Control Part (MIC) starts operation. Because of the relationship
of the turns ratios of the auxiliary winding D and of the primary
winding, the voltage through D does not rise to the target operat-
ing voltage immediately. After the IC starts, the VCC voltage
starts dropping. If it reaches VCC (OFF) = 9.4 V, the IC Control Part
(MIC) would be stopped by the UVLO (Undervoltage Lockout)
circuit, a startup failure would be caused, and the IC would revert
to the state before startup.
In order to prevent this, during a state of operating feedback con-
trol (the FB/OLP pin voltage is the Standby Operation Threshold
Voltage, VFB(STBOP) = 0.80 V or less), when the VCC pin voltage
falls to the Startup Current Supply Threshold Voltage, VCC(BIAS) =
11.0 V, the Bias Assist function is activated. While the Bias Assist
function is operating, the decrease of the VCC voltage is sup-
pressed by a supplementary current from the Startup circuit.
By the Bias Assist function, the use of a small value C2 capacitor
is allowed, resulting in improved response for OVP (Overvolt-
age Protection). Also, because the increase of VCC pin voltage
becomes faster when the output runs with excess voltage, the
response time of the OVP function can also be shortened. It is
necessary to check and adjust the process so that poor starting
conditions may be avoided.
Auxiliary Winding
In actual power supply circuits, there are cases in which the VCC
pin voltage fluctuates in proportion to the output of the SMPS
(see figure 5). This happens because C2 is charged to a peak volt-
age on the auxiliary winding D, which is caused by the transient
surge voltage coupled from the primary winding when the power
MOSFET turns off.
For alleviating C2 peak charging, it is effective to add some value
R2, of several tenths of ohms to several ohms, in series with D2
(see figure 6). The optimal value of R2 should be determined
using a transformer matching what will be used in the actual
application, because the proportion of the VCC pin voltage versus
the transformer output voltage differs according to transformer
structural design.
Time (t)
15.1 V
11.0 V
V
pin voltage
CC
VCC(OFF) =
VCC(ON) =
VCC(BIAS) =
9.4 V
IC startup Startup success
Target
Operating
Voltage
Bias Assist period
Startup failure
Figure 4. VCC during startup period
I
OUT
With R2
Without R2
V
pin voltage
CC
D
VCC
D2
C2
3
4
STR-Y6700
GND
R2
Added
Figure 5. VCC versus IOUT with and without resistor R2
Figure 6. VCC pin peripheral circuit with R2
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The variation of VCC pin voltage becomes worse if:
• The coupling between the primary and secondary windings of
the transformer gets worse and the surge voltage increases (low
output voltage, large current load specification, for example).
• The coupling of the auxiliary winding, D, and the secondary
side stabilization output winding (winding of the output line
which is controlling constant voltage) gets worse and it is sub-
ject to surge voltage.
In order to reduce the influence of surge voltages on the VCC pin,
alternative structures of the auxiliary winding, D, can be used.
Two alternatives are shown in figure 7.
• Winding structural example (a): Separating the auxiliary wind-
ing D from the primary side windings P1 and P2.
P1 and P2 are the windings which divide the primary side wind-
ing into two.
• Winding structural example (b): Structure which improves cou-
pling of the secondary side stabilization output winding S1 and
the auxiliary winding, D.
Of two output windings S1 and S2, the output winding S1 is a
stabilized output winding, controlled to constant voltage.
DS1 P2 S2P1
Barrier
Bobbin
Pin Side
Barrier
S1P2P1 S1 D S2
Barrier
Bobbin
Pin Side
Barrier
P1, P2 Primary side winding
S1 Secondary side winding from
which the output voltage is
controlled constant
S2 Secondary side winding
D Auxiliary winding for VCC
Figure 7. Winding structural examples
Winding structural example (b)
Winding structural example (a)
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Soft Start Function
Figure 8 shows the waveforms of operation at startup. The soft
start operation period, tSS , is internally set to 6.05 ms, and the
overcurrent protection (OCP) threshold voltage steps up in four
steps during this period. This reduces the voltage and current
stress on the incorporated MOSFET and on the secondary-side
rectifier.
During the soft start operation period, the operation is in
PWM operation, at an internally set operation frequency,
fOSC = 21.0 kHz. In addition, because the soft start operation
period is fixed internally, it is necessary to confirm and adjust the
VCC pin voltage and the OCP delay time during startup.
Operational Mode at Startup
As shown in figure 8, because the auxiliary winding voltage is
low at startup, there is a certain period when the quasi-resonant
signal has not yet reached regulation level (Quasi-Resonant
Operation Threshold Voltage 1, VBD(TH1)
, is 0.24 V or more, and
the effective pulse width for the quasi-resonant signal is 1.0 s
or more). During this period, the operation is in PWM operation
at an operation frequency of fOSC
= 21.0 kHz. Then, when output
voltage rises, the auxiliary winding voltage will rise, and when
a quasi-resonant signal reaches a regulated level, quasi-resonant
operation will begin.
Figure 8. Operational mode at startup
V
CC(ON)
V
CC(OFF)
Time
Startup Target Operating Voltage
MOSFET
Drain current
I
D
Soft-Start t
SS
=6.05 ms
Time
V
BD(TH1)
Time
BD pin voltage
VCC pin voltage
Operation mode
PWM operation
㧔f
OSC
=21.0kHz㧕
Quasi-resonant operation
A
Quasi-resonant
operation
PWM operation
BD pin waveform
Expanded at point A
Pulse width1.0 μs(min)
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Constant Voltage Control Operation
For enhanced response speed and stability, current mode control
(peak current mode control) is used for constant voltage control of
the output voltage.
Referring to figure 9, this IC compares the voltage, VR1
, of a cur-
rent detection resistor and target voltage, VSC , with the internal
FB comparator, and controls them so that the peak value of VR1
gets close to VSC .
VSC is determined by the voltage of the FB/OLP pin (refer to
figures 9 and 10).
• In the case of light load. If the load becomes light, the feedback
current (IFB) of the secondary side error amplifier will increase
along with the rise of output voltage. FB/OLP pin voltage falls
by detecting this current through a photocoupler. For the above
reason, because the target voltage VSC falls, it causes the value
of VR1 to fall. As a result, the peak value of the drain current
decreases and suppresses the rise of output voltage.
• In the case of heavy load. When the load becomes heavy, the
converse occurs with respect to light load operation: the target
voltage VSC of the FB comparator will become high, and the
peak value of the drain current increases and suppresses the
decrease of the output voltage.
Also, generally, because of the steep surge current which occurs
when the power MOSFET turns on, the FB comparator and
overcurrent protection circuit (OCP) may respond, and the power
MOSFET may turn off.
In order to prevent this phenomenon, the IC has a leading edge
blanking time, tON(LEB) = 470 ns, from the moment of the power
MOSFET turn on, which keeps it from responding to the drain
current surge. Please refer to each individual product datasheet
about tON(LEB) .
As shown in figure 11, when the power MOSFET turns on, if the
drain current surge pulse width is large, the following adjustments
are required so that the surge pulse width falls within tON(LEB)
.
• Match the turn-on timing to a VDS bottom point.
• Lower the rating of the voltage resonant capacitor, CV , and the
rating of the capacitor in the secondary side snubber circuit.
V'OCP(H) of figure 11 is the overcurrent detection threshold voltage
after input compensation.
Figure 9. FB/OLP pin feedback circuit
Figure 10. ID and FB comparator operation during
normal operation
Figure 11. S/OCP pin voltage
PC1
C3
R
OCP
245
S/OCP FB/OLPGND
STR-Y6700
I
FB
V
R1
V
SC
FB comparator
Drain Current,
I
D
-
+
S/OCP voltage
㧔R
OCP
voltage㧕
V
R1
Target voltage
Surge at MOSFET turn on
t
ON(LEB)
V
OCP(H)
'
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T1
S
E
IN
N
P
N
S
L
P
C
V
E
FLY
I
D
I
OFF
V
OUT
C6
V
f
C1
D3
P
Figure 12. Basic flyback converter circuit
Figure 13. Ideal bottom-on operation waveform (MOSFET turn-on at a
bottom point of a VDS waveform)
EIN Input voltage
EFLY Flyback voltage (EFLY = (NP / NS) × (VO + Vf)
NP Primary side number of turns
NS Secondary side number of turns
VOUT Output voltage
Vf Forward voltage drop of the secondary side rectifier
ID Drain current of power MOSFET
IOFF Current which flows through the secondary side rectifier
when power MOSFET is off
CV Voltage resonant capacitor
LP Primary side inductance
V
DS
I
OFF
I
D
t
ON
E
IN
E
FLY
VPONDLY CLt P
z
t
ONDLY
(half cycle of free oscillation)
Bottom
Point
0
0
0
Quasi-Resonant Operation and Bottom-On
Timing
Quasi-Resonant Operation
Figure 12 shows the circuit of a flyback converter. A flyback
converter is a system which transfers the energy stored in the
transformer to the secondary side when the primary side power
MOSFET is turned off. After the energy is completely trans-
ferred to the secondary, when the MOSFET keeps turning off, the
MOSFET drain node begins free oscillation based on the LP of
the transformer and CV across the drain and source pins.
The quasi-resonant operation is the VDS bottom-on operation that
turns-on the MOSFET at the bottom point of VDS free oscillation.
Figure 13 shows an ideal VDS waveform during bottom-on
operation.
Using bottom-on operation, switching loss and switching noise
are reduced and it is possible to obtain converters with high
efficiency and low noise. This IC performs bottom-on operation
not only during normal quasi-resonant operation, but also during
bottom-skip quasi-resonant operation. This allows reduction of
the operation frequency during light-load conditions, to improve
efficiency across the full range of loads.
Bottom-On Timing
Figure 14 shows the voltage waveform of the BD pin peripheral
circuit and auxiliary winding, D. The following setup is required
with the BD pin:
1. Bottom-on timing setup (described here, below).
2. OCP input compensation value setup (refer to OCP section for
description).
The components DZBD, RBD1, RBD2, and CBD, are connected to
the BD pin peripheral circuit as shown in figure 14, with values
that are determined with above-mentioned steps 1 and 2.
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This delay time for bottom-on, from the start of VDS free oscilla-
tion to the timing of turning-on the power MOSFET, is created by
exploiting the auxiliary winding voltage, which synchronizes to
the drain voltage VDS waveform.
Referring to figure 14, either end of RBD1 and RBD2 subtracts
the forward voltage drop, Vf
, of DZBD from the flyback voltage,
Erev1, of the auxiliary winding, D.
The quasi-resonant signal, Erev2
, is the voltage of the BD pin
biased RBD2 by Erev1. The delay time, tONDLY
, of Erev2 is required
to be adjusted by CBD after the other component values have
been set.
After the power MOSFET turns off, the quasi-resonant signal
immediately goes up and it exceeds the Quasi-Resonant Opera-
tion Threshold Voltage 1, VBD(TH1) = 0.24 V. After this occurs,
the power MOSFET remains off until the quasi-resonant sig-
nal comes down enough to cross the Quasi-Resonant Opera-
tion Threshold Voltage 2, VBD(TH2) = 0.17 V. Then the power
MOSFET again turns on. In addition, at this point, the threshold
voltage goes up to VBD(TH1) automatically to prevent malfunction
of the quasi-resonant operation from noise interference.
RBD1 and RBD2 Setup
RBD1 and RBD2 must set the range for the quasi-resonant signal:
VBD(TH1) = 0.34 V (max) or more under input and output con-
ditions where VCC becomes lowest, but less than the absolute
maximum rating of the BD pin, 6.0 V , under conditions where
VCC becomes highest.
Figure 21 defines the pulse width of the quasi-resonant signal. For
initiating quasi-resonant operation, the quasi-resonant signal pulse
width between the two points VBD(TH1) and VBD(TH2) must be
1.0 s or more. The recommended value of Erev2 is about 3.0 V.
CBD Setup
The delay time, tONDLY
, after which the power MOSFET turns on,
is adjusted by the value of CBD , so that the power MOSFET turns
on at the bottom-on of VDS.
To do so, observe the power MOSFET drain voltage, VDS, the
drain currnet, ID, and the quasi-resonant signal, under the maxi-
mum input voltage and the maximum output power, as shown in
figure 13.
1
S/OCP
VCC
D/ST
BD 6
3
C1
D2 R2
C2
T1
D
P
R
OCP
C
V
R
BD1
DZ
BD
E
IN
E
FLY
E
IN
Flyback voltage
Forward Voltage
0
E
fw1
E
rev1
㨠
ON
Auxiliary
Winding
Voltage
V
D
V
BD(TH1)
V
BD(TH2)
Clamping Snubber
2
C
BD
R
BD2
STR-Y6700
E
rev2
0
E
rev1
E
fw1
Quasi-resonant
signal,
E
rev2
GND
4
3.0 V recommended,
but less than 6.0 V acceptable
Figure 14. BD pin peripheral circuit (left) and auxiliary winding voltage and flyback voltage timing (right)
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VDS
0
IOFF
0
Auxiliary
Winding
Voltage
Bottom
point
Early turn-on point
Bottom
point
Delayed turn-on point
ｔ
ON ｔ
ON
VP
R
CL2
1
fP
Free oscillation, fR
ID
0
VBD
0
VD
0
VDS
0
IOFF
0
ID
0
VBD
0
VD
0
VBD(TH1)
VBD(TH2) VBD(TH2)
VBD(TH1)
Auxiliary
Winding
Voltage
Figure 15. When the turn-on of a VDS waveform
occurs before a bottom point Figure 16. When the turn-on of a VDS waveform
occurs after a bottom point
The following show how to adjust the turn-on point:
• If the turn-on point precedes the bottom of the VDS signal (see
figure 15), it causes higher switching losses. In that situation,
after confiming the initial turn-on point, delay the turn-on point
by increasing the CBD value gradually, so that the turn-on will
match the bottom point of VDS.
• In the converse situation, if the turn-on point lags behind the
VDS bottom point (see figure 16): it causes higher switching
losses also. After confirming the initial turn-on point, advance
the turn-on point by decreasing the CBD value gradually, so that
the turn-on will match the bottom point of VDS .
An initial reference value for CBD is about 1000 pF.
BD Pin Blanking Time
Figure 17 shows two different BD pin waveforms, comparing
transformer coupling conditions between the primary and second-
ary winding. The poor coupling tends to happen in a low output
voltage transformer design with high NP/ NS turns ratio (NP
and NS indicate the number of turns of the primary winding and
secondary winding, respectively), and it results in high leakage
inductance. The poor coupling causes high surge voltage ring-
ing at the power MOSFET drain pin when it turns off. That high
surge voltage ringing is coupled to the auxiliary winding and then
the inappropriate quasi-resonant signal occurs.
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Erev2
Normal Waveform
(Good coupling)
VBD(TH1)= 0.24V
VBD(TH2)= 0.17V
Erev2
VBD(TH1)= 0.24V
VBD(TH2)= 0.17V
BD pin blanking time
250ns（max）
Inappropriate Waveform
(Poor coupling)
Figure 17. The difference of BD pin voltage waveform by the coupling condition of
the transformer; good coupling (top) versus inappropriate coupling (bottom)
The BD pin has a blanking period of 250 ns (max) to avoid the
IC reacting to it, but if the surge voltage continues longer than
that period, the IC responds to it and repeatedly turns the power
MOSFET on and off at high frequency. This results in an increase
of the MOSFET power dissipation and temperature, and it can be
damaged.
The following adjustments are required when such high fre-
quency operation occurs:
• CBD must be connected near the BD pin and the GND pin
• The circuit trace loop between the BD pin and the GND pin
must be separated from any traces carrying high current
• The coupling of the primary winding and the auxiliary winding
must be good
• The clamping snubber circuit (refer to figure 14) must be ad-
justed properly.
In addition, the BD pin waveform during operation should be
measured by connecting test probes as short to the BD pin and
the GND pin as possible, in order to measure any surge voltage
correctly.
Bottom Skip Quasi-Resonant Operation
In order to reduce switching losses during light to medium load
conditions, in addition to quasi-resonant operation, the bottom
skip function is built in, to limit the rise of the power MOSFET
operation frequency. This function monitors the power MOSFET
drain current (in fact, the S/OCP pin voltage), and during heavy
load conditions it automatically changes to normal quasi-resonant
operation, and during light to medium loads, it changes to bottom
skip quasi-resonant operation.
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Figure 18 shows the operation state transition diagram of the
output load from light load to heavy load. Figure 19 shows the
state transition diagram from heavy load to light load. (In these
diagrams, the amplitude of the S/OCP pin is shown without input
current compensation, and thus the OCP threshold voltage is
VOCP(H) = 0.910 V.)
This IC has a built-in automatic multi-mode control which
changes among the following three operational modes according
to the output loading state: auto standby mode, one bottom-skip
quasi-resonant operation, and normal quasi-resonant operation.
• The mode is changed from one bottom-skip quasi-resonant
operation to normal quasi-resonant operation (figure 18), when
load is increased from one bottom-skip operation, the MOSFET
peak drain current value will increase, and the positive pulse
width (see figure 21) will widen. Also, the peak value of the
S/OCP pin voltage increases. When the load is increased further
and the S/OCP pin voltage rises to VOCP(BS1) , the mode is
changed to normal quasi-resonant operation.
• The mode is changed from normal quasi-resonant operation to
one bottom-skip quasi-resonant operation (figure 19), when load
is reduced from normal quasi-resonant operation, the MOSFET
peak drain current value will decrease, and the positive pulse
width (see figure 21) will narrow. Also, the peak value of the S/
OCP pin voltage decreases. When load is reduced further and
the S/OCP pin voltage falls to VOCP(BS2)
, the mode is changed to
one bottom-skip quasi-resonant operation. This suppresses the
rise of the MOSFET operation frequency.
As shown in figure 20, in the process of the increase and decrease
of load current, hysteresis is imposed at the time of each opera-
tional mode change. For this reason, the switching waveform
does not become unstable near the threshold voltage of a change,
and this enables the IC to switch in a stable operation.
V
OCP(BS1)
= 0.572V
One Bottom
pin voltage
-Skip Quasi-Resonant Normal Quasi-Resonant (Heavy Load)
V
OCP(H)
= 0.910V
V
DS
S/OCP
(Light Load)
V
OCP(BS2)
= 0.289V
One Bottom-Skip Quasi-ResonantNormal Quasi-Resonant
(Heavy Load
pin voltage
)
V
OCP(H)
= 0.910V
V
DS
S/OCP
(Light Load)
Figure 18. Operation state transition diagram from light load to heavy load conditions
Figure 19. Operation state transition diagram from heavy load to light load conditions
Bottom-Skip Quasi-resonsant
Normal Quasi-Resonant
V
OCP(BS2)
V
OCP(BS1)
V
OCP(H)
Load
Current
Figure 20. Hysteresis at the time of an operational mode change
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In order to perform stable normal quasi-resonant operation and
one bottom-skip operation, it is necessary to ensure that the pulse
width of the quasi-resonant signal is 1 s or more under the con-
ditions of minimum input voltage and minimum output power.
The pulse width of the quasi-resonant signal, Erev2
, is defined
as the interval between VBD(TH1) = 0.34 V (max) on the rising
edge, and VBD(TH2) = 0.27 V (max) on the falling edge of the
pulse. Figure 21 shows the quasi-resonant signal waveform pulse
width definitions.
Auto Standby with Burst Oscillation Function
The auto standby function automatically changes the IC operation
mode to standby mode, with burst oscillation, when the MOSFET
drain current, ID, decreases during light loads.
The S/OCP pin circuit monitors ID
. When the S/OCP pin voltage
falls to the standby state threshold voltage (about 9% compared
to VOCP(H) = 0.910 V) , the auto standby function changes the IC
to standby mode (figure 22). Also, during standby mode, when
the FB/OLP pin voltage falls below VFB(STBOP)
, the IC stops
switching operation, and the burst oscillation mode will begin.
During burst oscillation mode, because switching operation has
a certain interval of off-time, switching losses are reduced and
efficiency is improved under light load conditions.
Generally, a burst interval is set to several kilohertz or less, in
order to improve the efficiency during light loads. When the burst
oscillation frequency is in the human audible range (20 Hz to
20 kHz), audible noise may occur from the transformer.
This IC keeps the peak drain current low during burst oscillation
mode, and suppresses the audible noise of the transformer further
by enabling the step-on burst oscillation function, which expands
the pulse width gradually.
During the transition stage to burst oscillation mode, if the VCC
pin voltage falls to the Start-up Current Supply Threshold Volt-
age, VCC (BIAS) = 11.0 V, the Bias Assist function will operate and
supply the starting current ICC(STARTUP)
. This stops the fall of the
VCC pin voltage and enables stable standby operation.
In addition, because the power consumption of the IC will
increase when the Bias Assist function operates during normal
operation (which includes burst oscillation mode periods), an
adjustment of the peripheral circuit is required to make the VCC
pin voltage higher than VCC (BIAS)
, by adjusting the turns ratio of
the transformer, and minimizing R2, as shown in figure 6.
Figure 21. The pulse width of a quasi-resonant signal; normal operation (left) and one bottom-skip operation (right)
Figure 22. Auto Standby mode timing
E
rev2
V
BD(TH1)
= 0.34V(MAX)
Pulse Width
1.0s or more
V
BD(TH2)
= 0.27V(MAX)
S/OCP pin voltage S/OCP pin voltage
E
rev2
V
BD(TH1)
= 0.34V(MAX)
V
BD(TH2)
= 0.27V(MAX)
Pulse Width
1.0s or more
Normal Operation Standby Operation Normal Operation
Burst Oscillation
SMPS Output
Current, I
OUT
V
OCP(H)
approximately 9%
Below several kHz
S/OCP pin voltage related to
the drain current, I
D
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Protection Functions
Undervoltage Lockout Function (UVLO)
In operation, when the VCC pin voltage decreases to VCC(OFF) =
9.4 V (typ), the Control Part (MIC) stops operation, by activat-
ing the UVLO (Undervoltage Lockout) circuit, and reverts to the
state before startup (see figure 23).
Overvoltage Protection Function (OVP)
When the voltage between the VCC pin and GND pin exceeds
the OVP Operation power-supply voltage, VCC(OVP) = 31.5 V,
the overvoltage protection function (OVP) operates and stops
switching operation in latch mode. When the switching opera-
tion stops, the VCC pin voltage will begin to fall, and when it
reaches VCC(BIAS) = 11.0 V, the Bias Assist function will oper-
ate. When the Bias Assist function operates, the Startup Current,
ICC(STARTUP) , will be supplied to the VCC pin, and prevent VCC
pin voltage from falling to the Operation Stop power-supply volt-
age, VCC(OFF) = 9.4 V, and the latched state is maintained. Releas-
ing the latched state is done by turning off the input voltage and
by dropping the VCC pin voltage below VCC(OFF).
Because the VCC pin voltage is proportional to the output volt-
age, when supplying VCC pin voltage from the auxiliary wind-
ing of the transformer, excess voltage on the secondary side is
detectable (such that the output voltage detection circuit is open).
In this case, the approximate value of the secondary side output
voltage at the time of overvoltage protection operation can be
calculated by the following formula:
=
VOUT(OVP) 31.5 (V)
VOUT(normal operation)
VCC(normal operation)
× (3)
Overload Protection Function (OLP)
Figure 24 shows the waveform of the IC when the overload pro-
tection function is active.
When an overload state (the state where overcurrent protection,
OCP, operation has limited the peak drain current value) occurs,
the output voltage will decline and the error amplifier on the
secondary side cuts off. When the error amplifier cuts off, the
capacitor C4 connected to the FB/OLP pin will be charged, and
go up to the maximum voltage during feedback control, VFB(MAX)
45
FB/OLPGND
I
FB
C4 C3
R1 PC1
VCC pin voltage
FB/OLP pin voltage
V
FB(OLP)
= 5.96V
V
FB(MAX)
= 4.05V
V
CC(BIAS)
I
D
t
DLY
Bias assist
Latch release
V
CC(OFF)
STR-Y6700
Charge by I
FB(OLP)
Figure 24. Operation waveform at the time of OLP operation (left) and peripheral circuit (right)
Figure 23. ICC versus VCC at start and stop
V pin voltage
CC
= 3.7mA
I
CC(ON)
(max)
Sto
p
Startup
I
CC
9.4 V
V
CC(OFF)
V
CC(ON)
15.1 V
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= 4.05 V. Then, C4 is charged by feedback current IFB(OLP) =
–10 A. When the FB/OLP pin voltage reaches the OLP Thresh-
old Voltage, VFB(OLP) = 5.96 V, the overload protection circuit will
operate and stop switching operation. Switching operation will be
stopped in latch mode at the time of overload protection opera-
tion. Releasing the latched state is done by turning off the input
voltage and by dropping the VCC pin voltage below VCC(OFF).
The time of the FB/OLP pin voltage from VFB(max) = 4.05 V
to VFB(OLP) = 5.96 V is defined as the OLP Delay Time, tDLY
.
Because the capacitor C3 for phase compensation is small com-
pared to C4, in the case of IFB(OLP) = –10 A, the approximate
value of tDLY is determined by the following formula:
≈
tDLY
(VFB(OLP) – VFB(MAX)
) × C4
|
IFB(OLP)
|
≈
(5.96 (V) – 4.05 (V)
) × C4
|
–10 A
|
(4)
In the case of C4 = 4.7 F, the value of tDLY would be approxi-
mately 0.9 s. The recommended value of R1 is 47 k.
To enable the overload protection function to initiate an auto-
matic restart, 220 k is connected between the FB/OLP pin and
ground, as a bypass path for IFB(OLP)
, as shown in figure 25.
In the case where automatic restart is used, the IC function is
an intermittent oscillation mode, determined by the cycle of the
charge and discharge of the capacitor C2 (refer to figure 6) con-
nected to the VCC pin. In this case, the charge time is determined
by the startup current from the startup circuit, while the discharge
time is determined by the current supply to the internal circuits of
the IC.
Thermal Shutdown (TSD)
When the temperature of the Control Part (MIC) reaches the
Thermal Protection Threshold Temperature, TJ(TSD) = 135°C
(min), the thermal protection function (TSD) operates and switch-
ing operation is stopped in latch mode. Releasing the latched state
is done by turning off the input voltage and by dropping the VCC
pin voltage below VCC(OFF).
Overcurrent Protection Function (OCP)
The overcurrent protection function (OCP) detects the peak drain
current value of the incorporated power MOSFET by means of
the current detection resistor ROCP , between the S/OCP pin and
ground (see figure 27). When the voltage drop of ROCP reaches
the Overcurrent Detection Threshold Voltage (Normal Opera-
tion), VOCP(H) = 0.910 V, the power MOSFET turns off and the
output power is limited (pulse by pulse basis).
Overcurrent Input Compensation Function
When using a quasi-resonant converter with universal input
(85 to 265 VAC), if the output power is set constant, then because
higher input voltages have higher frequency, the MOSFET peak
drain current becomes low.
Figure 25. Individual operation waveforms (left) and peripheral circuit configured for OLP with
automatic restart (right)
VCC pin voltage
FB/OLP pin voltage
V
FB(OLP)
= 5.96V
V
CC(OFF)
V
CC(ON)
I
D
45
FB/OLPGND
I
FB
C3
220k
PC
1
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Because ROCP is fixed, the OCP point in the higher input volt-
age will shift further into the overload area. And thus, the output
current at OCP point in the maximum input voltage, IOUT(OCP)
,
doubles relative to that in the minimum input voltage.
In order to suppress this phenomenon, this IC has the overcurrent
input compensation function.
As for determining an input compensation value, it is necessary
to avoid excessive input compensation for the output current
specification, IOUT , as shown in figure 26. When excessive input
compensation is applied, IOUT(OCP) may be below IOUT in the situ-
ation where the input voltage is high. Therefore, it is necessary
to ensure that IOUT(OCP) remains more than IOUT across the input
voltage range.
Figure 27 shows an overcurrent input compensation circuit, and
figure 28 shows Efw1 and Efw2 relative to the input voltage. Also,
figure 29 shows the relationship between the overcurrent thresh-
old voltage after input compensation, V'OCP(H) , and the BD pin
voltage, Efw2.
The overcurrent input compensation function compensates the
overcurrent detection threshold voltage (normal operation),
VOCP(H) , according to the input voltage. As shown in figure 27,
the forward voltage, Efw1, is proportional to the input voltage,
Figure 26. OCP circuit input compensation
Figure 28. Efw1 and Efw2 voltage relative to AC input voltage
Figure 27. Overcurrent input compensation circuit
Figure 29. Overcurrent threshold voltage after input compensation, V'OCP(H)
(reference for design target values)
I
OUT
without input
compensation
I
OUT
with excessive
input compensation
I
OUT
Output Current at OCP, I
OUT(OCP)
㧔A㧕
85V 265V
AC Input Voltage (V㧕
I
OUT
target output level
I
OUT
with appropriate
input compensation
6
GND
VCC
BD
S/OCP
4
3
2
D2 R2
C2
T1
D
ROCP
RBD2
RBD1
DZBD
CBD
Efw2
VDZBD
STR-Y6700
Forward voltage, Efw1
Flyback voltage, Erev1
Efw1
Efw2
100 V 230 V
AC
AC
0
0
VZ
OCP input compensation
starting point:
the point matching Efw1– VZ = 0
0
0.2
0.4
0.6
0.8
1
–6–5–4–3–2–10
Recommended use range
V
OCP(H)
' (V)
MAX
TYP
MIN
BD pin voltage, Efw2 (V)
V
OCP
(
H
)
= 0.910
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the voltage passed through DZBD from Efw1 is biased by either
end of RBD1 and RBD2
, and thus the BD pin voltage is provided
the voltage on RDB2 divided by the divider of RBD1 and RBD2.
Referring to figure 29, the overcurrent detection threshold voltage
after input voltage compensation, V'OCP(H) , relative to Efw2 can be
calculated, and this voltage becomes the OCP threshold voltage
after input compensation.
• DZBD setting: The starting voltage for input compensation is
set by the Zener voltage, VZ , of DZBD
. According to the input
voltage specification or transformer specification, it is required
to be VZ = 6.8 to 30 V.
• RBD1 setting: Please refer to Bottom-On Timing section, p. 12.
• The recommended value of RBD2: 1.0 k
Overcurrent input compensation should be adjusted so that the
variance of the output current, IOUT(OCP) , at an OCP point, is
minimized at the high and low input voltage. In addition, as
shown in figure 26, the input compensation must be adjusted so
that IOUT(OCP) remains more than the output current specification,
IOUT , across the input voltage range.
If V'OCP(H) is compensated to the Bottom-Skip Operation Thresh-
old Voltage, VOCP(BS1), or less, the IC will change from one bot-
tom-skip operation to normal quasi-resonant operation, and thus
will raise the operation frequency and will provide output power.
Therefore, switching losses in normal quasi-resonant operation
is higher than that in bottom-skip operation. In this case, when
the input compensation is compensated to VOCP(BS1) or less, the
temperature of the power MOSFET should be checked in normal
quasi-resonant operation switched from bottom-skip operation,
by changing load condition. Efw2
, which includes surge voltage,
must be within the absolute maximum rating of the BD pin volt-
age (–6.0 to 6.0 V) at the maximum input voltage.
Figure 30 shows each voltage waveform for the input voltage in
normal quasi-resonant operation:
• When VDZBD Efw1 (Point A). No input compensation required,
Efw2 remains zero, and the detection voltage for an overcurrent
event is the Overcurrent Detection Threshold Voltage (normal
operation), VOCP(H).
• When VDZBD < Efw1 (Point B through Point D). When the input
voltage is increased and Efw1 exceeds the Zener voltage, VZ,
of DZBD, Efw2 will be produced as a negative voltage to com-
pensate the Overcurrent Detection Threshold Voltage (normal
operation), VOCP(H)
.
Efw2 is generally adjusted to the BD pin voltage of Efw2 = –3.0 V
at the maximum input voltage. Adjustment of Efw2 will change
the overcurrent detection threshold voltage by an overcurrent
input compensation function. Therefore, Efw2 must be adjusted
while checking the input compensation starting point and the
amount of input compensation. Also, the variations of the over-
current detection threshold voltage after input compensation,
V'OCP(H) , can be calculated by the MIN and MAX values shown
in figure 29.
Figure 30. Each voltage waveform for the input voltage in normal quasi-resonant operation
E
rev1
E
fw1
V
DZBD
E
fw2
100V 230V
t
ON
t
ON
t
ON
t
ON
DZBD Zener voltage, Vz
AB C D
Auxiliary winding voltage
0
0
0
Input voltage
Input voltage
At the input voltage where E
fw1
reaches
V
Z
or more, E
fw2
goes negative.
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BD Pin Peripheral Components Value Selection Reference
Example
This example demonstrates the determination of external compo-
nent values for the BD pin peripheral circuit. It assumes universal
input (85 to 265 VAC) is being used, and input compensation
begins from the input voltage of 120 VAC. The transformer is
assumed to have primary winding with NP = 40 T, and an auxil-
iary winding with ND = 5 T.
To determine the Zener voltage, VZ , of DZBD , Efw1 at 120 VAC is
calculated by the following formula:
Efw1
ND
NP
= × VIN(AC) ×
5
40
==
× 120 (V) × 21.2 (V)
(5)
The Zener diode rating, VZ
, is chosen to be 22 V, a standard
value.
RBD1 results in Efw2 = –3.0 V at the maximum input voltage of
265 VAC, as follows:
2fw
BD)AC(IN
P
D
2fw
2BD
1BD
E
Z2V
N
N
E
R
R=
=
=
×
××
××
28.73222265
40
5
3
(k)
(V) (V) (V) (V) (k)
1
(6)
The RBD1 rating is chosen to be 7.5 k of the E series.
Choosing RBD2 = 1.0 k, the | Efw2 | value at 265 VAC can be
calculated as follows:
BD1fw
2BD1BD
2BD
2fw
ZE
RR
R
E×
+
=
(V)
(V) (V)
92.2
222265
40
5
1 (k)7.5 (k)
1(k)
=
××
+
=
(7)
2.92 V is an acceptable approximation of |–3.0 V|. Referring to
figure 29, when compensated by Efw2 = –2.92 V, the overcurrent
threshold voltage after input compensation, V'OCP(H), is set to
about 0.66 V (typ).
When setting RBD2 = 1 k, RBD1 = 7.5 k, Vf = 0.7 V, and Erev1 =
20 V, Erev2 of figure 14 can be calculated as follows:
()
f1rev
2BD1BD
2BD
2rev
VE
RR
R
E×
+
=
()
(V)
(V)
(V)
27.2
7.020
(k)(k)5.71
(k)1
=
×
+
=
(8)
In this case, the quasi-resonant voltage Erev2 meets the design
guidelines: it is Quasi-Resonant Operation Threshold Voltage
1, VBD(TH1) = 0.24V or more, and Efw2 and Erev2 are kept within
the limits of the Absolute Maximum Rating (–6.0 to 6.0 V) of
the BD pin.
When Overcurrent Input Compensation is Not Required
When the input voltage is narrow range, or provided from PFC
circuit, the variation of the input voltage is small. And thus, the
variation of OCP point may become less than that of the universal
input voltage specification.
When overcurrent input compensation is not required, the input
compensation function can be disabled by substituting a high-
speed diode for the Zener DZBD diode, and by keeping BD pin
voltage from being minus voltage.
In addition, the following formula shows the reverse voltage of a
high-speed diode. The high-speed selection should take account
of its derating.
VoltageInput Maximum
P
D
fw1
N
N
E
(9)
Overcurrent Detection Threshold Voltage
The overcurrent detection threshold voltage has two modes of
operation.
• Overcurrent protection (OCP) on a pulse by pulse basis
When the S/OCP pin voltage reaches the Overcurrent Detection
Threshold Voltage (normal operation), VOCP(H), or the threshold
voltage after overcurrent input compensation, V'OCP(H) (refer
to figure 29), the OCP function is activated on a pulse by pulse
basis.
23
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Figure 31. Confirmation of maximum on-time
V
DS
I
D
Maximum
On-Time
Time
Time
• Overcurrent protection in latch mode
As the protection for an abnormal state, such as an output wind-
ing being shorted or the withstand voltage of secondary rectifier
being out of specification, when the S/OCP pin voltage reaches
VOCP(La.OFF) = 1.83 V, the IC stops switching operation immedi-
ately, in latch mode. Releasing the latched state is done by turn-
ing off the input voltage and by dropping the VCC pin voltage
below VCC(OFF).
This overcurrent protection also operates during the leading edge
blanking.
Maximum On-Time Limitation Function
When the input voltage is low or in a transient state such that
the input voltage turns on or off, the on-time of the incorporated
power MOSFET is limited to the maximum on-time, tON(MAX) =
40.0 s (refer to figure 31). And thus, the peak drain current is
limited, and the audible noise of the transformer is suppressed.
In designing a power supply, the on-time must be less than
tON(MAX)
.
If such a transformer is used that the on-time is tON(MAX) or more,
under the condition with the minimum input voltage and the
maximum output power, the output power would become low.
In that case, the transformer should be redesigned taking into
consideration the following:
• Inductance, LP , of the transformer should be lowered in order to
raise the operation frequency.
• Lower the primary and the secondary turns ratio, NP / NS
, to
lower the duty cycle.
24
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External Components
Take care to use properly rated and proper type of components.
• Output smoothing capacitor. Consider design margins for rat-
ings of ripple current, voltage, and temperature in selecting the
output capacitor. A low impedance capacitor, designed to be
tolerant against high ripple current, is recommended.
• Transformer. Consider design margins for temperature rise,
resulting from copper losses and core losses, in designing or
selecting a transformer. Switching current contains a high
frequency component that causes the skin effect; therefore,
consider a current density of 3 to 4 A/mm2 and select a wire
gauge based on RMS current. In the event further temperature
measurement is necessary and it is necessary to increase surface
area of the wire, try the following measures:
Increase the quantity of parallel wires
Use litz wire
Increase the diameter of the wires
• Current detection resistor, ROCP
. Choose a low equivalent series
inductance and high surge tolerant type for the current detection
resistor. If a high inductance type is used, it may cause malfunc-
tioning because of the high frequency current running through
it.
Transformer Design
The design of the transformer is fundamentally the same as the
power transformer of a Ringing Choke Converter (RCC) sys-
tem: a self-excitation type flyback converter. However, because
the duty cycle will change due to the quasi-resonant operations
delaying the turn-on, the duty cycle needs to be compensated.
When the on-duty, DON, is calculated by the ratio of the primary
turns, NP , and the secondary turns, NS
, the inductance, L'P on the
primary side, taking into consideration the delay time, can be
calculated by the following formula:
2
V0ON)MIN(IN
1
0O
2
ON)MIN(IN
P
CfDE
f2P
D)(E
'
L
×××+
×
×
=
(10)
where
PO: the maximum output power,
f0: the minimum operation frequency,
CV : the voltage resonance capacitor connected between the
drain and source of the power MOSFET,
1: the transformer efficiency,
DON : the on-duty at the minimum input voltage,
FLY)MIN(IN
FLY
ON
EE
E
D,
+
=
EIN(MIN): the C1 voltage of figure 32 at the minimum input
voltage,
EFLY : the flyback voltage ⇒
()
fO
S
P
FLY
VV
N
N
E, and+×=
Vf : the forward voltage drop of D3.
Design Notes
Figure 32. Quasi-resonant circuit
T1
S
EIN
NPNS
LP
CV
EFLY
ID
IOFF
VO
C6
VF
C1
D3
P
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Each parameter, such as the peak drain current, IDP
, is calculated
by the following formulas:
VP
ONDLY
C'Lπt=
(11)
()
ONDLY0ONON
tf1D
'
D×=
(12)
IN(MIN)2
O
IN E
1
P
Iǯ
(13)
'
D
I2
I
ON
IN
DP
=
(14)
AL-value
'L
N
P
P
(15)
FLY
fOP
S
E
VVN
N
(16)
where
tONDLY
: the delay time of quasi-resonant operation,
IIN
: the average input current,
2 : the conversion efficiency of the power supply,
IDP : the peak drain current,
D'ON : the on-duty after compensation, and
VO : the secondary side output voltage.
The minimum operation frequency, f0 , can be calculated by the
following formula:
()
2
ON)MIN(INV
P
V
2
ON)MIN(IN
1
O
1
O
0DEC2
'L
CDE4
2P
2P
f
××
××
++−
=
(17)
In transformer design, AL-value and NP must be set in a way that
the ferrite core does not saturate. Here, use ampere turn value
(AT), the result of IDP × NP and the graph of NI-Limit (AT) versus
AL-value (figure 33 is an example of it). NI-Limit is the limit
that the ampere turn value should not exceed; otherwise the core
saturates.
When choosing a ferrite core to match the relationship of
NI-Limit (AT) versus AL-value, it is recommended to set the cal-
culated NI-Limit value below about 30% from the NI-Limit curve
of ferrite core data, as shown in the hatched area containing the
design point in figure 33, to provide a design margin in consider-
ation of temperature effects and other variations.
Figure 33. Example of NI-Limit versus AL-Value characteristics
NI-Limit (AT)
AL-Value (nH/T2)
Margin = 30% less
Saturation
region lower
boundary
Design point
(example)
26
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Phase Compensation
Figure 34 shows a typical secondary side error amplifier circuit.
The C7 value for phase compensation is recommended to be
0.047 to 0.47 F, and should be confirmed in actual operation.
Figure 35 shows a circuit around the FB/OLP pin. The C3 value,
for high frequency noise rejection and phase compensation, is
recommended to be approximately 470 pF to 0.01 F. It should
be connected close between the FB/OLP pin and the GND pin,
and should be confirmed in actual operation.
Circuit Trace Layout
PCB circuit trace design and component layout affect IC func-
tioning during operation. Unless they are proper, malfunction,
significant noise, and large power dissipation may occur.
Circuit loop traces flowing high frequency current, as shown in
figure 36, should be designed as wide and short as possible to
reduce trace impedance.
In addition, earth ground traces affect radiation noise, and thus
should be designed as wide and short as possible.
Switching mode power supplies consist of current traces with
high frequency and high voltage, and thus trace design and
component layout should be done in compliance with all safety
guidelines.
Furthermore, because an integrated power MOSFET is being
used as the switching device, take account of the positive thermal
coefficient of RDS(on) for thermal design.
Figure 36. High-frequency current loops
Figure 35. FB/OLP pin peripheral circuit
PC1
C3
R
OCP
245
S/OCP FB/OLPGND
STR-Y6700
I
FB
Figure 34. Peripheral circuit around a secondary-side
shunt regulator (U2)
T1 D3
C6
R3
R4
U2
R6
R8
C7
S
PC1
R5
R7
L1
C8
VOUT
GND
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Figure 37 shows practical trace design examples and consider-
ations. In addition, observe the following:
• IC peripheral circuit
(1) Traces among S/OCP pin, ROCP
, C1, T1(primary winding),
and D/ST pin
The traces carry the switching current; therefore, widen and
shorten them as much as possible.
If the IC and the electrolytic capacitor C1 are apart, place a film
capacitor (0.1 F with appropriate voltage rating) close to the IC
or the transformer in order to reduce series inductances of the
traces against high frequency current.
(2) Traces among GND pin, C2(–), T1(auxiliary winding D), R2,
D2, C2(+), and VCC pin
This trace is for supplying voltage to the IC. Widen and shorten
the traces as much as possible. If the IC and the electrolytic
capacitor C2 are apart, place a film or ceramic capacitor
(0.1 to 1.0 F) as close to the VCC pin and the GND pin
as possible.
(3) Current Detection Resistor, ROCP:
Place ROCP as close to the S/OCP pin as possible. In addition,
in order to avoid interference of the switching current with the
control circuit, connect the ground of the control circuit to the
point A in figure 37 as close as possible, with a dedicated trace to
ROCP .
• Secondary side, traces among T1(secondary winding), D3,
and C6
The secondary-side switching current runs through this trace.
Widen and shorten the traces as much as possible.
Thin and long traces cause the series inductance to be high and it
results in high surge voltage on the power MOSFET when it turns
off. Therefore, proper layout pattern design helps to increase the
voltage margin of the power MOSFET to its breakdown voltage
and to reduce power stress and losses in the clamping snubber
circuit.
NF
GND
FB/OLP
S/OCP
V
CC
D/ST
2
175423
STR-Y6700
6
BD
C1
D2 R2
C2
T1 D3
C6
D
P
S
PC 1
C4
R
OCP
C5
C
V
Secondary rectification and
smoothing circuit
Control circuit GND circuit
A
R1
DZ
BD
R
BD1
Clamping Snubber Circuit
V
CC
C3 R
BD2
C
BD
U1
Main circuit
Figure 37. An example schematic of a typical application circuit
28
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Because reliability can be affected adversely by improper storage
environments and handling methods, please observe the following
cautions.
Cautions for Storage
• Ensure that storage conditions comply with the standard
temperature (5 to 35°C) and the standard relative humidity
(around 40 to 75%); avoid storage locations that experience
extreme changes in temperature or humidity.
• Avoid locations where dust or harmful gases are present and
avoid direct sunlight.
• Reinspect for rust on leads and solderability of products that have
been stored for a long time.
Cautions for Testing and Handling
When tests are carried out during inspection testing and other
standard test periods, protect the products from power surges
from the testing device, shorts between adjacent products, and
shorts to the heatsink.
Remarks About Using Silicone Grease with a Heatsink
• When silicone grease is used in mounting this product on a
heatsink, it shall be applied evenly and thinly. If more silicone
grease than required is applied, it may produce stress.
• Coat the back surface of the product and both surfaces of the
insulating plate to improve heat transfer between the product and
the heatsink.
• Volatile-type silicone greases may permeate the product and
produce cracks after long periods of time, resulting in reduced
heat radiation effect, and possibly shortening the lifetime of the
product.
• Our recommended silicone greases for heat radiation purposes,
which will not cause any adverse effect on the product life, are
indicated below:
Type Suppliers
G746 Shin-Etsu Chemical Co., Ltd.
YG6260 MOMENTIVE Performance Materials, Inc.
SC102 Dow Corning Toray Co., Ltd.
Heatsink Mounting Method
• Torque When Tightening Mounting Screws. Thermal resistance
increases when tightening torque is low, and radiation effects are
decreased. When the torque is too high, the screw can strip, the
heatsink can be deformed, and distortion can arise in the product
frame. To avoid these problems, observe the recommended tightening
torques for this product package type, 0.588 to 0.785 N•m
(6 to 8 kgf•cm).
Soldering
• When soldering the products, please be sure to minimize the
working time, within the following limits:
260±5°C 10 s
350±5°C 3 s (solder iron)
• Soldering iron should be at a distance of at least 2.0 mm from the
body of the products
Electrostatic Discharge
• When handling the products, operator must be grounded.
Grounded wrist straps worn should have at least 1 M of
resistance to ground to prevent shock hazard.
• Workbenches where the products are handled should be
grounded and be provided with conductive table and floor mats.
• When using measuring equipment such as a curve tracer, the
equipment should be grounded.
• When soldering the products, the head of soldering irons or the
solder bath must be grounded in other to prevent leak voltages
generated by them from being applied to the products.
• The products should always be stored and transported in our
shipping containers or conductive containers, or be wrapped in
aluminum foil.
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Copyright © 2011-2012 Allegro MicroSystems, Inc.
The products described herein are manufactured in Ja pan by Sanken Electric Co., Ltd. for sale by Allegro MicroSystems, Inc.
Sanken and Allegro reserve the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be re quired to per mit im-
prove ments in the per for mance, reliability, or manufacturability of its prod ucts. Therefore, the user is cau tioned to verify that the in for ma tion in this
publication is current before placing any order.
When using the products described herein, the ap pli ca bil i ty and suit abil i ty of such products for the intended purpose shall be reviewed at the users
responsibility.
Although Sanken undertakes to enhance the quality and reliability of its prod ucts, the occurrence of failure and defect of semi con duc tor products at
a certain rate is in ev i ta ble.
Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems
against any possible injury, death, fires or damages to society due to device failure or malfunction.
Sanken products listed in this publication are designed and intended for use as components in general-purpose electronic equip ment or apparatus
(home ap pli anc es, office equipment, tele com mu ni ca tion equipment, measuring equipment, etc.). Their use in any application requiring radiation
hardness assurance (e.g., aero space equipment) is not supported.
When considering the use of Sanken products in ap pli ca tions where higher reliability is re quired (transportation equipment and its control systems
or equip ment, fire- or burglar-alarm systems, various safety devices, etc.), contact a company sales representative to discuss and obtain written con-
firmation of your spec i fi ca tions.
The use of Sanken products without the written consent of Sanken in applications where ex treme ly high reliability is required (aerospace equip-
ment, nuclear power-control stations, life-support systems, etc.) is strictly prohibited.
The information in clud ed herein is believed to be accurate and reliable. Ap pli ca tion and operation examples described in this pub li ca tion are given
for reference only and Sanken and Allegro assume no re spon si bil i ty for any in fringe ment of in dus tri al property rights, intellectual property rights, or
any other rights of Sanken or Allegro or any third party that may result from its use.
Anti radioactive ray design is not considered for the products listed herein.
Sanken assumes no responsibility for any troubles, such as dropping products, caused during transportation out of Sanken’s distribution network.
The contents in this document must not be transcribed or copied without Sanken’s written consent.
