..,,f,i .. . ,.:.:,;ri, ,..:. , ,,..:,+:. . . . ...4.,, ? >..," .s, ,.. .,. ., c .,. , ,. $ ..., ,. . ., s .,, ...,..., ! .,,.,..,,.. : ..",>.... . .. . . .. . . . ,., ,,, . . . ... . ... . . ., ., ,,, .,,.,, ,, Freescale Semiconductor, Inc. MOTOROLA . .. . . Order this document byBR5091D SEMICONDUCTOR - TECHNICAL DATA .-- .".,., MC68882 :,, .:..$ .,.:1. 3 Floating-Point Freescale Semiconductor, Inc... . $. " :':~.+i `!?< :::,., ,,::? \,}txi\\/.. .,1., ,i..:.:,. ..-..,.3 . >ii}}. ,;.:, Coprocessor The MC68882 floating-point coprocessor fully implements the IEEE Standard for Binary Floatin~_+'',i~'C Point Arithmetic (ANSI-IEEE Standard 754-1985) for use with the Motorola M68000 Family of ,,~f@&~i$ processors. An upgrade of the MC68881, it is pin and software compatible with an optimiz$d ~~$~ interface providing in excess of 1.5 times the performance of the MC68881. It is implem~~~,, ui;ng VLSI technology to give systems designers the highest possible functionality in a ph~:W&~&mali .!.},., ~,,,*.,,,* device. \$.i,,, >$ Intended primarily for use as a coprocessor to the MC68020 or MC68030 32-bi~,~$&@'rocessor unit (MPU), the MC68882 provides a logical extension to the main MPU integer ~~$~~rocessing capabilities. This extension is achieved by providing a very high performan~~oatlng-point arithmetic unit and a set of floating-point data registers which are analogoust$~~t~ &se of the integer data registers. The MC68882 instruction set is a natural extension of a~j $afi~r members of the M68000 Family, and it supports all of the addressing modes of the ~$'~~~. Due to the flexible bus interface of the M68000 Family, the MC68882 can be used wj~~ ari~,of the MPU devices of the M68000 Family and as a peripheral to non-M68000 processors{,{~~ :&+, .,$>. . *), >. $ The major features of the MC68882 are: . :;:,>..+ ..:.?: . Eight general purpose floating-point data register%!,,,*..l,k*, ?P~M.8'tipporting a full 80-bit extended ,,**. precision real data format (a 64-bit mantissa plus ~~,~~ bit, and a 15-bit signed exponent). " -~, . ,J unit to allow very fast cal$ula~~ons~ with intermediate precision greater .3*$;; . format. " ":*\. etc.). . A 67-bit barrel shifter for high-speed s~jfl~~b d~erations (for normalizing o Special purpose hardware for high-#~~&k~"&nversion of binary real memory operands to and A 67-bit arithmetic than the extended from" the internal precision extended . Reduced coprocessor . instructions, . . Forty-six forma~J~$,,~#> interfac$~~wad to increase throughput. includ~n@~~5Jarith metic operations. ~,, \ ,...>.{,., `~. Full conformation to the.#~$~}FEE 754 standard, including all requirements and suggestions, .':'!.., Support of functionsA@"%+,@#ned by the IEEE standard, including a full set of trigonometric and transcendenta~,:t `.':*w, f&ct~ns, .,:s Seven data type$$.'b~e, word and long word integers; single, double, ~$% ,:+ real number$),$ndp-acked binary coded decimal string real numbers. Twenty-t~t~&$,~~tants Virtual @&@@rY/machine available in the on-chip ROM, including and extended n, e, and powers precision of 10, operations. Effi~~<#~~eChanisms for procedure calls, context switches, . ..f\. . Q&fiC&~~ent instruction execution with the main processor. and interrupt handling. ,4*j&QQlurrent instruction execution of multiple floating-point instructions. .`+:~:,$ ,~, ":%.,use with any host processor, on an 8-, 16-, or 32-bit data bus. .,,,,:., *I!<* $fi~: ~>+~~$.il> Y}i:,,,, $ I*> .. ,. ;7 :?, `:.? > This document contains information on a new product. Specifications and information For More Information On This Product, Go to: www.freescale.com @MoToRoLA INC., 1988 . . .. .. ,. herein are subject to change without notice. .. . MOTOROLA @ BRW/Rev. 3 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... THE COPROCESSOR CONCEPT The MC68882 functions as a coprocessor in systems where the MC68020 or MC68030 is the main processor via the M68000 coprocessor interface. It functions as a peripheral processor in systems where the main processor is the MC68000, MC68008, or MC68010. The MC68882 utilizes the M68000 Family coprocessor interface to provide a logical extension of the MC68020 or MC68030 registers and instruction set in a manner which is transparent to the programmer. The programmer perceives the MPU/FPCP execution model as if both devices are implemented on one chip. A fundamental goal of the M68000 Family coprocessor interface is to provide the programmer with an execution model based upon sequential instruction execution by the MC68020 or MC68030 and the MC68882. For optimum performante, however, the coprocessor interface allows concurrent operations in the MC68882 with respect to the MC68020 or MC68030 whenever possible. In order to simplify the programmer's model, the coprocessor interface is designed to emulate, as closely as possible, non-concurrent operation between the MC68020 or MC68030 and the MC68882. The MC68882 is a non-DMA type coprocessor which uses a subset of the general purpose coprocessor interface supported by the MC68020 or MC68030. Features of the interface implemented in the MC68882 are as follows: HARDWARE OVERVIEW The MC68882 is a high performance floating-point device designed to interface with the MC68020 or MC68030 as a coprocessor. This device fully supports the MC68020 or MC68030 virtual machine architecture and is implemented in HCMOS, Motorola's low power, small geometry process. This process allows CMOS and HMOS (high density NMOS) gates to be combined on the sa,,~<~~evice. CMOS structures are used where speed a~@,l~~,~ower is required, and HMOS structures are use~, W%re mini. ::,t.~.,;.i. +~$~ mum silicon area is desired. Using t~,~ W&Whology in..,,.'~> creases speed performance whi~g%~!$g low power consumption, yet still confines th~'~~~~~~1 to .,a reason`~.s,~;. ,"..t+~ ,,j,,'.J-,$\\ I..\.. ably small die size. ,*~-. !~ `k The MC68882 can also Qf ~~,$as a peripheral processor in systems where t@@~~C68020 or MC68030 is not the main processor (e,&};,W&OOO, MC68008, MC68010). The configuration o~$~ ,@68882 as a peripheral processor or coprocqs$@~'m#y be completely transparent to ~,..s ,,,`,~ ` user software (i.e.;%~~'%ame object code maybe executed in either co~~$~::atfon). The ar~&$,~~'re of the MC68882 appears to the user as a lo~i~.,1, e~tension of the M68000 Family architecture, Beca~$@o~the coupling of the coprocessor interface, the ~~fi80'* or MC68030 programmer can view the MC68882 .,.~eg$~ters as though the registers are resident in the #"~68020 or MC68030. Thus, a MC68020 or MC68030 and ` "$~e~ MC68882 device pair functions as one processor with . The main processor(s) and MC68882 communicat~~~~jw' ~~ eight integer data registers, eight address registers, and ~**. via standard M68000 bus cycles. .!> eight floating-point data registers supporting seven float. The main processor(s) and MC68882 cO.~mUti:iing-point and integer data types. cations are not dependent upon the a~@:a&cture The MC68882 programming model is shown in Figures of the individual devices (e.g., instruc@~$~ip&s or 1 through 6 and consists of the following: V;>!]*Q, caches, addressing modes). "..i. , ~).:t.x, `:. .* +f{"i,~ Eight 80-bit floating-point data registers (FPO-FP7). The main processor(s) and MC6@~~~@ay operate These registers are analogous to the integer data ,"~.!.. . ~'x$:'~kl, ,.~\ ~:.,?..:,.. {,m `+< at different clock speeds. .?,$:,,, 7* "''".: registers (DO-D7) and are completely general pur MC68882 instructions util,i~~,a$~~ddressing modes pose (i.e., any instruction can use any register). provided by the main @#o<$#&or. e ~:+~'~\;~, ., *,*$ A 32-bit control register that contains enable bits All effective addreqqb~~q'y%calcu lated by the main for each class of exception trap, and mode bits to processor at th~t~~~si~ of the coprocessor. set the user-selectable rounding and precision modes. All data tran~fdxk$:~~e performed by the main processor at ~~'~we~uest of the MC68882. .*:\,ij+p,,\:t Overla~@ ft'bncurrent) instruction execution enhan~,~~?~bughput while maintaining the prog&~t@~*~r's model of sequential instruction ~f3%$BNt ion, ,,:,~'~~~~~dprocessor detection of exceptions which require ` ,J:gt, ........ a trap to be taken are serviced by the main pro8::'i\iJ..,tJ?~. . ..:..$,,>9. cessor at the request of the MC68882. ~lt~. .;. > Support of virtual memory/virtual machine systerns is provided via the FSAVE and FRESTORE instructions. Up to eight coprocessor simultaneously. Multiple type are allowed. may reside in a system coprocessor of the same . Systems may use software emulation of the MC68882 without reassembling or relinking user software. .. ,..- A 32-bit status register that contains floating-point condition codes, quotient bits, and exception status information. A 32-bit instruction address register that contains the main processor memory address of the last floating-point instruction that was executed. This address is used in exception handling to locate the instruction that caused the exception, The connection between the MC68020 or MC68030 and the MC68882 is a simple extension of the M68000 bus interface. The MC68882 is connected as a coprocessor to the MC68020 or MC68030, and the selection of the MC68882 is based on a chip select which is decoded from the MC68020 or MC68030 function codes and address bus. Figure 7 illustrates the MPU/coprocessor configuration. As shown in Figure 8, the MC68882 is internally divided into three processing elements: the bus interface unit For More Information On This Product, Go to: www.freescale.com MOTOROU 2 ,p p \.; M~ BRW/Rev. 3 ,. -, ,~, `./ Freescale Semiconductor, Inc. 7 I FPO I t FP1 \ I I FP2 I , I FP3 r FP4 I FLOATING POINT DATA REGISTERS Freescale Semiconductor, Inc... FP5 ~ ROUNOING 00 01 10 11 MOOE: TO NEAREST TOWARD ZERO TOWARD MINUS INFINIW TOWARD PLUS INFINIV ROUNDING PRECISION: 00 EXTENDED 01 SINGLE 10 DOUBLE 11 (UNDEFINEO, RESERVEO) Figure MCBRW/Rev, 3. Mode Control B~e For More Information On This Product, Go to: www.freescale.com 3 MOTOROM 3 Freescale Semiconductor, Inc. 31 30 29 2a 27 26 25 24 N z I NAN o [ NOT A NUMBER lNFINl~ ZERO NEGATIVE Figure 4. Condition Code B~e 23 I s 22 21 20 19 la 17 16 QUOTIENT I Freescale Semiconductor, Inc... 1 Figure 5, Quotient B~e For More Information On This Product, Go to: www.freescale.com OR UNORDERED Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. (BIU), the conversion unit (CU), and the arithmetic proccycle. (The function codes are generated by the M68000 essing unit (APU). The BIU communicates with the Family processors to identify eight separate address MC68620 or MC68030, the CU performs data conversion spaces.)" Thus, the memory-mapped coprocessor interFor binary real data formats, and the APU executes all face registers do not infringe upon instruction or data MC68882 instructions. address spaces. The MC68020 or MC68030 places a coThe BIU contains the coprocessor interface registers processor ID field from the coprocessor instruction onto three of the upper address lines during coprocessor ac(CIRS). In addition to these registers, the register select and DSACK timing control logic is contained in the BIU. cesses. This ID, along with the CPU address space funcFinally, the status flags used to monitor the status of tion code, is decoded to select one of eight coprocessor communications with the main processor are contained in the system. ~~~~.~l, in the BIU. Since the coprocessor interface protocol is ba~~wlely The CU contains special purpose hardware that peron bus transfers, the protocol is easily ernu~?~q~~y softforms data format conversions between binary real data ware when the MC68882 is used as a perl,~~:~~ktiith any formats to and from `the internal extended format. The processor capable of memory-mapped @+@yaTan M68000 CU relieves the APU of a significant work load and allows style bus. When used as a periphe$$.@r@ssor with the the MC68882 to execute data movement and preparation 8-bit MC68008, the 16-bit MC68,R{:~$r?he .MC68010, all functions concurrently with arithmetic and transcendenMC68882 instructions are trapp~$:$ the main processor tal calculations, to an exception handler at g$$cut?~n time. Thus, the softThe eight 80-bit floating-point data registers (FPO-FP7) ware emulation of the c~~~~~$~or interface protocol can and the 32-bit control, status, and instruction address be totally transparent%~~:t~&Wser. The MC68882 can preregisters (FPCR, FPSR and FPIAR) are located in the APU. vide a performancetW~~.@ for MC68000-based designs In addition to these registers, the APU contains a highby changing the `T~%~@'*processors to the MC68020 or speed 67-bit arithmetic unit used for both mantissa and MC68030. Th,~~pftMre migrates without change to the exponent calculations, a barrel shifter that can shift from next gener&k$&#$eq uipment using the MC68020 or 1 bit to 67 bits in one machine cycle, and ROM constants MC6803@s"':?JW' (for use by the internal algorithms or user programs). Sin@'J%&$s is asynchronous, the MC68882 need not The control section of the APU contains the clock genru~.at~g same clock speed as the main processor. Total erator, a two-level microcode sequencer, the microcode ,J,~$&~~mperformance may therefore be customized. For a : Weti CPU performance requirement, the floating-point ROM, and self-test circuitry. The built-in self-test capabilities of the MC68882 enhance reliability and ease man- S+~&.$@'iformance can be selected to meet Particular Price/ ufacturing requirements; however, these diagnost~~~%k~ performance specifications, running the MC68882 at functions are not accessible outside of the special test `t slower (or faster) clock speeds than the MPU clock. COPROCESSOR INTERFACE ,, s~i;,y+,.>~. All communications between the MC68@~~OFWC68030 and the MC68882 occur via standard M@~~Q:@>amily bus The MC68882 is design,~t~~~~~erate on 8-, transfers, :f},\,.*7.~: >~$iy, .\\<.. 16-, or 32-bit data buses. p? The MC68882 contains a nu@b#~.~coprocessor interface registers (CIRS) that ar~.~~r$ised in the same manner as memory by the rnai~~~~essor. The M68000 Family coprocessor interface.r$<!#~@emented via a protocol of reading and writing t$$~#se registers by the main processor. The MC6@:~0 anfl MC68030 implement this gen~'`.:!$ ,~~ ..+ eral purpose co~ra$~ssor interface protocol in hardware and microc~$~,$~~~ ~ WhenJh*~$~&68020 or MC68030 detects a general type MC68&Q~~~s?tuction, the MC68020 or MC68030 writes the,i@tru$~on to the memory-mapped command CIR and r~S&%l~&response CIR. In this response, the BIU encodes `+':t .:.:.~':~'.t~. ~i%{e$~ests for any additional action required of the MC68020 "$.@~C68030 on behalf of the MC68882. For example, the `%sponse may request that the MC68020 or MC68030 fetch an operand from the evaluated effective address and transfer the operand to the operand CIR. Once the MC68020 or MC68030 fulfills the coprocessor request(s), the MC68020 or MC68030 is free to fetch and execute subsequent instructions. The only difference between a coprocessor bus transfer and any other bus transfer is that the MC68020 or MC68030 issues a CPU address space function code during the The M68000 Family coprocessor interface is an integral part of the MC68882 and MC68020 or MC68030 designs. The interface partitions MPU and coprocessor operations so that the MC68020 or MC68030 does not have to cornpletely decode coprocessor instructions, and the MC68882 does not have to duplicate main processor functions (such as effective address evaluation). This partitioning provides an orthogonal extension of the instruction set by permitting MC68882 instructions to utilize all MC68020 or MC68030 addressing modes and to generate execution time exception traps. Thus, from the programmer's view, the MPU and coprocessor appear to be integrated onto a single chip. While the execution of the great majority of MC68882 instructions may be overlapped with the execution of MC68020 or MC68030 instructions, concurrency is completelytransparent to the programmer. The MC68020 and MC68030 single-step and program flow (trace) modes are fully supported by the MC68882 and the M68000 Family coprocessor interface. While the M68000 Family coprocessor interface permits coprocessor to be bus masters, the MC68882 is never a bus master. The MC68882 requests that the MC68020 or MC68030 fetch all operands and store all results. In this manner, the MC68020 and MC68030 32bit data bus provides high speed transfer of floating-point operands and results while simplifying the design of the MC68882. For More Information On This Product, Go to: www.freescale.com f CLK ! For More Information On This Product, Go to: www.freescale.com @'n .*,, SAVE CIR RESTORE CIR CIR I .,..,), , t 4 I AA CIR 1 h ,!, ! Simplified Block Diagram BUILT IN SELF TEST REGISTERS : .+. `.,!,: .$? `$<. ,,:$' ~:<,,,.* \ ,~,f.**,.,* .\}$ .,.s,, .,:>, ` i+j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .* Figure 8. MC68882 S, D, X FORMAT CONVERSION L~lC ................................................................. `) .,>, ,t!, COMMAND/CONDITION STATUS FLAGS t RESPOWE CIR ................................................................. RESPONSE PLA 1 .?.%$!,? .l.~~:~ ..,, 1 L .,,,,,\:{.' f<, - -1 a. u .- CONTROL BIU .................................................................................................... Freescale Semiconductor, Inc... NROM I ................................. ,, APU ........................ Freescale Semiconductor, Inc. ,, .. . ... ..,.. ,. Freescale Semiconductor, Inc. Since the coprocessor interface is based solely upon potentially fully concurrent and, therefore, can be combus cycles (to and from CPU space) and the MC68882 is pletely executed during the execution of a previous innever a bus master, the MC68882 can be placed on either struction. the logical or physical side of the system memory manThe MC68882 also has a more optimized coprocessor agement unit in an MC68020-based system. Since the interface than the MC68881. If an arithmetic instruction memory management unit of the MC68030 is on-chi~, has data formats of Single, Double or Extended, the dialthe MC68882 is-always on the physical side of the mern~ ogs are designed to increase the potential overlap with ory management unit in an MC68030 system. subsequent instructions, This overlap can significantly The virtual machine architecture of the MC68020 or decrease the effective instruction execution time. MC68030 is supported by the coprocessor intetiace and the MC68882 through the FSAVE and FRESTORE instructions. If the MC68020 or MC68030 detects a page fault and/or a task time out, the MC68020 or MC68030 can force the MC68882 to stop whatever operation is in progress at any time and save the MC68882 internal state in memory, During the execution of a floating-point instruction, the MC68882 can stop at predetermined points as well as at the completion of the instruction. The size of the saved internal state of the MC68882 is Double Precision Rga~~~~N' dependent upon the state of the APU at the time the Extended Precisi~~,~<$PIX) FSAVE is executed, If the MC68882 is in the reset state Packed Decimal"t~$@~'Real (P) when the FSAVE instruction is received, only one word The capital letter<~$$~%ined in parentheses denote sufof state is transferred to memory, which may be examfixes added .~d}$~:troctions in the assembly language ined by the operating system to determine that the cosource spW~l@~~fhe data format to be used. processor programmer's model is empty, If the *" .~y. ,$ $*,,, coprocessor is in the idle state when the save instruction lNTE~~:~A$A FORMATS is received, only a few words of internal state are trans~~e t~be integer data formats (byte, word, and long ferred to memory. If executing an instruction in the busy ,,,~~oral. are the standard twos complement data formats state, it may be necessary to save the entire internal state in the M68000 Family architecture. Whenever of the machine, Instructions completing execution in less , $,sd$ported operation, the intime than it takes to save the larger state in mid-instrucl~c?~~~c,"&~ integer is used in a floating-point converted by the MC68882 to an tion are allowed to complete execution and then save the "'" `I+i,`"'''''''tiger is automatically extended precision floating-point number before being idle state, Thus, the size of the saved internal state is kepl used. For example, to add an integer constant of five to to a minimum. The ability to utilize several inter~~y, state sizes greatly reduces the average conte"xt switch~~g~tie. the number contained in `floating-point data "register 3 (FP3), the following instruction can be used: The FRESTORE instruction permits reloa~i'k~~k%n internal state that was saved earlier and co~~~q.~ any opFADD.W #5,FP3 eration that was previously suspende~. ~~,~&~STORE of (The Motorola assembler syntax "#" is used to the null state frame re-establishes d~~b$~@pister values, denote immediate addressing.) a function identical to the MC68w ~rdware reset, The ability to effectively use integers in floating-point ,\L: ~,..::,**\~\> ,.:~$~. operations saves user memory since an integer repreMC68882 PERFORMANCE ~~@@EMENTS ~:\., sentation ofa number, if representable, is usually smaller The high performanceKo$:~h$iMC68882 is the result of than the equivalent floating-point representation. the MC68882'S abilty $* ~~cute multiple floating-point instructions concu,$$ent?~gF~he direct result of concurFLOATING-POINT DATA FORMATS rency is to utilize$~~~~rithmetic Processing Unit (APU) The floating-point data formats, single precision (32more efficient~,{b~~'@&creasing its idle time. bits) and double precision (64-bits), are defined by the When th~;~,t*82 receives an instruction, the BIU, IEEE standard. These data formats are the main floatingalong wit~~@~~@U, can initiate the instruction, fetch the point formats and should be used for most calculations necesWW ~erands, and convert them to the internal involving real numbers, Table 1 lists the exponent and extq,~$~~,.,$rmat even though the APU is busy completmantissa size for single, double, and extended precision, ins~s%s~ution of a previous instruction. Although the The exponent is biased, and the mantissa is in sign and t&&~81 can only instruct the main processor to wait if magnitude form. Since single and double precision re~&''~PU is busy, the MC68882 CU can proceed with the quire normalized numbers, the most-significant bit of the n~xt instruction. When the APU is finally ready to perform mantissa is implied as a one and is ndt included, thus the calc(~lation. ., -------it can dn sn -- imm~diatelv without incurgiving one extra bit of precision, ring delav due to data movement and preparation funcThe extended precision data format is also in conformtio;s. ` ante with the IEEE standard, but the standard does not Another factor in obtaining increased performance in specify this format to the bit level whereas it does for the MC68882 is the oDtimized FMOVE instructions for single and double precision. The memory format on the binary real data formats. These FMOVE instructions execute twice as fast as the corresponding FMOVE instrucMC68882 consists of 96 bits (three long words), Only 80 tions of the MC68881, The FMOVE instructions are also bits are actually used; the other 16 bits are for future Freescale Semiconductor, Inc... 5% -'<..-Y !...,,,. ~r.: \ :<21 For More Information On This Product, Go to: www.freescale.com MC= BR~/Rov. .,-, MOTOROU 3 7 ,. . . .- . .. ... .. . ,, ,,, - ,, ,,. ,, ,,. . ,.. . ... . ... . .... . .. . . .. ... . ..- .. ... ... . Freescale Semiconductor, Inc. Table 1. Exponent and Mantissa Sizes Freescale Semiconductor, Inc... Data Format Exponent Bits Mantissa Bits Bias 127 Single 8 Double 11 52(+1) 1023 Extended 15 64 16383 23(tl) expandability and for long-word alignment of floatingpoint data structures. Extended format hasa 15-bit exponent, a 64-bit mantissa, and a l-bit mantissa sign. Extended precision numbers are intended for use as temporary variables, intermediate values, or in areas where extra precision is needed, For example, a compiler might select extended precision arithmetic for evaluation of the right side of an equation with mixed sized data and then convert the answer to the data type on the left side of the equation. It is anticipated that extended precision data will not be stored in large arrays due to the amount of memory required by each value. registers always contain extended precision values. All operands used are converted to extended precision by the MC68882 before a specific operation is performed, and all results are in extended precision. The use of extended precision ensures maximum accuracy without sacrificing performance. Refer to Figure 9 for a summary of the memory formats for the seven data formats supported by the MC68882. ~~*~.*. ...... $,*, f!'}~{,?.(,!~tt., :*, ,.;,~y`..~j,, ~\$\,.. ~$., , ../,." ~.:, .,. 1$.,1 P 4;3 The MC68882 instruction classes: 1. Moves between set ist&~~$~8&d intO SiX major `<k:\, :i \:v:p the,~~&8882 and memory or the MC68020 or MC$@~@A 2. Move multipl~t~[~i$~ers 3, Monadic and out), (in and out), og~~~@*s, PACKED DECIMAL STRING REAL DATA FORMAT The packed decimal data format allows packed BCD strings'to be transferred to and from the MC68882. The ,:~~~Qn$ll moves from memory (or from an MC68020 or strings consist of a 3-digit base 10 exponent and a 17$. ~'~g68030 data register) to the MC68882, data is converted digit base 10 mantissa. Both the exponent and mantissa., ~:t ~i$V:@4rom the source data format to the internal extended prehave a separate sign bit. All digits are packed BCD; an t:; ~~ cision format. On all moves from the MC68882 to memory entire string fits in 96 bits (three long words). As is th~. (or, to an MC68020, or .MC68030 data register), data is case with all data formats when packed BCD str~,~$ are converted from the internal extended precision format to supplied to the MC68882, the strings are auto~atrwally the destination data format. Note that data movement converted to extended precision real valuP@~$$,*$ coninstructions perform arithmetic operations, since the reversion allows packed BCD numbers to be~~~~~% inputs ..,{$!!: ~a, ~,f\ suit is always rounded to the precision selected in the ~.i:;.+i:>,~ :? to any operation. For example: .:;:':. "1., .~.i*.. FPCR mode control byte. The result is rounded using the FADD.P #-6.023E + ~~$w selected rounding mode and is checked for overflow and BCD numbers can be output$~~.~,%~e MC68882 in a underflow. generated format readily used for printingb~~program The syntax for the move is: by a high-level language c,~w~h~! For example: FMOVE.<fmt> <ea>,FPn .Move to MC68882 FM OVE,P ,@&~$.Q@FFER{# - 5} FMOVE.<fmt> FPm,<ea> Move from MC68882 Move within MC68882 FMOVE.X FPm,FPn This instruction con$~t@ the floating-point data regwhere: ister 3 (FP3) cont~~{~. intd a packed BCD string with five <ea> is an MC68020 or MC68030 effective address digits to the rigHt&~t#& ,{>$,.~i: decimal point (FORTRAN F for~?,~ ,,,. ,.?~~ operand. mat). .,~~. t$s,,} .,.$,.',\,\ ?$;, .\k,, ,<fmt> is the data format size. FPm and FPn are floating-point data registers. ~;...:, ~ ~.,,, $$?~~~t~'formats described above are supported orthB~Q"flBlly by all arithmetic and transcendental opera$~~&*and by all appropriate MC68020 or MC68030 ~dressing modes. For example, all of the following are legal instructions: FADD.B #O,FPO FADD.W D2,FP3 FADD.L BIGINT,FP7 FADD.S #3.14159,FP5 FADD.D (SP) + ,FP6 [(TEMP-PTR,A7)], FP3 FADD.X FADD.P #1.23 E25,FP0 Most on-chip calculations are performed in the extended precision format, and the eight floating-point data MOVE MULTIPLE REGISTERS The floating-point move mul~iple instructions on the MC68882 are much like the integer counterparts on'the M68000 Family processors. Any set of the floating-point registers FPOthrough FP7 can be moved to or from memory with one instruction. These registers are always moved as 96-bit extended data with no conversion (hence no possibility of conversion errors). Some examples of the move multiple instruction are as follows: (ea>,FPO-FP3/FP7 FMOVEM FP21FP41FP6,<ea> FMOVEM The move multiple instructions are useful during context switches and interrupts to save or restore the state For More Information On This Product, Go to: www.freescale.com Q; Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 94 91 80 0 . . . . . 17-DIGIT jMANTISSA;!:~j~; . . . . : : . :.. ~ : : ~ : . . . PACKED DECIMAL REAL ,.:$:.t. ~, ~~:~,~. *I,, ,.,,.,.*,. Figure 9. MC68882 Data Format Summary `..\..i:$\*.~~ .,*.?::$:$ >,,, ~, >,,, %*,$\$r. ....., *,*\,>~\ .a*t&\ i::,, .St,, $.,,, .,. >1> .,>> :~; MONADIC OPERATIONS o~a program. These moves are also useful at the start and end of a procedure to save and restore the register Monadic operations have one operand. This operand set of the calling routine, In order to reduce procedure may be in a floating-point data register, memory, or in call overhead, the list of registers to be saved or restored an MC68020 or MC68030 data register. The result is alcan be contained in a data register thus enabling runways stored in a floating-point data register. For example, time optimization by allowing a called routine to save as the syntax for square root is: few registers as possible, Note that no rounding or ovFSQRT.<fmt> <ea>,FPn or, erflow/underflow checking is performed by these operFSQRT.X FPm,FPn or, ations, FSQRT.X FPn For More Information On This Product, Go to: www.freescale.com \ Freescale Semiconductor, Inc. The MC68882 monadic operations available are as fol- Freescale Semiconductor, Inc... lows: FABS FACOS FASIN FATAN FATANH FCOS FCOSH FETOX FETOXMI FGETEXP FGETMAN FINT FLINTRZ FLOGIO FLOG2 FLOGN FLOGNPI FNEG FSIN FSINCOS FSINH FSQRT FTAN FTANH FTENTOX FTST FTWOTOX Absolute Value Arc Cosine Arc Sine Arc Tanqent Hyperb&ic Arc Tangent Cosine Hyperbolic Cosine e to the x Power e to the X Power -1 Get Exponent Get Mantissa Integer Part Integer Part (Truncated) Log Base 10 Log Base 2 Log Base e Log Base e of(x + 1) Negate Sine Simultaneous Sine and Cosine Hyperbolic Sine Square Root Tangent Hyperbolic Tangent 10 to the x Power Test 2 to the x Power the necessary condition checking and reports to the MC68020 or MC68030 whether the condition is true or false. The MC68020 or MC68030 then takes the appropriate action. Since the MC68882 and MC68020 or MC68030 are closely coupled, the floating-point branch operations execute very quickly. The MC68882 conditional operations are: Branch FBCC Decrement and Branch,. ~$:<~ FDBcc Set According to CoQQi~~~S FSCC Trap-on Condition ~' $'! " FTRAPcc (with an Opti~"~l~~&?#meter) ~:. ,~* ./.J!:{&, ,+*~ !.,*Q: * ?,. where: cc is one of the 32 floatind~@n$-~Onditional test specifiers as given in~%~~~@' **..*. . 1.$.,fy `.,., >~/. ~!?L.:i::~ ,7.. ,} \;h \,,y~\ ~...<,.,, \~:'''\%:., *;t Table 2. ,@~fi,~?-Point Conditional ,e~;~~ Specifiers `..., ..... $~:: r Q;.> ~.:...> Definition Mnemo@$"~,,,:,,, ",,, .:\'.$$..\.\ `::,,. . -~ *L ,$, \~,.i~ NOTE \ ~.~~,.a ,,.,{: T@~$@lFB~lngconditional tests do not set the BSUN bit .%&int~g, status register exception byte under any circum`%$~tances. >;):.'. . False f:.. j F" &;i ,ih;,~<+ Equal \$y[.::\k, ~ EQ >.. `~>' Ordered Greater Than OGT ~~ ..*: ,.,, Ordered Greater Than or Equal OGE .... .J,, ~.+is Ordered Less ,Tha.n OLT DYADIC OPERATIONS ~~,':~ ::\. Ordered Less Than or' Equal OLE Dyadic operations have two operands e~$~$~'~~ first Ordered Greater or Less Than OGL operand is in a floating-point data regis\@Y, %?~orYt or Ordered OR an MC68020 or MC68030 data registe~~'$:~~.:;~cond oPUnordered UN erand is the contents of a floating-p~~f$~~~% register. The Unordered or Equal UEQ Unordered or Greater Than UGT destination is the same floating-p~$~%.~%ta register used Unordered or Greater or Equal UGE for the second operand. For ex~&~l,~the syntax for float*,W,, , , i.. Unordered or Less Than ULT ing-point add is: Unordered or Less or Equal ULE <~pP;&$ FADD.<fmt> Not Equal NE FADD.X .~~,~~n True T The dyadic oPeratiom$~/$@Table with the MC68882 are as ,.,..>,:2$ follows: NOTE ,Fi:}'~"h .<.:. FADD ~,.:,..,,?$~ , ` ,l&A d d All the conditional tests below set the BSUN bit in the FCMP,$Y2]Y, `;$r" Compare status register exception byte if the NAN condition code FD,~~$;\;* Divide bit is set when a conditional instruction is executed. Modulo Remainder F~,@J> Signaling False SF i$y~~ Multiply Signaling Equal SEQ IEEE Remainder ik~5Q$M Greater Than GT Scale Exponent *$~*FSCALE Greater Than or Equal GE ?**T::.<,..*,. ..y Single Precision Divide FSGLDIV .\$., ~: Less Than LT ;,\,:, .;.,,.: "\/.$, Single Precision Multiply FSGLMUL Less Than or Equal LE FSUB Subtract Greater or Less Than GL Greater Less or Equal GLE Not {Greater, Less or Equal) NGLE BRANCH, SET, AND TRAP-ON CONDITION Not (Greater or Less) NGL Not (Less or Equal) NLE The floating-point branch, set, and trap-on condition Not (Less Than) NLT instructions implemented by the MC68882 are similar to Not (Greater or Equal) NGE the equivalent integer instructions of the M68000 Family Not (Greater Than) NGT processors, except more conditions exist due to the speSNE Signaling Not Equal cial values in IEEE floating-point arithmetic. When a conSignaling True ST ditional instruction is executed, the MC68882 performs For More Information On This Product, Go to: www.freescale.com MOTOROLA 10 ,..,..,,,; ... .. .. . . . ,,. MCBRW/Rev. ,.. 3 , . .. . .. .. ... ,. .. . Freescale Semiconductor, Inc. MISCELLANEOUS INSTRUCTIONS Miscellaneous instructions include moves to and from the status, control, and instruction address registers, Also included are the virtual memory/machine FSAVE and FRESTORE instructions that save and restore the internal state of the MC68882. FMOVE <ea>, FPcr Move to Control Register(s) FMOVE FPcr,<ea> Move from Control Register(s) FSAVE <es> Virtual Machine State Save FRESTORE <es> Virtual Machine State Restore Freescale Semiconductor, Inc... ADDRESSING unique format word prevents a saved MC68881 context from being restored into an MC68882 and vice versa. Second, the BSUN (Branch or Set on Unordered), SNAN (Signaling Not-A-Number), OPERR (Operand Error), OVFL (Overflow), DZ (Divide by Zero) and INEX (Inexact result) floating-point exception handlers must have these minimum requirements: 1. An FSAVE must be executed floating-point instruction, before any other ..~~~.j$ 2, A BSET or sjmilar instruction that sets'~~%1 of the BI U flag word (located in the sa~~~J~T& state `..`Stk, ::>.. ~...(i:,$.' <. itl?,)$,, frame), MODES 3. An FRESTORE instruction fore the RTE instruction. mus$~~i>kecuted ~~,,o +t':s ..*1,> . .:.~! ,t>.?:.~~$ \\`.<.! be- The MC68882 does not perform address calculations, Thus, if the MC68882 instructs the MC68020 or MC68030 The above requirements are ~&J<~p]icable to interrupt to transfer an operand via the coprocessor interface, the handlers that do not conta~d~ny'%oating-point instrucMC68020 or MC68030 performs the addressing mode caltions. For interrupt hand~~~~wt have floating-point incubations requested in the instruction, In this case, the structions, only req~?~gmnts #1 and #3 must be ,.3M ,:,. * ~.+ ,..,, instruction is encoded specifically for the MC68020 or ~~t,~ *<>,*, implemented. \.$\.h .. *;!$*N ,,.~:$? MC68030, and the execution of the MC68882 is depend~$'&,\ ~,:i ,1,$,, `~$+:$ ent only on the value of the command word written to the MC68882 by the main processor. SIGNAL DESCRIPTIONS FMN~~@~ ~,c This interface is flexible and allows any addressing j; ,>. ,!s'.!..?,~,$ 1' mode to be used with floating-point instructions, For the The$~.UoWtng paragraphs contain a brief description M68000 Family, these addressing modes include imofj~e iti~,ut and output signals for the MC68882 floatingmediate, postincrement, predecrement, data or address ~~~~~,coprocessor. The signals are functionally organized register direct, and the indexedfindirect addressing modes rY'~fi@ groups as shown in Figure 10. of the MC68020 and MC68030. Some addressing modes ~k;%k:,,f~ are restricted for instructions consistent with the M6800&$Y;~$,:j NOTE Family architectural definitions (e.g.; program counter "'ik, The terms assetiion and negation are used extenrelative addressing is not allowed for a destination o~~ sively to avoid confusion when describing "active,7{!'*:, . -> ., erand). ~s? low" and "active-high" signals. The term assert or :~:.,., The orthogonal instruction set of the MC6~$&~$the assertion is used to indicate that a signal is active flexible branches and addressing modes o&~~~~r68020/ or true, independent of whether that level is repMC68030 allow a programmer or a cQ~p~&''writer to resented by a high or low voltage. The term negate think of the MC68882 as though it is,,~~$~fithe MC68020 or negation is used to indicate that a signal is inor MC68030. There are no specia~ `~~t~$cllons imposed active or false. by the coprocessor interface, ~~'~;~$j~ating-point arithmetic is coded exactly like inta$erjarithmetic. ADDRESS BUS (AO through A4) ,,,,:s.,:,.id.:,~,\. !::,'`~*,*., ~.~ These active-high address line inputs are used by the \.$~ ,,`:*1** ,i.$l+ ,~t. ,'.,.1, . `.-, .:,:, main processor to select the coprocessor interface reg.~,\p\+ ister locations located in the CPU address space. These MC6W8PQ6MPATIBILITY .>$:,.d~" lines control the register selection `as listed in Table 3. ,,~ :,:-: ..,"+ Using the ~~~,~~~~n an existing MC68881 socket does not require&@~~*are changes nor user-software modi"Cc / 7 AO-A4 fications;<~J~@~entation of multiple floating-point in1 GNO * 13 structi@W ~~~cution concurrency gives the MC68882 a per~~'@&e advantage over the MC68881. However, to DO-D31 g~.,~mtee that the floating-point exception model mainMC6B882 ~~~~~~the precepts of a sequential execution model, some m FLOATING-POINT ~~stems-level software modifications are needed to up4 COPROCESSOR fl~ grade the system to operate properly with an MC68882. 4 First, note that the idle and busy state frames (generCLK E P * ated by the FSAVE instruction) are both 32 bytes larger m E * with the MC68882 than the MC68881, The offsets for the RESET DSACKO exceptional operand, the operand register word, and the > * SENSE DSACK1 > BIU flag word from the top of the saved idle state frame + * are 32 bytes more than that of the MC68881. However, a unique format word is generated by the MC68882 ensbling the system software to detect this difference. The Figure 10. MC68882 Input/Output Signals For More Information On This Product, Go to: www.freescale.com MCBRW/Rev. 3 ,.,,, .7.. .,.,.,.,,,........... ... .... . ..... ...... .,,.,,...,, . ......... . .. .. ..,, .,.,,. .. ........ . ., ..,,, ,, .,. ,," MOTOROLA 11 ... .. . . ,,, ,,.. .. .. . ,,. .. ..... . . .,, .. .. . ...... . .... . >..,..,,.. ............... ..... .,.."...,., ,,,..,.,,, .,...,.. .,.................;,..,.,,, ,, ,,, ,., . ,,,. .;, ., ..< ,., ....- Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 3. Coprocessor Intetiace Register Selection This active-low input signal indicates that there is a valid address on the address bus, and both the chip select (CS) and read/write (R~) signal lines are valid. A4-AO Offset Oooox $00 16 Read Response Ooolx $02 16 Write Control CHIP SELECT (CS) Oolox $04 16 Read Save Oollx $06 16 R~ Oloox $08 16 - (Reserved) Ololx $OA 16 Write Command Ollox $Oc 16 - (Reserved) Olllx $OE 16 Write Condition 1Ooxx $10 32 Rfi Operand 101OX $14 16 Read Register Select Iollx $16 16 11Oxx $18 32 Read Instruction Address Illxx $lC 32 RR Operand Address This active-low input signal enables the main processor access to the MC68882 coprocessor interface registers. When operating the MC68882 as a peripheral pro$essor, the chip select decode is system dependent (i.~~~j~$the "..., .\\!.+'*: >},i,~ ?? chip select on any peripheral). ..$'s,*k. ~;, .?;.l\ .,,.\$, ~\...:~ *;>K:,, `:3,."~~ `%$,, READ/WRITE (R/~) ,h+.t.::~, . !,.'.t..i~..,! This input signal indicates the di~~8]o~#@Y a bus transaction (read/write) by the main~f~~~sbr. A logic high (1) indicates a read from the @8,@~, an~ a logic low (0) indicates a w~te to the ~~~8&The RN signal must be valid when AS is ass@Xl@+~j: ~..+ ".**,?,)$.!+ .`X., ,,\ -$: ~:<:~,.. ..,/ , DATA STROBE (DS)':Xj~,~,t.$~ ,;~.>t,, . ,>+f, This active-lowin:~~~ignal indicates that there is valid Mdth Register ADDRESS STROBE (AS) Type - Restore (Reserved) data on the d~~~:~ys When the MC68882 is configured to operate over an 8bit data bus, the AO pin is used as an address signal for byte accesses of the coprocessor interface registers. When the MC68882 is configured to operate over a f16- or 32bit system data bus, both the AO and the SIZE pins are strapped high and/or low as listed in Table 4. r .::.:Y during a write bus cycle. `?, ~Kese active-low, three-state output signals indicate ..?~,,c&hpletion of a bus cycle to the main processor. The i$$it,~@8882 asserts b~h the DSACKO and DSACKI signals *$rS$$upon assertion of CS. Table 4. System Data Bus Size Configuration `-l?+ If the bus cycle is a main processor read, the MC68882 ~i$t Data Bus ~ ,:' AO SIZE asserts DSACKO and DSACKI signals to indicate that the ,$~$' .; `>:,}, information on the data bus is valid. (Both DSACK signals -- 8-Bit Low .tt,. *>:.,. ..*.,,,* ,,.,,, may be asserted in advance of the valid data being placed 16-Bi~$$'Q$y`?' Low High on the bus. ) If the bus cycle is a main processor write to .,?, ... :. 3~*qk$;,.~' High High the MC68882, DSACKO and DSACKI are used to acknowl.~~,;~y$. edge acceptance of the data by the MC68882. ,. `\\.~J~.\ .'~:i,> ,,..:.. The MC68882 also uses DSACKO and DSACKI signals ,,,4). > ` `%;V, $~$ to dynamically indicate to the MC68020/MC68030 the DATA BUS (DO through D31 ) ~~" `"~~ "port" size (system data bus width) on a cycle-by-cycle This 32-bit, bidirectional, +~k~%%~bte bus serves as the basis, Depending upon which of the two DSACK pins are general purpose data,~~~h,~etween the MC68020/ asserted in a given bus cycle, the MC68020/MC68030 asMC68030 and the MC~~&~.'''Regardless of whether the sumes data has been transferred to/from an 8-, 16-, or MC68882 is operat~d a~$~'coprocessor or a peripheral 32-bit wide data port. Table 5 lists the DSACK assertions processor, all in~,@$@o,gessor transfers of instruction inthat are used by the MC68882 for the various bus cycles formation, op~r,~~d$$~ata, status information, and reover the various system data bus configurations. quests for $~~J~@'&ccur as standard M68000 bus cycles. Table 5 indicates that all accesses over a 32-bit bus The MQ@,*~will operate over an 8-, 16-, or 32-bit where A4 equals zero are to 16-bit registers, The MC68882 syste~%at%~,bbs. Depending upon the system data bus implements all 16-bit coprocessor interface registers on conJ~@~~{a@n, both the AO and SIZE pins are configured data lines D16-D31 (to eliminate the need for on-chip s~:~?t~a"lly for the applicable bus configuration. (Refer to multi plexers); however, the MC68020/MC68030 expects :$Q~*ESS BUS (AO through A4) and SIZE (SIZE) for fur16-bit registers that are located in a 32-bit port at odd `&#rdetails). word addresses (Al = 1) to be implemented on data lines $$j DO-DI 5. For accesses to these registers when configured SIZE (SIZE) for 32-bit bus operation, the MC68882 generates DSACK signals as listed in Table 5 to inform the MC68020/ This active-low input signal is used in conjunction with MC68030 of valid data on D16-D31 instead of DO-D15. the AO pin to configure the MC68882 for operation over An external holding resistor is required to maintain an 8-, 16-, or 32-bit system data bus. When the MC68882 both DSACKO and DSACKI high between bus cycles. In is configured t~erate over a 16- or 32-bit system data order to reduce the signal rise time, the DSACKO and bus, both the SIZE and AO pins are strapped high and/or DSACKI lines are actively pulled up (negated) by the low as listed in Table 4. For More Information On This Product, Go to: www.freescale.com ~:- ... Freescale Semiconductor, Inc. Table 5. DSACK Assertions Data bus A4 DSACKI DSACKO 32-Bit 1 Low Low Valid Data on D31-DO 32-Bit o Low High Valid Data on D31-D16 16-Bit x Low High Valid Data on D31-D16 or D15-DO 8-Bit x High Low Valid Data on D31-D24,.D23-D16, All x High High Insert Wait States in Current Comments D15-D8, or D7-DO Bus Cycle ~~~~.j, .:J;:::{:.Jy<,:~:!l ~, following the rising edge of AS or DS, and both are then three-stated (placed in the highimpedance state) to avoid interference with the next bus cycle. MC68882 DSACK lines Freescale Semiconductor, Inc... RESET (RESET) time and must conform to minimum riod and pulse width times. and m~~~~.~''pe*~. ` ~~~j,?~ ~'~$..;.., ,w~\.:.\l~. ":$w,. ,.,<,,, ,*S.$.* ,,:,,? `y,, .>,k.:.:t.:, ,,.$ SENSE DEVICE (SENSE) ~! it,. *!V$ ,$~ This pin may be used optionally ~~~fi,$~ditional GND pin or as as indicator to exte{~'~?$t~~dware that the MC68882 is present in the sys~$m$%~~ signal is internally connected to the GND of t~:~~$~, but it is not necessary to connect it to the ext~w$$?ound for correct device operation. Ifa pullup rp~~$~iwhich should be Iargerthan 10 kohm) is conneqq~t~%~s pin location, external hard.a*~J: ~,x~:,<,:i,. ware may sense, the~resence of the MC68882 in a sys.~,~t~. ~$}.}. tem. ~t:.,it ,$*!>:$;$. ,b~.,$7::+ ~owER ~gc~j ~ND) This active-low input signal causes the MC68882 to initialize the floating-point data registers to non-signaling (NANs) and clears the floating-point connot-a-numbers trol, status, and instruction address registers. When performing a power-up reset, external circuitry of should keep the RESET line asserted for a minimum tolerance. This asfour clock cycles after VCC is within sures correct initialization of the MC68882 when power is applied, For compatibility with all M68000 Family de,.\q,~.,.. .*,:,,. ,~. ,,, vices, 100 milliseconds should be used as the minimum. Thes%i~~ns provide the supply voltage and system refWhen performing a reset of the MC68882 after VCC has er%a$e Iekl for the internal circuitry of the MC68882, Care been within tolerance for more than the initial ~ower-uo ..~~uf~ be taken to reduce the noise level on these pins time, the RESET line must have an asserted p~lse width ,P,$~fi~ appropriate capacitive decoupling, which is greater than two clock cycles. For compatibility .*,. `*>$*s `~;$,::::b%?$: I;,,...-ho CONNECT (NC) with all M68000 Family devices, 10 clock cycles should be used as the minimum. .,<..(*' One pin of the MC68882 package is designated as a no ,$,$ connect (NC). This pin position is reserved for future use ..,7,. `!..!,$:,,,, CLOCK (CLK) i~,,!, .?*t. by Motorola, and should not be used for signal routing The MC68882 clock input is a ~L-com~#~W&~ignal or connected to VCC or GND. that is internally buffered for development~~,th~ ?nternal SIGNAL SUMMARY clock signals, The clock input should ,Qd~$:&~%fi:stantfrequency square wave with no stretchi~~~$~$haping tech~ated offat anY niques required. The clock should q~t~ Table 6 provides a summary of all the MC68882 signals described in the above paragraphs. .,:~:,?,'.....sy. >.,' t!;:>\ <. \ SignaK<#a*eJ'o :~i:i\y Address Bus,~>':$ { Data Bus `$:$**~~#F lnputiOutput Active State Three State AO-A4 Input High -- High Yes DO-DI 3 Size ,%~~>)~ SIZE Input/Output Input Low -- G Input Low -- m Input Low -- Rim Input High/Low -- m Input Low -- DSACKO, DSACK1 output Low Yes Reset RESET Input Low -- Clock CLK Input -- -- Low No Input -- -- Input -- -- ?~$?$s~tro be , , `&i,@S-elect ~,t:,)...~ ,> `@:J;~ `:'%ad/Write .$~,+,)?:., ~\ `~3 `".,t{,!~ `$~' Data Strobe ~.~ Data Transfer Sense Device Power Input Ground MCBR=/Rev. . .... .. ... .... . ... ,, ... .,, .,.., ,." Mnemonic and Size Acknowledge SENSE Vcc GND Input/Output For More Information On This Product, Go to: www.freescale.com MOTOROLA 13 3 .. . . .. , ,,, . .. .. . . . . .. . . ,,. . . . . .. ., ,' ,.. . ,,, ..,. Freescale Semiconductor, Inc. INTERFACING METHODS MC68882/MC6801 I O OR MC68030 INTERFACING The following paragraphs describe how to connect the MC68882 to an MC68020 or MC68030 for coprocessor operation via an 8-, 16-, or 32-bit data bus, v. A16-A19 ~ DEcoDE I - SIZE 32-Bit Data Bus Coprocessor Connection Figure 11 illustrates the coprocessor interface connection of an MC68882 to an MC68020/MC68030 via a 32-bit data bus. The MC68882 is configured to operate over a 32-bit data bus when both the AO and SIZE pins are connetted to VCC. FCO-FC2 a- A20-A31 -- Freescale Semiconductor, Inc... A16-A19 A13-A15 ~ ~ 8 z E 0 ~ 0 z z A5-A12 -- A1-A4 ~ AO CHIP SELECT OECODE E Vcc SIZE A1-A4 E E R~ D24-031 D24-D31 016-D23 D16-D23 FCO-FC2 D8-D15 D8-D15 DO-D? DO-D7 DSACKO DSACK1 MAIN PROCESSOR CLOCK ./,:, ,,. . ,,,,,$:/; 16-Bit Data Bus @+@oce&sor Connection Figure 12 ill.y~~~#'the coprocessor interface connection of an M~m2 to an MC68020/MC68030 via a 16-bit data bu~i,~k~WC68882 is configured to operate over a 16-bit,@~d~~ bus when the SIZE pin is connected to VCC, and. t~e ~0 pin is connected to GND. The sixteen leasts~~k~?arit data pins (DO-D15) must be connected to the $:a~~~~en most-significant data pins (D1 6-D31 ) when the !&&8882 is configured to operate over a 16-bit data bus ~.e., connect DO to D16, DI to D17, . . . and D15 to D31). The DSACK pins of the two devices are directly connected, although it is not necessary to connect the DSACKO pin since the MC68882 never asserts it in this configuration. 08-015 Da-D15 =H J + MAIN PROCESSOR CLOCK figure 13. 8-Bit Data Bus Coprocessor DO-07 DSACKO OSACK1 \ ? COPROCESSOR CLOCK Connection bus. The MC68882 is configured to operate over an 8-bit data bus when the SIZE pin is connected to GND. The twenty-four least-significant data pins (DO-D23) must be connected to the eight most-significant data pins (D24- Figure 13 illustrates the connect of an MC68882 to an MC68020/MC68030 as a coprocessor over an 8-bit data ,., D24-D31 D16-D23 DO-D7 m 8-Bit Data Bus Coprocessor Connection MOTOROU 14 D24-D31 D16-D23 For More Information On This Product, Go to: www.freescale.com MCBRW/Rav. ,, .. 3 . . ....,,,. . . .. . .. ,,. - Freescale Semiconductor, Inc. D31) when the MC68882 is configured to operate over an 8-bit data bus (i.e., connect DO to D8, D16 and D24; DI to D9, D17, and D25; . . . and D7 to D15, D23 and D31). The DSACK pins of the two devices are directly connetted, although it is not necessary to connect the DSACKI pin since the MC68882 never asserts it in this configuration. MC68882-MC68000/MC68008/MC68010 INTERFACING The following paragraphs describe how to connect the MC68882 to an MC68000, MC68008, or MC6801 O processor for opertion as a peripheral via an 8- or 16-bit data bus. 16-Bit Data BUS Peripheral Processor Connection Freescale Semiconductor, Inc... Figure 14 illustrates the connection of an MC68882 to an MC68000 or MC68010 as a peripheral processor over a 16-bit data bus. The MC68882 is configured to operate over a 16-bit data bus when the SIZE pin is connected to Vcc, and the AO pin is connected to GND. The sixteen least-significant data pins (DO-DI 5) must be connected to the sixteen most-significant data pins (D16-D31 ) when the MC68882 is configured to operate over a 16-bit data bus (i.e., connect DO to D16, DI to D17, ,.. and D15 to D31). The DSACKI pin of the MC68882 is connected to the DTACK pin of the main processor, and the DSACKO pin is not used. When connected as a peripheral processor, the MC68882 chip select (CS) decode, is system dependent. If the MC68000 is used as the main processor, the MC68882 CS must be decoded in the supervisor or user data spaces, However, if the MC68010 is used for the main processor, the MOVES instruction may be used to emulate any CPU space access that the MC68020/MC68030 generates for coprocessor communications. Thus, the CS decode logic for such systems may be the same as in an MC68020/ MC68030 system, such that the MC68882 will not-'hse any .,;*s.t::\~& k};<..N*.. part of the data address spaces. ,,i#:*~" {$:, ~,`,".: ~.i ,,.:; ,* ~$$, ~~ 8-Bit Data Bus Peripheral Processor C,~~~f~8n Figure 15 illustrates the connecti,~hjd~j~k MC68882 to an MC68008 as a peripheral proc~$@''r,@ver an 8-bit data <.~1.g, , !!*,*), bus, The MC68882 is configur~ tm~perate over an 8-bit data bus when the SIZE piq,,is'"&&#nected to GND. The eight least-significant d~ti$~~s (DO-D7) must be connetted to the twenty:f~~~~~st-sig nificant pins (D8-D31 ) figured to operate over an 8when the MC68882a{,~.~~b@ bit data bus (i,e,, q~@M'DO to D8, D16, and D24; DI to D9, D17, and ~$; .'!:,* and D7 to D15, D23, and D31), The DSACKO pin$$,~~~ MC68882 is connected to the DTACK pin of th@<W~m08, and the DSACKI pin is not used. Wh~@ ~-cted as a peripheral processor, the MC68882 chip #&#ct (CS) decode is system dependent, and the CS ~#st be:tiecoded in the supervisor or user data spaces. - ,", r 1 FCO-FC2 --+ A16-A19 --+ A13-A15 --* A5-A12 --* CHIP SELECT DECDDE (SYSTEM DEPENDENT) - E ,, SIZE GND+ > Al -A4 g ~ m Al -A4 AO ~ AO B E g g : ~ + . m R~ . 8 z E - R~ + D24-D31 00-07 4 * D16-D23 * D8-D15 * DO-D7 DSACKO DTACK ~ -- DSACK1 t f I 1 MAIN COPROCESSOR CLOCK PROCESSOR CLOCK [.;\, i:. ;$4) `"w COPROCESSOR CLOCK M'AIN PRbCESSOR CLOCK Figure 15. 8-Bit Data Bus Peripheral Processor Connection Figure 14. 16-Bit Data Bus Peripheral Processor Connection For More Information On This Product, Go to: www.freescale.com M C688B2 BRW/Rev. 3 .. .... .... .. . ... ..-,,. .. . ., ,,.,,... ...... ... .. ,...-,, ... .. .... . ,:. .:,.,.,..., !-.---...........-. ., ,"' ":. ,, .,..:,, , .',,,,,,. . ,.', !, ,. ...: --- .,,. . ,. MOTOROLA . ,,, .,, .. 15 ... . .. .. .... .. .., .,,. . .. .. .... ... ,, ... . . ,, . . . . ... ...-.,.:..... . ... .......... . ... . . .. .... . . . . .. .,. -.', . . Freescale Semiconductor, Inc. ELECTRICAL SPECIFICATIONS MAXIMUM RATINGS Rating Value Symbol Unit Supply Voltage Vcc -0.3 to +7.0 v Input Voltage ~n -0.3 to +7.0 v Operating Temperature TA Storage Temperature THERMAL T~tq o to 70 -55to `c +150 `c CHARACTERISTICS Characteristic Resistance -- Ceramic Junction to Ambient Junction to Case Symbol Value 9JA 33 15 Rating "cm Freescale Semiconductor, Inc... Thermal POWER 8JC CONSIDERATIONS <,*,:b'+~ The total thermdk,g@Wstance of a package (0.jA) -. can be :.?. separated in,t$'{~&o components, OJC and eCA, representing th@.*Q~#$i~eFtoheat flow from the semiconductor junctio,$.t$,th~ package (case) surface (eJc) and from the case tq $he+Dutside ambient (OCA). These terms are relat@ b~she equation: .ti.,.$,m ~ eJA= 6JC+ 6CA (4) , ... ~s~, The average chip-junction temperature, TJ, in `C can be obtained from: TJ=TA+(PD06JA) (1) where: TA = Ambient Temperature, `C 8JA = Package Thermal Resistance, Junction-to-Ambient, OC/W J #"'S$JC is device related and cannot be influenced by the pD 3,J$&&r. However, 6CA is user dependent and can be min= PINT+ Pi/0 +.+,?! ~$t,:.,.. ,.,,. %,+$~tlmized by such thermal management techniques as heat PINT = ICC x VCC, Watts -- Chip Internal Power sinks, ambient air cooling, and-thermal convention. Thus, Pi/0 = Power Dissipation on Input and Output ` .:k. ..,,1 . >:. .':' good thermal management on the p,art of the user can Pins -- User Determined For most applications P1/O<PINT and can be ~~$~q~ed. Significantly reduce 6CA so that eJA approximately equals eJc. Substitution of eJc for eJA in equation (1) will result The following is an approximate relation~~f~%ween ,,:.+;?,:,.: .\ in a lower semiconductor junction temperature. PD and TJ (if Pi/0 is neglected): Values for thermal resistance presented in this docuPD = K+ (TJ + 273"C] ~~'$!?j'~> (2) ment, unless estimated, were derived using the proceSolving equations (1) and (2) for.@~~#l@ dure described in Motorola Reliability Report 7843, K= PD (TA+ 273C) t8j~$PD2 (3) where K is a constant pertainiq~~~~~ particular part. K "Thermal Resistance Measurement Method for MC68XX can be determined from e~M&~A&~(3) by measurin9 pD Microcomponent Devices," and are provided for design purposes only, Thermal measurements are complex and (at equilibrium) for a kno~n ~~. Using this value of K, the values of PD and T&#~~~~&'obtained by solving equadependent on procedure and setup, User derived values for thermal resistance may differ. tions (1) and (2) ite$at~~l&%or any value of TA. :,< ,;~~~ d:" . J:{.;,!, .\~.}\\.\. y. ,, \`:?*.,,{> \ DC ELECTRl&#&j&ARACTERISTICS (Vcc =5.o Vdct5%; GND = O Vdc; TA= OCto 700C) ..,t .,,.1, . ..l\,...*+ *:4>* .g ~,., Symbol Max Characteristic Min Unit ,,.,...... > lnpu#Wg~+oltage vlH Vcc 2.0 v ?k~:~':~dw \,oltage -- ~~ Leakage Current @t5.25 V $ ~ji~t ---- ---- CLK, RESET, R/~, AO-A4, CS, DS, AS, SIZE ~Hi-Z (Off State) ,Input Current ~1.2.4 V/O.4V vlL GND -0,5 0.8 v Iin -- 10 WA ~, m, DO-D31 ITSI -- 20 FA Output High Voltage (IOH = -400 wA) ~, m, DO-D31 vOH 2.4 -- v Output Low Voltage (iOL = 5,3 mA) ~, ~, DO-D31 vOL -- 0.5 v SENSE IOL -- 500 PA Output Low Current (VOL= GND) Power Dissipation pD -- 0.75 w Capacitance* (Vin =0, TA=250C, f= 1 MHz) Cin 20 pF Output Load Capacitance CL -- -- 130 pF *Capacitance is periodically sampled rather than 10070tested. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AC ELECTRICAL -- CLOCK INPUT CHARACTERISTICS (VCC=5.O Vdc* 570; GND=O Vdc; TA=O to 70C; refer to Figure 16) 16.67 MHz Num Characteristic Frequency Freescale Semiconductor, Inc... 1 of Operation Cycle Time 2,3 Clock Pulse Width for 33 MHz) 4,5 Rise and Fall Times (VCC=5.O Vdc* (Measured 5%; GND=O Vdc; TA=O 65 Address Valid to ~ 6A5 Address 6B5 Address Valid to ~*As~~ed \ Valid ~"~~k~setied 76 ~ 33.33 MHz Max Min Max Min Max Min Max `nit 8 16.67 12.5 20 12.5 25 16.7 33.33 MHz 60 125 50 80 40 80 30 60 ns 24 95 20 54 15 59 14 -- 5 -- 5 -- 4 -- q,s ..,'..,., ..:',}*.. *,,i+i.,, 3$' `F.:. , ," ;,,, Rs ~!?,~. a?>,, ,\$* 66 17, 18, and 19) 16.67 MHz 20 MHz 25 MHz 33.33 MHz Unit Min Max Min Max Min Max Min Max 15 -- 10 -- 5 -- 5 -- ns (Read) 15 -- 10 -- 5 -- 5 -- ns (Write) 50 -- 50 -- 35 -- 26 -- ns 5 -- 5 -- ns Invalid 10 -- 10 -- Invalid 10 -- 10 -- 5 -- 5 -- ns o -- o -- o -- o -- ns to ~ Asserted to ~ Asserted (Read) o -- o -- o -- o -- ns q~ f,k. @ Asserted to ~ Asserted (Write) 30 -- 25 -- 20 -- 15 -- ns 89 ~%g~<$d 25 MHz Min to Figures As&'~#'@ Negat~@~o A~~ess :,`,+:,.,+ `> Nega@&i~@yAddress ~ 1.5 V to 1.5 V ~~@@$refer ~1$ ,* $>\.*::>." ? :.`,, .,,. ,.?*\\> ,.,/<".$.$. ,* ?a:$)$!&.~( ` Charac&r?8$~<<" -~+. * :.,! Num 7A6 from 20 MHz 8A9 ,.* %~*&ated ),~.y `~:;p ~?~i<%x ,, ` 10 10A IOB ~i @_ AS Negated ~ Negated to ~ Negated 10 -- 10 -- 5 -- 5 -- ns to ~ Negated 10 -- 10 -- 5 -- 5 -- ns R% High to ~ Asserted (Read) 15 -- 10 -- 5 -- 5 -- ns Rfi High to ~ Asserted (Read) 15 -- 10 -- 5 -- 5 -- ns R/~ Low to ~ Asserted (Write) 30 -- 25 -- 25 -- ns 35 -- 11 ~ N_egated to R~ R/W High (Write) Low (Read) or ~ Negated to 10 -- 10 -- 5 -- 5 -- ns 11A ~ Negated to R/~ Rfi High (Write) Low (Read) or ~ Negated to 10 -- 10 -- 5 -- 5 -- ns -- Continued u -- For More Information On This Product, Go to: www.freescale.com MC68882 BR~/Rev. 3 . . ....~., ..-..t.Fo. T..! .,!r,,.J. >.,,.,, ryrTAw.w..-r. Tw.,,l,t,,.., q,Tm, f.7.--, yT,..,.,..~,.!.,.........-;., $-: ..!.,,~,...,,-.,.-. 1..!.... .. . .... ..,:.....- ,. .. ... .. ... .,?,,.,( :, "--. *P8,!!!\,m,m :,!... ...,..,:,:,..;., ,,;, , ,,,, . :: , ,.. ,,...:., ,. ,,,!,, ,t.. . . ,'. ,, ,, .,'., ... ,. ,1,, ,., , `:.. ,~.,: . .....7-.... (, `, "., MOTOROLA 17 ,, . .,., .:... ....... . .< ..... ....,.r.,,~. !~?--~,Y,. ,-.,,,,,1,.-...,..~." :'.,~,.;l..:,->*T ~, ,, .. ,':,.,. ;,,.. ,.. , `,'. Freescale Semiconductor, Inc. AC ELECTRICAL SPECIFICATIONS -- READ AND WRITE CYCLES (Continued) 20 MHz 16.67 MHz Num 12 Max -- 38 -- 30 -- 23 -- Unit 38 -- 30 -- 23 -- ns 30 -- 25 -- 18 -- ns -- 80 -- 60 -- 45 -- o -- o -- o -- o -- 50 -- 30 -- 30 5 -- ~, ~ 15 ~ Negated to Data-Out Invalid 16 ~ Negated to Data-Out High Impedance Asserted Asserted to Data-Out 17 Data-In Valid to ~ 18 ~ 253S8 Min -- 142 243 Max -- Negated to ~ 233,8 Min 30 Width Negated 228 Max 40 ~ 20 Min 40 = 218 33.33 MHz Max Width Asserted {Write) 13 19A7 25 MHz Min ~ 13A4 192 Freescale Semiconductor, Inc... Characteristic Asserted Valid) (Read) (Read) (Read) (Write) Negated to Data-In Invalid (Write) -- -- START True to DSACKO and DSACK1 Asserted DSACKO Asserted to DSACKI -- -- DSACKO or DSACKI Asserted Asserted (Skew) to Data-Out Valid START False to DSACKO and DSACK1 Negated -- _ START False to DSACKO and DSACKI High Impedance START True to Clock High (Synchronous Clock Low to Data-Out 15 -- 10 -- 15 -- 10 -- -- 50 -- 35 -15 15 -lo -- 50 -- -- 50 -- -- 70 Read) Valid (Synchronous START True to Data-Out Valid (Synchronous Read) Read) . -- 10 l,g , ~,g *"_ 80 ns - n5 - - $*., $:.10 ` " - ! ;,, ,$ :$ &~~:~ - ~<:~ `(~' 7 -- ,$ `$~b,. i- 5 43 ,j;~:,<p~s 20 ns 5 n5 32 -- 17 ns 30 -- 20 ns 40 - 30 ns -- ns 45 ns o -- -- 60 -- 80+ -- 1.p:(, 2.5 ` 1.5 2.5 1.5 .. ~..>,i: ~>~ ,, ~ii \ ?';~75 263 Clock Low to DSACKO and DSACKI Asserted -- 55 -- *$ ... <i, `+$> \Jli)~,i,.$ (Synchronous Read) -- -- *,~,\::<., ,J>,, .x.,*_ 2j3,8 START True to DSACKO and DSACK1 As5~~ted "*7,!.. 75+ -- 55+ -- (Synchronous Read) "<$ 1.5 2.5 1.5 2.5 1.5 **>.. : ` ,+:~~$,{ > NOTES: t:~,. ~, (~j, 1. Timing measurements are referenced to ~~,.~~m"'a low voltage of 0.8 volts and a high voltage noted, The voltage swing through this&@~~$~$~ould start outside, and pass through, the range "ii~(,:}' linear between 0.8 volts and 2.o vol~ 2. These specifications only apply if $&$*~882 has completed all internal operations initiated by `":;$.': ::<~j:. bus cycle when ~ was negated~tl, .~, ~~ ns o .-- 60+ -- 45+ 2.5 1.5 2.5 C;:s 45 -- 30 ns 45+ 2.5 -- 1.5 30+ 2.5 CY:S of 2.0 volts, unless otherwise such that the rise or fall will be the termination ~~. , r <:, , x.-.. ,.~, ,) *.*/ of the previous the save or response CIR locations are read. 3. Synchronous read cycles occ~:$o~'when 4. This specification only ap#}?&s~W->ystemsin which back-to-back accesses (read-write or write-write) of the operand CIR can as a coprocessor to the MC68020/MC68030, this can occur when the addressing mode is occur. When the MC6w&~,$@sed $ *.{:&$ .~~: Immediate. 5. If the SIZE pin is g~~~~mped to either VCC 6. If the SIZE pin i/'~t#rapped to either VCC 7. This numbW?~,~edu~ed to 5 nanoseconds if or GND, it must have the same setup times as do addresses. or -- GND, it must -- have the same hold times as do addresses. DSACKO and DSACKI have equal loads. 8. START is ti~~iw~xternal signal; rather, it is the logical condition that indicates the start of an access. The logical equation for this c~,~~~~o ~ m= ~ +~ t R~*~. 9. If a ~'~k~~~$nt access is not a FPCP access, ~ must be negated before the assertion of ~ end/or ~ on the non-FPCP acce~ Tk@#@'~cifications replace the old specifications 8 and 8A (the old specifications implied that in all cases, transitions in CS. g~u~s~ot occur simultaneously with transitions of ~ or ~. This is not a.requirement of the MC68882). }} `{$>$.,.* ,+,: <,i,:.,i ,+~,.., ,y.lw, &,:,?:**~:4 <.bk>l >ib `$~~~ ELECTRICAL SPECIFICATION DEFINITIONS and/or maximum limits, as with minimum appropriate, and are measured as shown. Inputs are specified with minimum and, as appropriate, maximum setup and hold times, and are measured as shown, Finally, the measurement for signal-to-signal specifications are also shown. Note that the testing levels used to verify conformance to the AC specifications does not affect the guaranteed DC operation of the device as specified in the DC electrical characteristics. are specified The AC specifications presented consist of output delays, input setup and hold times, and signal skew times, All signals are specified relative to an appropriate edge ef the clock input and, possibly, relative to one or more other signals. The measurement of the AC specifications is defined by the waveforms shown in Figure 20. In order to test the parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in. Figure 20. Outputs .:. `. &`,,,.,. v For More Information On This Product, Go to: www.freescale.com MOTOROLA 18 MC6B682 BR~/Rev. 3 ,. ..,, . . . . ... . ,.,.,.. Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. --. I For More Information On This Product, Go to: www.freescale.com ? MC= BRW/Rev. 3 MOTOROM 19 ~,,,,, `\,, ,,. Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... ;.,, L -- 22 + 21 -- -- -- t- For More Information On This Product, Go to: www.freescale.com MCBR~/Rev. MOTOROW 20 ,,, . 3 ,,,,.,,- Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... S1 S2 Sw Sw Sw Sw S3 S4 S5 -- MCBRW/Rev. For More Information On This Product, Go to: www.freescale.com 3 MOTOROU 21 Freescale Semiconductor, Inc. DRIVE TO 2.4 V CLK A -2.0 v 0.8 v ~ 0.8 V + ORIVE J TO 0,5 V OUTPUTS(1) CLK ~A+ B + VALID 2,0 v ` OUTPUT n 0,8V7 c2.0v ~0,8V vALID OUTPUTn+l Freescale Semiconductor, Inc... -- For More Information On This Product, Go to: www.freescale.com MOTOROU z MC= BRW/Rev. 3 --., Freescale Semiconductor, Inc. I PIN ASSIGNMENTS AND MECHANICAL DATA PIN ASSIGNMENTS r. ~:$, ,J PIN GRID ARRAY 0000000000 D30 D29 D27 0000000000 ---- A3 Vcc CS DSACKO D31 D28 D25 Al R~ GNDDSACK1 00-0 ~ A2 o. ~A4 0 GND D24 D22 D23 D21 000 AO Vcc GND D19 00 D20 D18 00 = GND 00 D17 Vcc Vcc NC Freescale Semiconductor, Inc... D26 00 D16 00 GND 0 q; 00 RESET GND 000 GND CLK GND o Vcc 0 GND 0 GND o Vcc 0 GND 0 DO 0 D9 & SENSE o D2 0 D5 0 D1 0 D3 0 0<::.,0''"0 D4 ,,?}W6 "~{~~ D; %~&$ ,,,:f:&:,>;,Dli 0 Q'V,Q,,'"0 GND\$V~ `~l~ D8 Dll 0 GND TDP VIEW NC EGND RESET GND --- rl K D9 60 ~ For More Information On This Product, Go to: www.freescale.com MCBRW/Rev. MOTOROW 3 23 --- ,.,,. ...<..,>,.,.. . ...........;.,,,..,,,. ........... .. ..., , ,,.:,,, ............ . ... . .. .,. 0 61 ,, '...- .. . ,.,' . ."----. ....... ... . .. . ........ . . ,. ..,.. ... ... . ,.. ,. -, . . ,,, .,. , , ..:.' "..,-t!tl....... .... .......-.4. ..- ,. .:,:, :,', . ,.. :,.. ,, ... .......... ,!, ,: ;'. , -- - ,,. Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com MOTOROM 24 ., ..,. . . .. . . ,,. .. ,. . . . . . ... .,,, . ,. M~ BR~/Rev. .. .. ........ . 3 Freescale Semiconductor, Inc. FN SUFFIX PLASTIC LEADED CHIP-CARRIER CASE 779-02 --B + ru i Freescale Semiconductor, Inc... 0,18(0,007) @ T N@P@ [$1 o.18(o.QQ71 @ ]T L&M@ N @-P@ L@M@ d 7" I L A -R + 0.18(0.0071 @ 1+]0.18(0.007) @ T L@-M@l \T I L@M N@-P@ @l N@-P@] I I a 0.10(0,004) NE F I l\ I I u DETAIL S NOTES: CASE 779-02 SHALL 1. DUETO SPACELIMITATION, :,*:*... $?0.48 ~ M~ BRW/Rev. 0.013 0.019 BE REPRESENTEDBY A GENERAL (SMALLERI CASE OUTLINEDRAWING RATHERTHAN SHOWING ALL68LEADS. 2.DATUMS -L., M-,-N-, AND -P-DETERMINED WHERE TOP OF LEAD SHOULDER EXITPLASTIC BODY AT MOLO PARTINGLINE. 3,DIM Gl,TRUE POSITIONTO BE MEASURED AT DATUM -T-, SEATINGPLANE. 4,DIM R AND U DO NOT INCLUDEMOLO PROTRUSION.ALLOWABLE MOLD PROTRUSION IS0.25(0,010} PERSIDE, 5.DIMENSIONINGAND TOLERA.NCING PERANSI Y14.5M, 1982. 6.CONTROLLINGDIMENSION:INCH, For More Information On This Product, Go to: www.freescale.com 3 MOTOROLA 25 ,. . . Freescale Semiconductor, Inc. FAMILY STANDARD ORDERING IN FORMATION,., Freescale Semiconductor, Inc... M68000 NOTE: Motorola .,) Consult Order Factory for Products Requiring Exte@d~erating ~tf<.i?.< *:\ \.\, ..! `~:t~+ Temperatures or Special Processing. Number: :,. , l&&ot&k~a''?&serves the ,right to make changes witho:t f:rrher notice to any products herein to improve reliability, function or design. Motorola ~~sR~ assume any Imblhty ar!slng out of the application or use of any product or circuit described herein; neither does it convey any license u~er Its patent rights nor the rights of others. Motorola products are not authorized for use as components in life support devices or systems int%nded for surgical implant into the body or intended to suppo~ or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product orproducts for the use intended. Motorola and@ are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity:Affi rmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive, Blakelands Milton Keynes, MK145BP, England. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; PO. Box 80300; Cheung Sha Wan Post Office; Kowloon Hong Kong. - n M MOTOROLA For More Information On This Product, Go to: www.freescale.com J