MC68882RC20A - Motorola / Freescale Semiconductor

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-SEMICONDUCTOR

TECHNICAL DATA

.—

3MC68882

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Floating-Point Coprocessor $.:::?“

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The MC68882 floating-point coprocessor fully implements the IEEE Standard for Binary Floatin~_+’’,i~’C

Point Arithmetic (ANSI-IEEE Standard 754-1985) for use with the Motorola M68000 Family of ,,~f@&~i$

processors. An upgrade of the MC68881, it is pin and software compatible with an optimiz$d ~~$~

interface providing in excess of 1.5 times the performance of the MC68881. It is implem~~~,, ui;ng

VLSI technology to give systems designers the highest possible functionality in aph~:W&~&mali

device. .!.}~,,,*.,,,*

\$.i,,,,., >$

Intended primarily for use as acoprocessor to the MC68020 or MC68030 32-bi~,~$&@’rocessor

unit (MPU), the MC68882 provides alogical extension to the main MPU integer ~~$~~rocessing

capabilities. This extension is achieved by providing avery high performan~~oatlng-point arith-

metic unit and a set of floating-point data registers which are analogoust$~~t~ &se of the integer

data registers. The MC68882 instruction set is anatural extension of a~j$afi~r members of the

M68000 Family, and it supports all of the addressing modes of the ~$’~~~. Due to the flexible

bus interface of the M68000 Family, the MC68882 can be used wj~~ ari~,of the MPU devices of the

M68000 Family and as aperipheral to non-M68000 processors{,{~~ :&+,

The major features of the MC68882 are: .,$>..*), $

.:.?:

.:;:,>..+..

●Eight general purpose floating-point data register% ?P~M.8’tipporting afull 80-bit extended

!,,,*..l,k*,,,**.

precision real data format (a 64-bit mantissa plus ~~,~~ bit, and a 15-bit signed exponent).

●A67-bit arithmetic unit to allow very fast cal$ula~~ons~ with intermediate precision greater

“-~, than the extended precision format. .3*$;; .

.,J ““:*\.

.A67-bit barrel shifter for high-speed s~jfl~~b d~erations (for normalizing etc.).

oSpecial purpose hardware for high-#~~&k~”&nversion of binary real memory operands to and

from” the internal extended forma~J~$,,~#>

.Reduced coprocessor interfac$~~wad to increase throughput.

.Forty-six instructions, includ~n@~~5Jarith metic operations.

~,,\,...>.{,.,‘~.

.Full conformation to the.#~$~}FEE 754 standard, including all requirements and suggestions,

.’:’!..,

.Support of functionsA@”%+,@#ned by the IEEE standard, including afull set of trigonometric

and transcendenta~, f&ct~ns,

:t ‘.’:*w,.,:s

●Seven data type$$.’b~e, word and long word integers; single, double, and extended precision

~$%,:+

real number$),$ndp-acked binary coded decimal string real numbers.

●Twenty-t~t~&$,~~tants available in the on-chip ROM, including n, e, and powers of 10,

●Virtual @&@@rY/machine operations.

●Effi~~<#~~eChanisms for procedure calls, context switches, and interrupt handling.

. ..f\.

.Q&fiC&~~ent instruction execution with the main processor.

,4*j&QQlurrent instruction execution of multiple floating-point instructions.

.‘+:~:,$,~,

“:%.,use with any host processor, on an 8-, 16-, or 32-bit data bus.

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This document contains information on anew product. Specifications and information herein are subject to change without notice.

@MOTOROLA -

@MoToRoLAINC.,1988 BRW/Rev. 3

. ... . . .. .

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THE COPROCESSOR CONCEPT HARDWARE OVERVIEW

The MC68882 functions as acoprocessor in systems The MC68882 is ahigh performance floating-point de-

where the MC68020 or MC68030 is the main processor vice designed to interface with the MC68020 or MC68030

via the M68000 coprocessor interface. It functions as aas acoprocessor. This device fully supports the MC68020 ,p

peripheral processor in systems where the main proces- or MC68030 virtual machine architecture and is imple- p

sor is the MC68000, MC68008, or MC68010. \.;

mented in HCMOS, Motorola’s low power, small geom-

The MC68882 utilizes the M68000 Family coprocessor etry process. This process allows CMOS and HMOS (high

interface to provide alogical extension of the MC68020 density NMOS) gates to be combined on the sa,,~<~~evice.

or MC68030 registers and instruction set in amanner CMOS structures are used where speed a~@,l~~,~ower

which is transparent to the programmer. The program- is required, and HMOS structures are use~, W%re mini-

mer perceives the MPU/FPCP execution model as if both . ::,t.~.,;.i.+~$~

mum silicon area is desired. Using t~,~ W&Whology in-

devices are implemented on one chip. Afundamental ..,,.’~>

creases speed performance whi~g%~!$g low power

goal of the M68000 Family coprocessor interface is to consumption, yet still confines th~’~~~~~~1 to areason-

provide the programmer with an execution model based ‘~.s,~;.,“..t+~

ably small die size. .,

,,j,,’.J-,$\\I..\..

!~ ‘k

upon sequential instruction execution by the MC68020 ,*~-.

The MC68882 can also Qf ~~,$as aperipheral pro-

or MC68030 and the MC68882. For optimum perform- cessor in systems where t@@~~C68020 or MC68030 is not

ante, however, the coprocessor interface allows concur- the main processor (e,&};,W&OOO, MC68008, MC68010).

rent operations in the MC68882 with respect to the The configuration o~$~ ,@68882 as aperipheral pro-

MC68020 or MC68030 whenever possible. In order to sim- cessor or coprocqs$@~’m#y be completely transparent to

plify the programmer’s model, the coprocessor interface ~,..s,,,‘,~ ‘

user software (i.e.;%~~’%ame object code maybe executed

is designed to emulate, as closely as possible, non-con- in either co~~$~::atfon).

current operation between the MC68020 or MC68030 and The ar~&$,~~’re of the MC68882 appears to the user

the MC68882. as alo~i~.,1, e~tension of the M68000 Family architecture,

The MC68882 is anon-DMA type coprocessor which Beca~$@o~the coupling of the coprocessor interface, the

uses asubset of the general purpose coprocessor inter- ~~fi80’* or MC68030 programmer can view the MC68882

face supported by the MC68020 or MC68030. Features of .,.~eg$~ters as though the registers are resident in the

the interface implemented in the MC68882 are as follows: #“~68020 or MC68030. Thus, aMC68020 or MC68030 and

‘“$~e~ MC68882 device pair functions as one processor with

.The main processor(s) and MC68882 communicat~~~~jw’

via standard M68000 bus cycles. ~**.~~ eight integer data registers, eight address registers, and

.!> eight floating-point data registers supporting seven float-

.The main processor(s) and MC68882 cO.~mUti:i- ing-point and integer data types.

cations are not dependent upon the a~@:a&cture The MC68882 programming model is shown in Figures

of the individual devices (e.g., instruc@~$~ip&s or 1through 6 and consists of the following:

caches, addressing modes). V;>!]*Q,

“..i.

~).:t.x,.*

,‘:. +f{”i,~

●The main processor(s) and MC6@~~~@ay operate ●

,“~.!...~’x$:’~kl,,.~\

at different clock speeds. ~:.,?..:,..{,m‘+<

.?,$:,,,7* “’’”.:

●MC68882 instructions util,i~~,a$~~ddressing modes

provided by the main @#o<$#&or.

~:+~’~\;~,., *,*$ e

●All effective addreqqb~~q’y%calcu lated by the main

processor at th~t~~~si~ of the coprocessor.

,..-

Eight 80-bit floating-point data registers (FPO-FP7).

These registers are analogous to the integer data

registers (DO-D7) and are completely general pur-

pose (i.e., any instruction can use any register).

A32-bit control register that contains enable bits

for each class of exception trap, and mode bits to

set the user-selectable rounding and precision

modes.

A32-bit status register that contains floating-point

condition codes, quotient bits, and exception sta-

tus information.

A32-bit instruction address register that contains

the main processor memory address of the last

floating-point instruction that was executed. This

address is used in exception handling to locate the

●All data tran~fdxk$:~~e performed by the main pro-

cessor at ~~’~we~uest of the MC68882.

.*:\,ij+p,,\:t ●

●Overla~@ ft’bncurrent) instruction execution en-

han~,~~?~bughput while maintaining the pro-

g&~t@~*~r’s model of sequential instruction

~f3%$BNtion, ●

,,:,~’~~~~~dprocessor detection of exceptions which require

‘,J:gt,........atrap to be taken are serviced by the main pro-

8::’i\iJ..,tJ?~.

..:..$,,>9...cessor at the request of the MC68882.

~lt~. instruction that caused the exception,

.;.

>●Support of virtual memory/virtual machine sys- The connection between the MC68020 or MC68030 and

terns is provided via the FSAVE and FRESTORE the MC68882 is asimple extension of the M68000 bus

instructions. interface. The MC68882 is connected as acoprocessor to

●Up to eight coprocessor may reside in asystem the MC68020 or MC68030, and the selection of the

MC68882 is based on a chip select which is decoded from

simultaneously. Multiple coprocessor of the same the MC68020 or MC68030 function codes and address

type are allowed. bus. Figure 7illustrates the MPU/coprocessor configu-

.Systems may use software emulation of the ration.

MC68882 without reassembling or relinking user As shown in Figure 8, the MC68882 is internally divided ,~,

,. -,

software. into three processing elements: the bus interface unit ‘./

MOTOROU M~

2BRW/Rev. 3

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7IFPO

FP1

FP2

FP3 FLOATING POINT

FP4 DATA REGISTERS

FP5

~ROUNOING MOOE:

00 TO NEAREST

01 TOWARD ZERO

10 TOWARD MINUS INFINIW

11 TOWARD PLUS INFINIV

ROUNDING PRECISION:

00 EXTENDED

01 SINGLE

10 DOUBLE

11 (UNDEFINEO, RESERVEO)

Figure 3. Mode Control B~e

MC- MOTOROM

BRW/Rev, 33

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31 30 29 2a 27 26 25 24

[oNzINAN

NOT ANUMBER OR UNORDERED

lNFINl~

ZERO

NEGATIVE

Figure 4. Condition Code B~e

23 22 21 20 19 la 17 16

IsQUOTIENT

Figure 5, Quotient B~e

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(BIU), the conversion unit (CU), and the arithmetic proc- cycle. (The function codes are generated by the M68000

essing unit (APU). The BIU communicates with the Family processors to identify eight separate address

MC68620 or MC68030, the CU performs data conversion spaces.)” Thus, the memory-mapped coprocessor inter-

For binary real data formats, and the APU executes all face registers do not infringe upon instruction or data

MC68882 instructions. address spaces. The MC68020 or MC68030 places aco-

The BIU contains the coprocessor interface registers

(CIRS). In addition to these registers, the register select processor ID field from the coprocessor instruction onto

three of the upper address lines during coprocessor ac-

and DSACK timing control logic is contained in the BIU. cesses. This ID, along with the CPU address space func-

Finally, the status flags used to monitor the status of tion code, is decoded to select one of eight coprocessor

communications with the main processor are contained in the system. ~~~~.~l,

in the BIU. Since the coprocessor interface protocol is ba~~wlely

The CU contains special purpose hardware that per- on bus transfers, the protocol is easily ernu~?~q~~y soft-

forms data format conversions between binary real data ware when the MC68882 is used as aperl,~~:~~ktiith any

formats to and from ‘the internal extended format. The processor capable of memory-mapped @+@yaTan M68000

CU relieves the APU of asignificant work load and allows style bus. When used as aperiphe$$.@r@ssor with the

the MC68882 to execute data movement and preparation 8-bit MC68008, the 16-bit MC68,R{:~$r?he .MC68010, all

functions concurrently with arithmetic and transcenden- MC68882 instructions are trapp~$:$ the main processor

tal calculations, to an exception handler at g$$cut?~n time. Thus, the soft-

The eight 80-bit floating-point data registers (FPO-FP7) ware emulation of the c~~~~~$~or interface protocol can

and the 32-bit control, status, and instruction address be totally transparent%~~:t~&Wser. The MC68882 can pre-

registers (FPCR, FPSR and FPIAR) are located in the APU. vide aperformancetW~~.@ for MC68000-based designs

In addition to these registers, the APU contains ahigh- by changing the ‘T~%~@’*processors to the MC68020 or

speed 67-bit arithmetic unit used for both mantissa and MC68030. Th,~~pftMre migrates without change to the

exponent calculations, abarrel shifter that can shift from next gener&k$&#$eq uipment using the MC68020 or

1bit to 67 bits in one machine cycle, and ROM constants MC6803@s”’:?JW’

(for use by the internal algorithms or user programs). Sin@’J%&$s is asynchronous, the MC68882 need not

The control section of the APU contains the clock gen- ru~.at~g same clock speed as the main processor. Total

erator, atwo-level microcode sequencer, the microcode ,J,~$&~~mperformance may therefore be customized. For a

ROM, and self-test circuitry. The built-in self-test capa- :Weti CPU performance requirement, the floating-point

bilities of the MC68882 enhance reliability and ease man- S+~&.$@’iformance can be selected to meet Particular Price/

ufacturing requirements; however, these diagnost~~~%k~ performance specifications, running the MC68882 at

functions are not accessible outside of the special test ‘t slower (or faster) clock speeds than the MPU clock.

,, s~i;,y+,.>~.

All communications between the MC68@~~OFWC68030

and the MC68882 occur via standard M@~~Q:@>amily bus

transfers, The MC68882 is design,~t~~~~~erate on 8-,

16-, or 32-bit data buses. :f},\,.*7.~:

>~$iy,.\\<..

The MC68882 contains anu@b#~.~coprocessor inter-

face registers (CIRS) that ar~.~~r$ised in the same man-

ner as memory by the rnai~~~~essor. The M68000 Family

coprocessor interface.r$<!#~@emented via aprotocol of

reading and writing t$$~#se registers by the main pro-

cessor. The MC6@:~0 anfl MC68030 implement this gen-

~’‘.:!$,~~..+

eral purpose co~ra$~ssor interface protocol in hardware

and microc~$~,$~~~ ~

WhenJh*~$~&68020 or MC68030 detects ageneral type

MC68&Q~~~s?tuction, the MC68020 or MC68030 writes

the,i@tru$~on to the memory-mapped command CIR and

r~S&%l~&response CIR. In this response, the BIU encodes

‘+’:t.:.:.~’:~’.t~.

~i%{e$~estsfor any additional action required of the MC68020

“$.@~C68030 on behalf of the MC68882. For example, the

‘%sponse may request that the MC68020 or MC68030 fetch

an operand from the evaluated effective address and

transfer the operand to the operand CIR. Once the

MC68020 or MC68030 fulfills the coprocessor request(s),

the MC68020 or MC68030 is free to fetch and execute

subsequent instructions.

The only difference between acoprocessor bus transfer

and any other bus transfer is that the MC68020 or MC68030

issues aCPU address space function code during the

COPROCESSOR INTERFACE

The M68000 Family coprocessor interface is an integral

part of the MC68882 and MC68020 or MC68030 designs.

The interface partitions MPU and coprocessor operations

so that the MC68020 or MC68030 does not have to corn-

pletely decode coprocessor instructions, and the MC68882

does not have to duplicate main processor functions (such

as effective address evaluation). This partitioning pro-

vides an orthogonal extension of the instruction set by

permitting MC68882 instructions to utilize all MC68020

or MC68030 addressing modes and to generate execution

time exception traps. Thus, from the programmer’s view,

the MPU and coprocessor appear to be integrated onto

asingle chip.

While the execution of the great majority of MC68882

instructions may be overlapped with the execution of

MC68020 or MC68030 instructions, concurrency is com-

pletelytransparent to the programmer. The MC68020 and

MC68030 single-step and program flow (trace) modes are

fully supported by the MC68882 and the M68000 Family

coprocessor interface.

While the M68000 Family coprocessor interface per-

mits coprocessor to be bus masters, the MC68882 is

never abus master. The MC68882 requests that the

MC68020 or MC68030 fetch all operands and store all

results. In this manner, the MC68020 and MC68030 32-

bit data bus provides high speed transfer of floating-point

operands and results while simplifying the design of the

MC68882.

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\.+.‘.,!,:

i+j ‘$<.

~:<,,,.*,,:$’ APU

.,.s,,.,:>,‘I

CLK !BIU

BUILT IN SELF TEST

REGISTERS

CONTROL CIR I

.- 1RESTORE CIR

uSAVE CIR

RESPOWE CIR

.................................................................

RESPONSE PLA

tAA

a. tSTATUS FLAGS

-1 NROM

,I1

-COMMAND/CONDITION CIR h

,!, !

.,..,), ,t!,

.*,, .?.%$!,?

.l.~~:~

f<, ..,, 14

.,>,

‘) S, D, XFORMAT

.,,,,,\:{.’ CONVERSION L~lC

.................................................................

@’n

Figure 8. MC68882 Simplified Block Diagram

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,, ... ... ..,.. ,.

Since the coprocessor interface is based solely upon

bus cycles (to and from CPU space) and the MC68882 is

never abus master, the MC68882 can be placed on either

the logical or physical side of the system memory man-

5% agement unit in an MC68020-based system. Since the

-’<..-Y memory management unit of the MC68030 is on-chi~,

the MC68882 is-always on the physical side of the mern~

ory management unit in an MC68030 system.

The virtual machine architecture of the MC68020 or

MC68030 is supported by the coprocessor intetiace and

the MC68882 through the FSAVE and FRESTORE instruc-

tions. If the MC68020 or MC68030 detects a page fault

and/or atask time out, the MC68020 or MC68030 can force

the MC68882 to stop whatever operation is in progress

at any time and save the MC68882 internal state in mem-

ory, During the execution of afloating-point instruction,

the MC68882 can stop at predetermined points as well

as at the completion of the instruction.

The size of the saved internal state of the MC68882 is

dependent upon the state of the APU at the time the

FSAVE is executed, If the MC68882 is in the reset state

when the FSAVE instruction is received, only one word

of state is transferred to memory, which may be exam-

ined by the operating system to determine that the co-

processor programmer’s model is empty, If the

coprocessor is in the idle state when the save instruction

is received, only afew words of internal state are trans-

ferred to memory. If executing an instruction in the busy

potentially fully concurrent and, therefore, can be com-

pletely executed during the execution of aprevious in-

struction.

The MC68882 also has amore optimized coprocessor

interface than the MC68881. If an arithmetic instruction

has data formats of Single, Double or Extended, the dial-

ogs are designed to increase the potential overlap with

subsequent instructions, This overlap can significantly

decrease the effective instruction execution time.

Double Precision Rga~~~~N’

Extended Precisi~~,~<$PIX)

Packed Decimal”t~$@~’Real (P)

The capital letter<~$$~%ined in parentheses denote suf-

fixes added .~d}$~:troctions in the assembly language

source spW~l@~~fhe data format to be used.

*“ .~y.

,$$*,,,

lNTE~~:~A$A FORMATS

~~e t~be integer data formats (byte, word, and long

state, it may be necessary to save the entire internal state ,,,~~oral. are the standard twos complement data formats

of the machine, Instructions completing execution in less ,$,sd$ported in the M68000 Family architecture. Whenever

time than it takes to save the larger state in mid-instrucl~c?~~~c,

“&~ integer is used in afloating-point operation, the in-

tion are allowed to complete execution and then save the ‘I+i,

“’” ‘“’’’’’’’tiger is automatically converted by the MC68882 to an

idle state, Thus, the size of the saved internal state is kepl extended precision floating-point number before being

to aminimum. The ability to utilize several inter~~y, state used. For example, to add an integer constant of five to

sizes greatly reduces the average conte”xt switch~~g~tie. the number contained in ‘floating-point data “register 3

The FRESTORE instruction permits reloa~i’k~~k%n in- (FP3), the following instruction can be used:

ternal state that was saved earlier and co~~~q.~ any op- FADD.W #5,FP3

eration that was previously suspende~. ~~,~&~STORE of (The Motorola assembler syntax “#” is used to

the null state frame re-establishes d~~b$~@pister values, denote immediate addressing.)

afunction identical to the MC68w ~rdware reset,

,\L:~,..::,**\~\> The ability to effectively use integers in floating-point

,.:~$~.

MC68882 PERFORMANCE ~~@@EMENTS operations saves user memory since an integer repre-

~:\.,

The high performanceKo$:~h$iMC68882 is the result of sentation ofa number, if representable, is usually smaller

than the equivalent floating-point representation.

the MC68882’S abilty $* ~~cute multiple floating-point

instructions concu,$$ent?~gF~he direct result of concur- FLOATING-POINT DATA FORMATS

rency is to utilize$~~~~rithmetic Processing Unit (APU)

more efficient~,{b~~’@&creasing its idle time. The floating-point data formats, single precision (32-

When th~;~,t*82 receives an instruction, the BIU, bits) and double precision (64-bits), are defined by the

along wit~~@~~@U, can initiate the instruction, fetch the IEEE standard. These data formats are the main floating-

necesWW ~erands, and convert them to the internal point formats and should be used for most calculations

extq,~$~~,.,$rmat even though the APU is busy complet- involving real numbers, Table 1lists the exponent and

ins~s%s~ution of aprevious instruction. Although the mantissa size for single, double, and extended precision,

t&&~81 can only instruct the main processor to wait if The exponent is biased, and the mantissa is in sign and

~&’’~PU is busy, the MC68882 CU can proceed with the magnitude form. Since single and double precision re-

n~xt instruction. When the APU is finally ready to perform quire normalized numbers, the most-significant bit of the

the calc(~lation. it can dn sn imm~diatelv without incur- mantissa is implied as a one and is ndt included, thus

., -------- -- !...,,,.

ring delav due to data movement and preparation func- giving one extra bit of precision,

tio;s. ‘The extended precision data format is also in conform-

Another factor in obtaining increased performance in ante with the IEEE standard, but the standard does not

the MC68882 is the oDtimized FMOVE instructions for specify this format to the bit level whereas it does for

~r.: binary real data formats. These FMOVE instructions ex-

\single and double precision. The memory format on the

:<21 ecute twice as fast as the corresponding FMOVE instruc- MC68882 consists of 96 bits (three long words), Only 80

tions of the MC68881, The FMOVE instructions are also bits are actually used; the other 16 bits are for future

MC= MOTOROU

BR~/Rov. 37

.,-, . ,. . .- . ....... . ,,. .

,,,

,,.

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,.. . ... . ........ . .. . ... ... . ..- .. ... ... .

Table 1. Exponent and Mantissa Sizes

Data Exponent Mantissa

Format Bits Bits Bias

Single 823(tl) 127

Double 11 52(+1) 1023

Extended 15 64 16383

expandability and for long-word alignment of floating-

point data structures. Extended format hasa 15-bit ex-

ponent, a64-bit mantissa, and a l-bit mantissa sign.

Extended precision numbers are intended for use as

temporary variables, intermediate values, or in areas

where extra precision is needed, For example, acompiler

might select extended precision arithmetic for evaluation

of the right side of an equation with mixed sized data

and then convert the answer to the data type on the left

side of the equation. It is anticipated that extended pre-

cision data will not be stored in large arrays due to the

amount of memory required by each value.

PACKED DECIMAL STRING REAL DATA FORMAT

The packed decimal data format allows packed BCD

registers always contain extended precision values. All

operands used are converted to extended precision by

the MC68882 before aspecific operation is performed,

and all results are in extended precision. The use of ex-

tended precision ensures maximum accuracy without P

.,.

1$.,1

sacrificing performance. Refer to Figure 9for asummary 4;3

of the memory formats for the seven data formats sup-

ported by the MC68882. ~~*~.*.

...... $,*,

f!’}~{,?.(,!~tt.,:*,

,.;,~y‘..~j,,

~\$\,.. ~$.,

,../,.”~.:,

The MC68882 instruction set ist&~~$~8&d intO SiX major

classes: ‘<k:\,:i

\:v:p

1. Moves between the,~~&8882 and memory or the

MC68020 or MC$@~@A and out),

2. Move multipl~t~[~i$~ers (in and out),

3, Monadic og~~~@*s,

strings’to be transferred to and from the MC68882. The

strings consist of a3-digit base 10 exponent and a 17- ,:~~~Qn$ll moves from memory (or from an MC68020 or

$. ~’~g68030 data register) to the MC68882, data is converted

digit base 10 mantissa. Both the exponent and mantissa., ~:t

~i$V:@4rom the source data format to the internal extended pre-

have aseparate sign bit. All digits are packed BCD; an t:; ~~

entire string fits in 96 bits (three long words). As is th~. cision format. On all moves from the MC68882 to memory

case with all data formats when packed BCD str~,~$ are (or, to an MC68020, or .MC68030 data register), data is

supplied to the MC68882, the strings are auto~atrwally converted from the internal extended precision format to

converted to extended precision real valuP@~$$,*$ con- the destination data format. Note that data movement

version allows packed BCD numbers to be~~~~~% inputs instructions perform arithmetic operations, since the re-

..,{$!!:~a,~,f\

to any operation. For example: suit is always rounded to the precision selected in the

~.i:;.+i:>,~:?

.:;:’:.“1.,..~.i*..

FADD.P #-6.023E +~~$w FPCR mode control byte. The result is rounded using the

BCD numbers can be output$~~.~,%~e MC68882 in aselected rounding mode and is checked for overflow and

underflow.

format readily used for printingb~~program generated The syntax for the move is:

by ahigh-level language c,~w~h~! For example: FMOVE.<fmt> <ea>,FPn .Move to MC68882

FM OVE,P ,@&~$.Q@FFER{# –5} FMOVE.<fmt> FPm,<ea> Move from MC68882

This instruction con$~t@ the floating-point data reg- FMOVE.X FPm,FPn Move within MC68882

ister 3(FP3) cont~~{~. intd apacked BCD string with five where:

digits to the rigHt&~t#& decimal point (FORTRAN Ffor- <ea> is an MC68020 or MC68030 effective address

,{>$,.~i:

~?,~,,,.,.?~~

mat). .,~~..’,\,\t$s,,} operand.

.,.$,

?$;, .\k,, ,<fmt> is the data format size.

FPm and FPn are floating-point data registers.

~.,,,

~;...:,~

$$?~~~t~’formats described above are supported or-

thB~Q”flBlly by all arithmetic and transcendental opera- MOVE MULTIPLE REGISTERS

$~~&*and by all appropriate MC68020 or MC68030 The floating-point move mul~iple instructions on the

~dressing modes. For example, all of the following are MC68882 are much like the integer counterparts on’the

legal instructions: M68000 Family processors. Any set of the floating-point

FADD.B #O,FPO registers FPOthrough FP7 can be moved to or from mem-

FADD.W D2,FP3 ory with one instruction. These registers are always moved

FADD.L BIGINT,FP7 as 96-bit extended data with no conversion (hence no

FADD.S #3.14159,FP5 possibility of conversion errors). Some examples of the

FADD.D (SP) +,FP6 move multiple instruction are as follows:

FADD.X [(TEMP-PTR,A7)], FP3 FMOVEM (ea>,FPO-FP3/FP7

FADD.P #1.23 E25,FP0 FMOVEM FP21FP41FP6,<ea>

Most on-chip calculations are performed in the ex- The move multiple instructions are useful during con- Q;

tended precision format, and the eight floating-point data text switches and interrupts to save or restore the state

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91 80 0

17-DIGIT : : ~: : ~:

jMANTISSA;!:~j~; PACKED DECIMAL REAL

. . . . . . . . . . :.. . . .

,.:$:.t.

*I,, ~~:~,~.

,.,,.,.*,. Figure 9. MC68882 Data Format Summary

.?::$:$‘..\..i:$\*.~~

.,* >,,,~,>,,,

%*,$\$r......,

*,*\,>~\.a*t&\

i::,,.St,,$..,.

>1>.,>>,,,

:~;

o~a program. These moves are also useful at the start MONADIC OPERATIONS

and end of aprocedure to save and restore the register Monadic operations have one operand. This operand

set of the calling routine, In order to reduce procedure may be in afloating-point data register, memory, or in

call overhead, the list of registers to be saved or restored an MC68020 or MC68030 data register. The result is al- \

can be contained in adata register thus enabling run- ways stored in afloating-point data register. For example,

time optimization by allowing acalled routine to save as the syntax for square root is:

few registers as possible, Note that no rounding or ov- FSQRT.<fmt> <ea>,FPn or,

erflow/underflow checking is performed by these oper- FSQRT.X FPm,FPn or,

ations, FSQRT.X FPn

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The MC68882 monadic operations available are as fol- the necessary condition checking and reports to the

lows: FABS

FACOS

FASIN

FATAN

FATANH

FCOS

FCOSH

FETOX

FETOXMI

FGETEXP

FGETMAN

FINT

FLINTRZ

FLOGIO

FLOG2

FLOGN

FLOGNPI

FNEG

FSIN

FSINCOS

FSINH

FSQRT

FTAN

FTANH

FTENTOX

FTST

FTWOTOX

MC68020 or MC68030 whether the condition is true or

Absolute Value false. The MC68020 or MC68030 then takes the appro-

Arc Cosine priate action. Since the MC68882 and MC68020 or

Arc Sine MC68030 are closely coupled, the floating-point branch r$~::

Arc Tanqent operations execute very quickly. Q;.>

Hyperb&ic Arc Tangent The MC68882 conditional operations are:

Cosine FBCC Branch

Hyperbolic Cosine FDBcc Decrement and Branch,. ~$:<~

eto the xPower FSCC Set According to CoQQi~~~S

eto the XPower –1 FTRAPcc Trap-on Condition ~’ $’! “

Get Exponent (with an Opti~”~l~~&?#meter)

Get Mantissa ,~*./.J!:{&,

where: ~:.

,+*~!.,*Q:*?,.

Integer Part cc is one of the 32 floatind~@n$-~Onditional test

Integer Part (Truncated) specifiers as given in~%~~~@’

Log Base 10 **..*. .

1.$.,fy

Log Base 2‘.,., ~!?L.-

>~/.

:i::~,7..,}

\;h\,,y~\

Log Base e~...<,.,,

\~:’’’\%:.,*;t

Log Base eof(x +1)Table 2. ,@~fi,~?-Point Conditional

Negate ,e~;~~ Specifiers

Sine ‘...,

Simultaneous Sine and Cosine

Hyperbolic Sine

Square Root

Tangent

Hyperbolic Tangent

10 to the xPower

Test >;):.’.

f:..

2to the xPower &;i,ih;,~<+

\$y[.::\k,

>.. ‘~>’

~~..*:

,.,,

....

DYADIC OPERATIONS .J,,

~.+is

~~,’:~::\.

Dyadic operations have two operands e~$~$~’~~ first

operand is in afloating-point data regis\@Y, %?~orYt or

an MC68020 or MC68030 data registe~~’$:~~.:;~cond oP-

erand is the contents of afloating-p~~f$~~~% register. The

destination is the same floating-p~$~%.~%ta register used

for the second operand. For ex~&~l,~the syntax for float-

*,W,, , ,

ing-point add is: i..

FADD.<fmt> <~pP;&$

FADD.X .~~,~~n

The dyadic oPeratiom$~/$@Table with the MC68882 are as

follows: ,.,..>,:2$

.<.:.

,Fi:}’~”h

FADD ~,

,.:,..,,?$~‘,l&Add

FCMP,$Y2]Y, ‘;$r” Compare

FD,~~$;\;* Divide

F~,@J> Modulo Remainder

i$y~~ Multiply

ik~5Q$M IEEE Remainder

*$~*FSCALE Scale Exponent

?**T::.<,..*,...y

.\$.,~:;.,,.: FSGLDIV Single Precision Divide

;,\,:,.

“\/.$, FSGLMUL Single Precision Multiply

FSUB Subtract

BRANCH, SET, AND TRAP-ON CONDITION

The floating-point branch, set, and trap-on condition

instructions implemented by the MC68882 are similar to

the equivalent integer instructions of the M68000 Family

processors, except more conditions exist due to the spe-

cial values in IEEE floating-point arithmetic. When acon-

ditional instruction is executed, the MC68882 performs

.....

~.:...>

Mnemo@$”~,,,:,,, Definition

“,,,.:\’.$$..\.\‘::,,.

\~,.i~.-~*L

,$, NOTE

\~.~~,.a,,.,{:

T@~$@lFB~lngconditional tests do not set the BSUN bit

.%&int~g, status register exception byte under any circum-

‘%$~tances.

jF“ False

~EQ Equal

OGT Ordered Greater Than

OGE Ordered Greater Than or Equal

OLT Ordered Less,Tha.n

OLE Ordered Less Than or’ Equal

OGL Ordered Greater or Less Than

OR Ordered

UN Unordered

UEQ Unordered or Equal

UGT Unordered or Greater Than

UGE Unordered or Greater or Equal

ULT Unordered or Less Than

ULE Unordered or Less or Equal

NE Not Equal

TTrue

NOTE

All the conditional tests below set the BSUN bit in the

status register exception byte if the NAN condition code

bit is set when aconditional instruction is executed.

SF Signaling False

SEQ Signaling Equal

GT Greater Than

GE Greater Than or Equal

LT Less Than

LE Less Than or Equal

GL Greater or Less Than

GLE Greater Less or Equal

NGLE Not {Greater, Less or Equal)

NGL Not (Greater or Less)

NLE Not (Less or Equal)

NLT Not (Less Than)

NGE Not (Greater or Equal)

NGT Not (Greater Than)

SNE Signaling Not Equal

ST Signaling True

MOTOROLA MC-

10 BRW/Rev. 3

,..,..,,,;....... . . . ,,. ,.. , . ... . . ..

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.,. ...

MISCELLANEOUS INSTRUCTIONS unique format word prevents asaved MC68881 context

Miscellaneous instructions include moves to and from from being restored into an MC68882 and vice versa.

the status, control, and instruction address registers, Also Second, the BSUN (Branch or Set on Unordered), SNAN

included are the virtual memory/machine FSAVE and (Signaling Not-A-Number), OPERR (Operand Error), OVFL

FRESTORE instructions that save and restore the internal (Overflow), DZ (Divide by Zero) and INEX (Inexact result)

state of the MC68882. floating-point exception handlers must have these min-

FMOVE <ea>, FPcr Move to Control Register(s) imum requirements:

FMOVE FPcr,<ea> Move from Control Register(s) 1. An FSAVE must be executed before any other

FSAVE <es> Virtual Machine State Save

FRESTORE <es> floating-point instruction,

Virtual Machine State Restore ..~~~.j$

2, ABSET or sjmilar instruction that sets’~~%1 of

the BIUflag word (located in the sa~~~J~T& state

frame), ‘.. ::>..~.(i:,$.’

<.‘Stk,itl?,)$,,..

ADDRESSING MODES 3. An FRESTORE instruction mus$~~i>kecuted be-

fore the RTE instruction. ~~,,o +t’:s

The MC68882 does not perform address calculations, ‘.<.!... .:.~!

,t>.?:.~~$\\ *1,>

Thus, if the MC68882 instructs the MC68020 or MC68030 The above requirements are ~&J<~p]icable to interrupt

to transfer an operand via the coprocessor interface, the handlers that do not conta~d~ny’%oating-point instruc-

MC68020 or MC68030 performs the addressing mode cal- tions. For interrupt hand~~~~wt have floating-point in-

cubations requested in the instruction, In this case, the structions, only req~?~gmnts #1 and #3 must be

instruction is encoded specifically for the MC68020 or ,.3M,:,. *

implemented. ~~t,~*<>,*,

~.+ ,..,,

MC68030, and the execution of the MC68882 is depend- \.$\.h..

*;!$*N,,.~:$?

~$’&,\

ent only on the value of the command word written to ~,:i,1,$,, ‘~$+:$

the MC68882 by the main processor. FMN~~@~ SIGNAL DESCRIPTIONS

This interface is flexible and allows any addressing j; ~,c

,>.

mode to be used with floating-point instructions, For the ,!s’.!..?,~,$1’

M68000 Family, these addressing modes include im- The$~.UoWtng paragraphs contain abrief description

mediate, postincrement, predecrement, data or address ofj~e iti~,ut and output signals for the MC68882 floating-

rY’~fi@groups as shown in Figure 10.

of the MC68020 and MC68030. Some addressing modes ~k;%k:,,f~

are restricted for instructions consistent with the M6800&$Y;~$,:j NOTE

Family architectural definitions (e.g.; program counter “’ik, The terms assetiion and negation are used exten-

relative addressing is not allowed for adestination o~~ sively to avoid confusion when describing “active-

erand). ,7{!’*:,.

-> ., ~s?

:~:.,., low” and “active-high” signals. The term assert or

The orthogonal instruction set of the MC6~$&~$the

flexible branches and addressing modes o&~~~~r68020/ assertion is used to indicate that asignal is active

MC68030 allow aprogrammer or acQ~p~&’’writer to or true, independent of whether that level is rep-

resented by ahigh or low voltage. The term negate

think of the MC68882 as though it is,,~~$~fithe MC68020 or negation is used to indicate that asignal is in-

or MC68030. There are no specia~ ‘~~t~$cllons imposed active or false.

by the coprocessor interface, ~~’~;~$j~ating-point arith-

metic is coded exactly like inta$erjarithmetic.

,,,,:s.,:,.id.:,~,\. ADDRESS BUS (AO through A4)

‘~*,*.,

!::,’ ~.~

\.$~,,‘:*1**,i.$l+ These active-high address line inputs are used by the

,~t.,’.,.1,.‘.-,

.:,:,

.~,\p\+ main processor to select the coprocessor interface reg-

MC6W8PQ6MPATIBILITY ister locations located in the CPU address space. These

.>$:,.d~” lines control the register selection ‘as listed in Table 3.

,,~:,:-: ..,“+

Using the ~~~,~~~~n an existing MC68881 socket does

not require&@~~*are changes nor user-software modi- “Cc

fications;<~J~@~entation of multiple floating-point in- /7AO-A4

structi@W ~~~cution concurrency gives the MC68882 aGNO 1

*13

per~~’@&e advantage over the MC68881. However, to

g~.,~mtee that the floating-point exception model main- DO-D31

~~~~~~the precepts of asequential execution model, some MC6B882

~~stems-level software modifications are needed to up- FLOATING-POINT m

grade the system to operate properly with an MC68882. COPROCESSOR fl~

First, note that the idle and busy state frames (gener- CLK E

ated by the FSAVE instruction) are both 32 bytes larger mP*E

with the MC68882 than the MC68881, The offsets for the ●*

exceptional operand, the operand register word, and the RESET DSACKO

BIU flag word from the top of the saved idle state frame +SENSE >DSACK1 *

are 32 bytes more than that of the MC68881. However, a

unique format word is generated by the MC68882 ens-

bling the system software to detect this difference. The Figure 10. MC68882 Input/Output Signals

MC- MOTOROLA

BRW/Rev. 311

,.,,, .7.. .,.,.,.,,,........................ .......,,.,,...,, . ......... ... ....,,.,.,,. ............, ..,,, ..... . . ,,, ,,.. .... . ,,. .. ..... . . .,, .. ... ...... ......>..,..,,.......................,..”...,., ,,,..,.,,,.,...,... .,.................;,..,.,,,

,, .,.

,,, ,.,

,,- .;,

,,” ., ..< ,., ,.

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....-

Table 3. Coprocessor Intetiace

A4-AO Offset Mdth Type Register

Oooox $00 16 Read Response

Ooolx $02 16 Write Control

Oolox $04 16 Read Save

Oollx $06 16 R~ Restore

Oloox $08 16 – (Reserved)

Ololx $OA 16 Write Command

Ollox $Oc 16 – (Reserved)

Olllx $OE 16 Write Condition

1Ooxx $10 32 Rfi Operand

101OX $14 16 Read Register Select

Iollx $16 16 – (Reserved)

11Oxx $18 32 Read Instruction Address

Illxx $lC 32 RR Operand Address

When the MC68882 is configured to operate over an 8-

bit data bus, the AO pin is used as an address signal for

byte accesses of the coprocessor interface registers. When

the MC68882 is configured to operate over af16- or 32-

bit system data bus, both the AO and the SIZE pins are

strapped high and/or low as listed in Table 4.

ADDRESS STROBE (AS)

This active-low input signal indicates that there is a

valid address on the address bus, and both the chip select

(CS) and read/write (R~) signal lines are valid.

...

~:-

CHIP SELECT (CS) .::.

This active-low input signal enables the main processor

access to the MC68882 coprocessor interface registers.

When operating the MC68882 as aperipheral pro$essor,

the chip select decode is system dependent (i.~~~j~$the

chip select on any peripheral). “...,

.\\!.+’*:>},i,~??

..$’s,*k.

~;,

.?;.l\

.,,.\$,~\...:~

READ/WRITE (R/~) ‘%$,,

*;>K:,,‘:3,.“~~

,h+.t.::~,.

!,.’.t..i~..,!

This input signal indicates the di~~8]o~#@Y abus trans-

action (read/write) by the main~f~~~sbr. Alogic high

(1) indicates aread from the @8,@~, an~ alogic low

(0) indicates aw~te to the ~~~8&The RN signal must

be valid when AS is ass@Xl@+~j:

~..+

“.**,?,)$.!+

.‘X.,,,\ -$:

~:<:~,....,/ ,

DATA STROBE (DS)’:Xj~,~,t.$~

,;~.>t,,.,>+f,

This active-lowin:~~~ignal indicates that there is valid

data on the d~~~:~ys during awrite bus cycle.

‘?,

~Kese active-low, three-state output signals indicate

..?~,,c&hpletion of abus cycle to the main processor. The

i$$it,~@8882 asserts b~h the DSACKO and DSACKI signals

Table 4. System Data Bus Size Configuration *$rS$$upon assertion of CS.

‘-l?+ If the bus cycle is amain processor read, the MC68882

AO SIZE Data Bus ~,:’

~i$t

,$~$’ asserts DSACKO and DSACKI signals to indicate that the

.; ‘>:,},

—Low 8-Bit information on the data bus is valid. (Both DSACK signals

.tt,. *>:.,.

..*.,,, ,,.,,,

Low High may be asserted in advance of the valid data being placed

16-Bi~$$’Q$y‘?’ on the bus. )If the bus cycle is amain processor write to

.,?, ... :.

High High 3~*qk$;,.~’ the MC68882, DSACKO and DSACKI are used to acknowl-

.~~,;~y$. edge acceptance of the data by the MC68882.

,. ‘\\.~J~.\.’~:i,>

,,..:..

,,,4).>‘‘%;V,$~$ The MC68882 also uses DSACKO and DSACKI signals

DATA BUS (DO through D31 )~~” ‘“~~ to dynamically indicate to the MC68020/MC68030 the

This 32-bit, bidirectional, +~k~%%~bte bus serves as the “port” size (system data bus width) on a cycle-by-cycle

general purpose data,~~~h,~etween the MC68020/ basis, Depending upon which of the two DSACK pins are

MC68030 and the MC~~&~.’’’Regardless of whether the asserted in agiven bus cycle, the MC68020/MC68030 as-

MC68882 is operat~d a~$~’coprocessor or aperipheral sumes data has been transferred to/from an 8-, 16-, or

32-bit wide data port. Table 5lists the DSACK assertions

processor, all in~,@$@o,gessor transfers of instruction in-

formation, op~r,~~d$$~ata, status information, and re- that are used by the MC68882 for the various bus cycles

quests for $~~J~@’&ccur as standard M68000 bus cycles. over the various system data bus configurations.

The MQ@,*~will operate over an 8-, 16-, or 32-bit Table 5indicates that all accesses over a32-bit bus

syste~%at%~,bbs. Depending upon the system data bus where A4 equals zero are to 16-bit registers, The MC68882

conJ~@~~{a@n, both the AO and SIZE pins are configured implements all 16-bit coprocessor interface registers on

s~:~?t~a”lly for the applicable bus configuration. (Refer to data lines D16-D31 (to eliminate the need for on-chip

:$Q~*ESS BUS (AO through A4) and SIZE (SIZE) for fur- multi plexers); however, the MC68020/MC68030 expects

‘&#rdetails). 16-bit registers that are located in a32-bit port at odd

$$j word addresses (Al =1) to be implemented on data lines

DO-DI5. For accesses to these registers when configured

SIZE (SIZE) for 32-bit bus operation, the MC68882 generates DSACK

This active-low input signal is used in conjunction with signals as listed in Table 5to inform the MC68020/

the AO pin to configure the MC68882 for operation over MC68030 of valid data on D16-D31 instead of DO-D15.

an 8-, 16-, or 32-bit system data bus. When the MC68882 An external holding resistor is required to maintain

is configured t~erate over a16- or 32-bit system data both DSACKO and DSACKI high between bus cycles. In

bus, both the SIZE and AO pins are strapped high and/or order to reduce the signal rise time, the DSACKO and

low as listed in Table 4. DSACKI lines are actively pulled up (negated) by the

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Table 5. DSACK Assertions

Data bus A4 DSACKI DSACKO Comments

32-Bit 1Low Low Valid Data on D31-DO

32-Bit oLow High Valid Data on D31-D16

16-Bit xLow High Valid Data on D31-D16 or D15-DO

8-Bit xHigh Low Valid Data on D31-D24,.D23-D16, D15-D8, or D7-DO

All xHigh High Insert Wait States in Current Bus Cycle

MC68882 following the rising edge of AS or DS, and both

DSACK lines are then three-stated (placed in the high-

impedance state) to avoid interference with the next bus

cycle.

RESET (RESET)

This active-low input signal causes the MC68882 to

initialize the floating-point data registers to non-signaling

not-a-numbers (NANs) and clears the floating-point con-

trol, status, and instruction address registers.

When performing apower-up reset, external circuitry

should keep the RESET line asserted for aminimum of

four clock cycles after VCC is within tolerance. This as-

sures correct initialization of the MC68882 when power

is applied, For compatibility with all M68000 Family de-

vices, 100 milliseconds should be used as the minimum.

When performing areset of the MC68882 after VCC has

been within tolerance for more than the initial ~ower-uo

~~~~.j,

.:J;:::{:.Jy<,:~:!l~,

time and must conform to minimum and m~~~~.~’’pe-

riod and pulse width times. *~. ‘~~~j,?~

~’~$..;..,,w~\.:.\l~.

“:$w,.,.,<,,,

,*S.$.*

‘y,,

SENSE DEVICE (SENSE) ,,:,,?

it,..>,k.:.:t.:,,,.$

~!*!V$,$~

This pin may be used optionally ~~~fi,$~ditional GND

pin or as as indicator to exte{~’~?$t~~dware that the

MC68882 is present in the sys~$m$%~~ signal is internally

connected to the GND of t~:~~$~, but it is not necessary

to connect it to the ext~w$$?ound for correct device

operation. Ifa pullup rp~~$~iwhich should be Iargerthan

10 kohm) is conneqq~t~%~s pin location, external hard-

.a*~J:~,x~:,<,:i,.

ware may sense, the~resence of the MC68882 in asys-

tem. .~,~t~.~$}.}.

~t:.,it,$*!>:$;$.

,b~.,$7::+

~owER ~gc~j ~ND)

,.\q,~.,...*,:,,.,~.,,,

Thes%i~~ns provide the supply voltage and system ref-

er%a$e Iekl for the internal circuitry of the MC68882, Care

..~~uf~ be taken to reduce the noise level on these pins

time, the RESET line must have an asserted p~lse width ,P,$~fi~ appropriate capacitive decoupling,

which is greater than two clock cycles. For compatibility .*,.‘*>$*s

‘~;$,::::b%?$:

with all M68000 Family devices, 10 clock cycles should I;,, -ho CONNECT (NC)

be used as the minimum. .,<..(*’

,$,$

CLOCK (CLK) ..,7,.‘!..!,$:,,,,

i~,,!, .?*t.

The MC68882 clock input is a~L-com~#~W&~ignal

that is internally buffered for development~~,th~ ?nternal

clock signals, The clock input should ,Qd~$:&~%fi:stantfre-

quency square wave with no stretchi~~~$~$haping tech-

niques required. The clock should q~t~ ~ated offat anY

.,:~:,?,’.....sy.>.,’

... One pin of the MC68882 package is designated as a no

connect (NC). This pin position is reserved for future use

by Motorola, and should not be used for signal routing

or connected to VCC or GND.

SIGNAL SUMMARY

Table 6provides asummary of all the MC68882 signals

described in the above paragraphs.

t!;:>\ <.

SignaK<#a*eJ’o

\Mnemonic lnputiOutput Active State Three State

:~i:i\y

Address Bus,~>’:$ AO-A4 Input High —

{

Data Bus ‘$:$**~~#F DO-DI 3Input/Output High Yes

Size ,%~~>)~ SIZE Input Low —

?~$?$s~tro be GInput Low —

, , ‘&i,@S-elect mInput Low —

~,t:,)...~

‘@:J;~‘:’%ad/Write Rim Input High/Low

.$~,+,)?:.,~\‘~3—

‘“ ‘$~’ Data Strobe mInput Low —

.,t{,!~

~.~ Data Transfer and Size Acknowledge DSACKO, DSACK1 output Low Yes

Reset RESET Input Low —

Clock CLK Input ——

Sense Device SENSE Input/Output Low No

Power Input Vcc Input ——

Ground GND Input — —

MC-

BR=/Rev. 3

. .... ......... . ... ,, ... .,,.,.., ... . .., . .. ... .. . .. . . . . .. .. .,,, ..,.

,.” ,,, ,,.

,’ ,..

MOTOROLA

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INTERFACING METHODS

MC68882/MC6801 OOR MC68030 INTERFACING

The following paragraphs describe how to connect the

MC68882 to an MC68020 or MC68030 for coprocessor

operation via an 8-, 16-, or 32-bit data bus,

32-Bit Data Bus Coprocessor Connection

Figure 11 illustrates the coprocessor interface connec-

tion of an MC68882 to an MC68020/MC68030 via a32-bit

data bus. The MC68882 is configured to operate over a

32-bit data bus when both the AO and SIZE pins are con-

A16-A19 ~DEcoDE I-v.

SIZE

netted to VCC.

FCO-FC2 a-

CHIP

—SELECT E

OECODE

—Vcc SIZE

A20-A31

A16-A19

A13-A15

A5-A12

A1-A4

~AO

0R~

zD24-031

~A1-A4

D24-D31

D16-D23

D8-D15

DO-D?

FCO-FC2

016-D23

D8-D15

DO-D7

DSACKO

DSACK1

MAIN PROCESSOR

CLOCK

D24-D31

D16-D23

08-015

DO-D7 m

D24-D31

D16-D23

./,:,

,,..

,,,,,$:/;

16-Bit Data Bus @+@oce&sor Connection

Figure 12 ill.y~~~#’the coprocessor interface connec-

tion of an M~m2 to an MC68020/MC68030 via a16-bit

data bu~i,~k~WC68882 is configured to operate over a

16-bit,@~d~~ bus when the SIZE pin is connected to VCC,

and. t~e ~0 pin is connected to GND. The sixteen least-

s~~k~?aritdata pins (DO-D15) must be connected to the J

$:a~~~~en most-significant data pins (D16-D31 )when the

!&&8882 is configured to operate over a16-bit data bus +

MAIN PROCESSOR

Da-D15

DO-07

=H DSACKO

OSACK1

COPROCESSOR

~.e., connect DOto D16, DI to D17, . . . and D15 to D31). CLOCK CLOCK

The DSACK pins of the two devices are directly con-

nected, although it is not necessary to connect the DSACKO figure 13. 8-Bit Data Bus Coprocessor Connection

pin since the MC68882 never asserts it in this configu-

ration. bus. The MC68882 is configured to operate over an 8-bit

8-Bit Data Bus Coprocessor Connection data bus when the SIZE pin is connected to GND. The

Figure 13 illustrates the connect of an MC68882 to an twenty-four least-significant data pins (DO-D23) must be

MC68020/MC68030 as a coprocessor over an 8-bit data connected to the eight most-significant data pins (D24-

MOTOROU MC-

14 BRW/Rav. 3

,., ,, . . . . ....,,,. .. ... ..,,. -

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D31) when the MC68882 is configured to operate over an When connected as aperipheral processor, the MC68882

8-bit data bus (i.e., connect DO to D8, D16 and D24; DI chip select (CS) decode, is system dependent. If the

to D9, D17, and D25; ...and D7 to D15, D23 and D31). MC68000 is used as the main processor, the MC68882 CS

The DSACK pins of the two devices are directly con- must be decoded in the supervisor or user data spaces,

netted, although it is not necessary to connect the DSACKI However, if the MC68010 is used for the main processor,

pin since the MC68882 never asserts it in this configu- the MOVES instruction may be used to emulate any CPU

ration. space access that the MC68020/MC68030 generates for

coprocessor communications. Thus, the CS decode logic

MC68882-MC68000/MC68008/MC68010 INTERFACING for such systems may be the same as in an MC68020/

The following paragraphs describe how to connect the MC68030 system, such that the MC68882 will not-’hse any

MC68882 to an MC68000, MC68008, or MC6801 Oproces- .,;*s.t::\~&

part of the data address spaces. k};<..N*..

sor for opertion as aperipheral via an 8- or 16-bit data ,,i#:*~”

,,.:;{$:,~,‘,”.:

~.i

bus. ~~

,* ~$$,

8-Bit Data Bus Peripheral Processor C,~~~f~8n

16-Bit Data BUSPeripheral Processor Connection Figure 15 illustrates the connecti,~hjd~j~k MC68882 to

an MC68008 as aperipheral proc~$@’’r,@ver an 8-bit data

Figure 14 illustrates the connection of an MC68882 to <.~1.g,,!!*,*),

bus, The MC68882 is configur~ tm~perate over an 8-bit

an MC68000 or MC68010 as aperipheral processor over data bus when the SIZE piq,,is’”&&#nected to GND. The

a16-bit data bus. The MC68882 is configured to operate eight least-significant d~ti$~~s (DO-D7) must be con-

over a16-bit data bus when the SIZE pin is connected to netted to the twenty:f~~~~~st-sig nificant pins (D8-D31 )

Vcc, and the AO pin is connected to GND. The sixteen when the MC68882a{,~.~~b@

figured to operate over an 8-

least-significant data pins (DO-DI 5) must be connected to bit data bus (i,e,, q~@M’DO to D8, D16, and D24; DI to

the sixteen most-significant data pins (D16-D31 )when the D9, D17, and ~$; .’!:,*and D7 to D15, D23, and D31), The

MC68882 is configured to operate over a16-bit data bus DSACKO pin$$,~~~ MC68882 is connected to the DTACK

(i.e., connect DO to D16, DI to D17, ,.. and D15 to D31). pin of th@<W~m08, and the DSACKI pin is not used.

The DSACKI pin of the MC68882 is connected to the Wh~@ ~-cted as aperipheral processor, the MC68882

DTACK pin of the main processor, and the DSACKO pin chip #&#ct (CS) decode is system dependent, and the CS

is not used. ~#st be:tiecoded in the supervisor or user data spaces.

-,“,

1r●

FCO-FC2 --+ CHIP

A16-A19 --+ SELECT

DECDDE

A13-A15 --* -E

(SYSTEM

A5-A12 -–* DEPENDENT) ,,

GND+ SIZE

Al -A4 >Al -A4

AO ~AO

mB~E

m+Ez

R~ ..-R~

+D24-D31

*D16-D23

*D8-D15

00-07 4*DO-D7

DTACK ~DSACKO

—DSACK1

M’AIN PRbCESSOR COPROCESSOR

MAIN PROCESSOR COPROCESSOR CLOCK CLOCK

CLOCK CLOCK

[.;\, )

i:. ;$4

‘“w Figure 14. 16-Bit Data Bus Peripheral Figure 15. 8-Bit Data Bus Peripheral

Processor Connection Processor Connection

MC688B2 MOTOROLA

BRW/Rev. 315

.. .... ............-,,. .. . ., ,,.,,............ .. ,...-,, ..... ..... ,:. .:,.,.,..., !-.---...........-. --- .,,.. . .. ... . .. .. .... ...., .,,. ... .. .... ...

!, ,.’, .

,“’

., ,. ...: “:. ,, .,..:,, ,.’,,,,,,. ,. ,,

,,, .,, . . . . .

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,, .. .. ... ...-.,.:...... ............. . ... . . . .. ..... . . .. .,.-.’, . .

ELECTRICALSPECIFICATIONS

MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Voltage Vcc –0.3 to +7.0 v

Input Voltage ~n –0.3 to +7.0 v

Operating Temperature TA oto 70 ‘c

Storage Temperature T~tq –55to +150 ‘c

THERMAL CHARACTERISTICS

Characteristic Symbol Value Rating

Thermal Resistance —Ceramic “cm

Junction to Ambient 9JA 33

Junction to Case 8JC 15

POWER CONSIDERATIONS <,*,:b’+~

The total thermdk,g@Wstance of apackage (0.jA) can be

The average chip-junction temperature, TJ, in ‘C can :.?. -.

separated in,t$’{~&o components, OJC and eCA, repre-

be obtained from: senting th@.*Q~#$i~eFtoheat flow from the semiconductor

TJ=TA+(PD06JA) (1) junctio,$.t$,th~ package (case) surface (eJc) and from the

where: case tq $he+Dutside ambient (OCA). These terms are re-

TA =Ambient Temperature, ‘C lat@ b~she equation:

8JA =Package Thermal Resistance, .ti.,.$,m~

~s~,,

... eJA= 6JC+ 6CA (4)

Junction-to-Ambient, OC/W J#“’S$JC is device related and cannot be influenced by the

pD =PINT+ Pi/0 3,J$&&r. However, 6CA is user dependent and can be min-

PINT =ICC xVCC, Watts —Chip Internal Power +.+,?!~$t,:.,..,.,,.

%,+$~tlmized by such thermal management techniques as heat

Pi/0 =Power Dissipation on Input and Output ‘

.:k.

Pins —User Determined ,,1>:. .’:’

.....

For most applications P1/O<PINT and can be ~~$~q~ed.

The following is an approximate relation~~f~%ween

PD and TJ (if Pi/0 is neglected): ?,:,.:\

,,:.+;.

PD =K+ (TJ +273”C] ~~’$!?j’~> (2)

Solving equations (1) and (2) for.@~~#l@

K= PD ●(TA+ 273°C) t8j~$PD2 (3)

where Kis aconstant pertainiq~~~~~ particular part. K

can be determined from e~M&~A&~(3) by measurin9 pD

(at equilibrium) for akno~n ~~. Using this value of K,

the values of PD and T&#~~~~&’obtained by solving equa-

tions (1) and (2) ite$at~~l&%or any value of TA.

:,<

,;~~~

d:”

.J:{.;,!,.\~.}\\.\.

,, \‘:?*.,,{>\

sinks, ambient air cooling, and-thermal convention. Thus,

good thermal management on the p,art of the user can

Significantly reduce 6CA so that eJA approximately equals

eJc. Substitution of eJc for eJA in equation (1) will result

in alower semiconductor junction temperature.

Values for thermal resistance presented in this docu-

ment, unless estimated, were derived using the proce-

dure described in Motorola Reliability Report 7843,

“Thermal Resistance Measurement Method for MC68XX

Microcomponent Devices,” and are provided for design

purposes only, Thermal measurements are complex and

dependent on procedure and setup, User derived values

for thermal resistance may differ.

DC ELECTRl&#&j&ARACTERISTICS (Vcc =5.o Vdct5%; GND=OVdc; TA= O°Cto 700C)

..,t .,,.1,.

..l\,...*+

*:4>*.g ~,.,

,,.,....

... Characteristic Symbol Min Max Unit

lnpu#Wg~+oltage vlH 2.0 Vcc v

?k~:~’:~dw \,oltage vlL GND –0,5 0.8 v

—~~

$~ji~t Leakage Current @t5.25 V—— ——

CLK, RESET,R/~, AO-A4, CS, DS, AS, SIZE Iin —10 WA

~Hi-Z (Off State) ,Input Current ~1.2.4 V/O.4V~, m, DO-D31 ITSI —20 FA

Output High Voltage (IOH=-400 wA) ~, m, DO-D31 vOH 2.4 —v

Output Low Voltage (iOL=5,3 mA) ~, ~, DO-D31 vOL —0.5 v

Output Low Current (VOL= GND) SENSE IOL —500 PA

Power Dissipation pD —0.75 w

Capacitance* (Vin =0, TA=250C, f= 1MHz) Cin —20 pF

Output Load Capacitance CL —130 pF

*Capacitance is periodically sampled rather than 10070tested.

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AC ELECTRICAL CHARACTERISTICS —CLOCK INPUT

(VCC=5.O Vdc* 570; GND=O Vdc; TA=O to 70°C; refer to Figure 16)

16.67 MHz 20 MHz 25 MHz 33.33 MHz

Num Characteristic Min Max Min Max Min Max Min Max ‘nit

Frequency of Operation 816.67 12.5 20 12.5 25 16.7 33.33 MHz

1Cycle Time 60 125 50 80 40 80 30 60 ns

2,3 Clock Pulse Width (Measured from 1.5 Vto 1.5 V24 95 20 54 15 59 14 66 q,s

for 33 MHz) ..,’..,.,

..:’,}*..*,,i+i.,,

4,5 Rise and Fall Times —5—5—4—3$’

,,“ ‘F.:.

;,,, Rs

~!?,~.a?>,,,\$*

(VCC=5.O Vdc* 5%; GND=O Vdc; TA=O ~~@@$refer to Figures 17, 18, and 19)

~1$,* $>\.*::>.”

:.‘,, .,,.

,.?*\\>,.,/<”.$.$.

,* ?a:$)$!&.~(‘16.67 MHz 20 MHz 25 MHz 33.33 MHz

Num Charac&r?8$~<<” Min Max Min Max Min Max Min Max Unit

-~+.*:.,!

65 Address Valid to ~As&’~#’@ 15 —10 —5—5—ns

6A5 Address Valid to ~*As~~ed (Read) 15 —10 —5—5—ns

6B5 \

Address Valid ~“~~k~setied (Write) 50 —50 —35 —26 —ns

76 ~Negat~@~o A~~ess Invalid 10 —10 —5—5—

:,‘,+:,.,+‘> ns

7A6 ~Nega@&i~@yAddress Invalid 10 —10 —5—5—ns

89 ~%g~<$d to ~Asserted o—o—o—o—ns

8A9 ,.* %~*&ated to ~Asserted (Read) o—o—o—o—ns

q~ f,k.@Asserted to ~Asserted (Write) 30 —25 —20 —15 —ns

),~.y~i@_

‘~:;p AS Negated to ~Negated 10 —10 —5—5—ns

~?~i<%x ~Negated to ~Negated 10 —10 —5—5—ns

‘10 R% High to ~Asserted (Read) 15 —10 —5—5—ns

10A Rfi High to ~Asserted (Read) 15 —10 —5—5—ns

IOB R/~ Low to ~Asserted (Write) 35 —30 —25 —25 —ns

11 ~N_egated to R~ Low (Read) or ~Negated to 10 —10 —5—5—ns

R/W High (Write)

11A ~Negated to R/~ Low (Read) or ~Negated to 10 —10 —5—5—ns

Rfi High (Write)

—Continued —

uMC68882 MOTOROLA

BR~/Rev. 317

“--. *P8,!!!\,m,m~.,:,!..

. .......-..t.Fo.T..!.,!r,,.J.>.,,.,,ryrTAw.w..-r.Tw.,,l,t,,..,q,Tm,f.7.--, yT,..,.,..~,.!.,.........-;.,$-: ..!.,,~,...,,-.,.-.1..!.............,:.....-,........... .,?,,.,(:, ,, ..,.,.:...........

,,;, , . ...,..,:,:,..;., ,,,, . :: , ,..

,,...:., .<.........,.r.,,~.!~?--~,Y,.,-.,,,,,1,.-...,..~.”:’.,~,.;l..:,->*T~,

,,,!,,,t.. . . ,.

‘:.. ,~.,: ......7-.... (, ,’. ,, ,,

,,.,’., ... ,. ,1,, ,., , .. ,’:,.,. ;,,..

,.. ,

‘, ”., ‘,’.

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AC ELECTRICAL SPECIFICATIONS —READ AND WRITE CYCLES (Continued)

16.67 MHz 20 MHz 25 MHz 33.33 MHz

Num Characteristic Min Max Min Max Min Max Min Max Unit

12 ~Width Asserted {Write) 40 —38 —30 —23 —ns r~~. ,

13 ~Width Negated <:, ,

40 —38 —30 —23 —ns

13A4 =Negated to ~Asserted 30 —30 —25 —18 —ns

142 ~, ~Asserted to Data-Out Valid) (Read) —80 —60 —45 —

15 ~Negated to Data-Out Invalid (Read) o—o—o—o

16 ~Negated to Data-Out High Impedance (Read) —50 —30 —30

17 Data-In Valid to ~Asserted (Write) 15 —10 —5—:$ &~~:~-ns

18 ~Negated to Data-In Invalid (Write) 15 —10 —57

192

~<:~ ‘(~’ –n5

— —

START True to DSACKO and DSACK1 Asserted —50 —35 —,$ ‘$~b,. i– 20 ns

19A7 DSACKO Asserted to DSACKI Asserted (Skew) –15 15 –lo 10

— —

-$*., $:.10 ‘–5n5

DSACKO or DSACKI Asserted to Data-Out Valid —50 —43 ,j;~:,<p~s 32 —17 ns

218 START False to DSACKO and DSACK1 Negated —50 —30 —20 ns

—_

228 START False to DSACKO and DSACKI High Impedance —70 “– 40 – 30 ns

233,8 START True to Clock High (Synchronous Read) o—o—ns

243 Clock Low to Data-Out Valid (Synchronous Read) —.l,g !-

;,, ,$ 80 —60 .— 45 ns

253S8 START True to Data-Out Valid (Synchronous Read) —,~,g *“_ 80+ —60+ —45+

1.p:(, 2.5 ‘1.5 2.5 1.5 2.5 1.5 2.5 C;:s

263 Clock Low to DSACKO and DSACKI Asserted ..~..>,i:~>~

,, ~ii \

*$ ?’;~75 —55 —45 —30

..... ns

(Synchronous Read) <i,

‘+$>\Jli)~,i,.$

— —

2j3,8 START True to DSACKO and DSACK1 As5~~ted *,~,\::<.,

,J>,,

.x.,*_

“*7,!.. 75+ —55+ —45+ —30+

(Synchronous Read) “<$ 1.5 2.5 1.5 2.5 1.5 2.5 1.5 2.5 CY:S

**>.. :‘

,+:~~$,{>x.-..

NOTES: ~,

(~j, ,.

t:~,.~,

1. Timing measurements are referenced to ~~,.~~m”’a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise ,)

*.*/

noted, The voltage swing through this&@~~$~$~ould start outside, and pass through, the range such that the rise or fall will be

linear between 0.8 volts and 2.o vol~ “ii~(,:}’

2. These specifications only apply if $&$*~882 has completed all internal operations initiated by the termination of the previous

bus cycle when ~was negated~tl, .~, ~~

‘“:;$.’:::<~j:.

3. Synchronous read cycles occ~:$o~’when the save or response CIR locations are read.

4. This specification only ap#}?&s~W->ystemsin which back-to-back accesses (read-write or write-write) of the operand CIR can

occur. When the MC6w&~,$@sed as acoprocessor to the MC68020/MC68030, this can occur when the addressing mode is

Immediate. $*.{:&$

.~~:

5. If the SIZE pin is g~~~~mped to either VCC or GND, it must have the same setup times as do addresses.

6. If the SIZE pin i/’~t#rapped to either VCC or GND, it must have the same hold times as do addresses.

7. This numbW?~,~edu~ed to 5nanoseconds if DSACKO and DSACKI have equal loads.

— —

8. START is ti~~iw~xternal signal; rather, it is the logical condition that indicates the start of an access. The logical equation for

this c~,~~~~o ~m= ~ +~ tR~*~.

9. If a~’~k~~~$nt access is not aFPCP access, ~must be negated before the assertion of ~end/or ~on the non-FPCP acce~

Tk@#@’~cifications replace the old specifications 8 and 8A (the old specifications implied that in all cases, transitions in CS.

g~u~s~ot occur simultaneously with transitions of ~or ~. This is not a.requirement of the MC68882).

}}

,+,:<,i,:.,i

‘{$>$.

,y.lw,,.*

,+~,..,

&,:,?:**~:4

<.bk>l>ib

‘$~~~ ELECTRICAL SPECIFICATION DEFINITIONS are specified with minimum and/or maximum limits, as

The AC specifications presented consist of output de- appropriate, and are measured as shown. Inputs are

lays, input setup and hold times, and signal skew times, specified with minimum and, as appropriate, maximum

All signals are specified relative to an appropriate edge setup and hold times, and are measured as shown, Fi-

ef the clock input and, possibly, relative to one or more nally, the measurement for signal-to-signal specifications

other signals. are also shown.

The measurement of the AC specifications is defined Note that the testing levels used to verify conformance

by the waveforms shown in Figure 20. In order to test to the AC specifications does not affect the guaranteed .:. ‘.

the parameters guaranteed by Motorola, inputs must be DC operation of the device as specified in the DC electrical &‘,,,.,.

driven to the voltage levels specified in.Figure 20. Outputs characteristics. v

MOTOROLA MC6B682

18 BR~/Rev. 3

,. ..,, . . .. .... ,.,.,..

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—.

MC= MOTOROM

BRW/Rev. 319

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+21

—

~,,,,,

‘\,, ,,.

;.,,

MOTOROW MC-

20 BR~/Rev. 3

,,, .,,,,.,,-

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—

S2 Sw Sw Sw Sw S3 S4 S5

MC- MOTOROU

BRW/Rev. 321

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DRIVE

TO 2.4V

CLK A

0.8 v~

ORIVE J~A+

TO 0,5 VB+

OUTPUTS(1) CLK VALID 2,0v‘c2.0v vALID

OUTPUT n0,8V7 ~0,8V OUTPUTn+l

—

-2.0 v

0.8 V

MOTOROU MC=

zBRW/Rev. 3

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—.,

PIN ASSIGNMENTS AND MECHANICAL DATA

PIN ASSIGNMENTS

r~:$, PIN GRID ARRAY

.,J

0000000000

Al R~ GNDDSACK1 D30 D29 D27 D26 D24 D22

0000000000 ——

A3 Vcc CS DSACKO D31 D28 D25 GND D23 D21

00-0 000

~A2 AO Vcc GND D19

o. 000

~A4 D20 D18

= GND 00

D17 D16

00 00

NC Vcc Vcc GND

00 0 q;

RESET GND

000 0D; %~&$

GND CLK GND D9 ,,,:f:&:,>;,Dli

o 0 0 &o 0 0 Q’V,Q,,’”0

Vcc GND GND SENSE D2 D5 GND\$V~ ‘~l~ Dll

o 0 0 0 0 0 0<::.,0’’”0 0

Vcc GND DO D1 D3 D4 ,,?}W6 “~{~~ D8 GND

TDP

VIEW

---

D9 60 61 0E-

GND

RESET

GND

rl K

MC- MOTOROW

BRW/Rev. 323

--- ,.,,. ...<..,>,.,..............;.,,,..,,,. ............. ...,, ,,.:,,, ............. ... . .. . .“----. ....... .... .. ........... ,...,.. ... ... . ..:.’ “..,-t!tl..................-.4. ..- ,. ... ..........

.,.

,.. -, . .

,.,’

,, ’...- ,,, , .:,:, :,’,

.,!,

.. . ,. ,..

.,. , :,.. ,, ,: ;’. ,

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-—

,,.

MOTOROM

24 M~

BR~/Rev. 3

., ..,. . . .. . . ,,. .. . . . . .... .,,, . ,. . . . . ........ .

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FN SUFFIX

PLASTIC LEADED CHIP-CARRIER

CASE 779-02

—B +0,18(0,007)@ T N@P@ L&M@

ru [$1o.18(o.QQ71@ ]T N @-P@ L@M@

7“ A + 0.18(0.0071@ TL@-M@l N@-P@

–R 1+]0.18(0.007)@ \T IL@M @l N@-P@]

a 0.10(0,004)

Il\

IIuDETAIL S

:,*:*...$?0.48 0.013 0.019

NOTES:

1. DUETO SPACELIMITATION,CASE779-02SHALL

BEREPRESENTEDBY A GENERAL(SMALLERI

CASEOUTLINEDRAWING RATHERTHAN

SHOWING ALL68LEADS.

2.DATUMS -L.,M-,-N-,AND -P-DETERMINED

WHERE TOP OF LEADSHOULDER EXITPLASTIC

BODY AT MOLO PARTINGLINE.

3,DIMGl,TRUE POSITIONTO BEMEASURED AT

DATUM -T-,SEATINGPLANE.

4,DIMRAND U DO NOT INCLUDEMOLO

PROTRUSION.ALLOWABLEMOLD PROTRUSION

IS0.25(0,010}PERSIDE,

5.DIMENSIONINGAND TOLERA.NCINGPERANSI

Y14.5M,1982.

6.CONTROLLINGDIMENSION:INCH,

M~ MOTOROLA

BRW/Rev. 3 25

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,. ..

M68000 FAMILY STANDARD ORDERING IN FORMATION,.,

NOTE: Consult Factory for Products Requiring Exte@d~erating Temperatures or Special Processing.

~tf<.i?.<

\.\,

*:\ ‘~:t~+

..!

Motorola Order Number:

.,) :,.

,l&&ot&k~a’’?&servesthe ,right to make changes witho:t f:rrher notice to any products herein to improve reliability, function or design. Motorola

~~sR~ assume any Imblhty ar!slng out of the application or use of any product or circuit described herein; neither does it convey any license

u~er Its patent rights nor the rights of others. Motorola products are not authorized for use as components in life support devices or systems

int%nded for surgical implant into the body or intended to suppo~ or sustain life. Buyer agrees to notify Motorola of any such intended end use

whereupon Motorola shall determine availability and suitability of its product orproducts for the use intended. Motorola and@ are registered

trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity:Affi rmative Action Employer.

Literature Distribution Centers:

USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.

EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive, Blakelands Milton Keynes, MK145BP, England. J

ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; PO. Box 80300; Cheung Sha Wan Post Office; Kowloon Hong Kong.

-MMOTOROLA

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