LM48557 www.ti.com SNAS486D - JULY 2009 - REVISED MAY 2013 LM48557 BoomerTM Mono, Bridge-Tied Load, Ceramic Speaker Driver with I2C Volume Control and Reset Check for Samples: LM48557 FEATURES DESCRIPTION * * * * * * * * * * * The LM48557 is a single supply, mono, ceramic speaker driver with an integrated charge-pump, designed for portable devices, such as cell phones and portable media players, where board space is at a premium. The LM48557 charge pump allows the device to deliver 5.8VRMS from a single 4.2V supply. 1 23 Integrated Charge Pump Bridge-Tied Load Output Differential Input High PSRR I2C Volume and Mode Control Reset Input Advanced Click-and-Pop Suppression Low Supply Current Minimum External Components Micro-Power Shutdown Available in Space-Saving 16-Bump DSBGA Package APPLICATIONS * * * * Mobile Phones PDAs Notebook Electronic Devices MP3 Players The LM48557 features high power supply rejection ratio (PSRR), 80dB at 217Hz, allowing the device to operate in noisy environments without additional power supply conditioning. Flexible power supply requirements allow operation from 2.7V to 4.5V. The LM48557 features an active low reset input that reverts the device to its default state. Additionally, the LM48557 features a 36-step I2C volume control and mute function. The low power Shutdown mode reduces supply current consumption to 0.01A. The LM48557's superior click and pop suppression eliminates audible transients on power-up/down and during shutdown. The LM48557 is available in an ultra-small 16-bump DSBGA package (1.965mm x 1.965mm). KEY APPLICATIONS * Output Voltage at VDD = 4.2V - RL = 1F +22, THD+N 1%: 5.8 VRMS (Typ) 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Boomer is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009-2013, Texas Instruments Incorporated LM48557 SNAS486D - JULY 2009 - REVISED MAY 2013 www.ti.com Typical Application +2.7V to +4.5V CS2 CS1 SVDD PVDD CIN OUTIN+ VOLUME CONTROL AUDIO INPUT IN- OUT+ CIN VCM +1.7V to +4.5V 2 I CVDD SDA SCL RESET I2C INTERFACE CHARGE PUMP SGND C1P C1N C2 CPVSS PGND C1 Figure 1. Typical Audio Amplifier Application Circuit Connection Diagram 2 IN- IN+ I CVDD PVDD 4 IN- IN+ I CVDD PVDD 3 VCM RESET SDA C1P 3 VCM RESET SDA C1P 2 SGND OUT+ SCL PGND 2 SGND OUT+ SCL PGND 1 VDD OUT- CPVSS C1N 1 VDD OUT- CPVSS C1N A B C D A B C D Figure 2. YZR Package - Top View See Package Number YZR001611A 2 2 4 Figure 3. YPD Package - Top View See Package Number YPD001611A Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 LM48557 www.ti.com SNAS486D - JULY 2009 - REVISED MAY 2013 Table 1. Bump Descriptions Bump Name A1 SVDD Signal Power Supply Description A2 SGND Signal Ground A3 VCM A4 IN- B1 OUT- Amplifier Inverting output B2 OUT+ Amplifier Non-Inverting Output B3 RESET Common Mode Sense Input Amplifier Inverting input Active Low Reset Input. Connect to VDD for normal operation. Toggle between VDD and GND to reset the device. B4 IN+ C1 CPVSS Charge Pump Output C2 SCL I2C Serial Clock Input SDA I2C Serial Data Input C3 2 C4 I CVDD D1 C1N D2 PGND Amplifier Non-Inverting Input I2C Supply Voltage Charge Pump Flying Capacitor Negative Terminal Power Ground D3 C1P Charge Pump Flying Capacitor Positive Terminal D4 PVDD Power Supply These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage (1) 5.25V -65C to +150C Storage Temperature -0.3V to VDD +0.3V Input Voltage Power Dissipation (4) Internally Limited ESD Rating-Human Body Model (5) 2kV ESD Rating-Machine Model (6) 150V Junction Temperature Thermal Resistance 150C JA (typ) - (YZR001611A) 63C/W Soldering Information: See AN-1112 "Micro SMD Wafer Level Chip Scale Package." (1) (2) (3) (4) (5) (6) "Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Operating Ratings is not implied. The Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables list specified specifications under the listed Operating Ratings except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / JA or the number given in Absolute Maximum Ratings, whichever is lower. Human body model, applicable std. JESD22-A114C. Machine model, applicable std. JESD22-A115-A. Operating Ratings Temperature Range (TMIN TA TMAX) Supply Voltage -40C TA +85C PVDD and SVDD I2CVDD 2.7V VDD 4.5V 1.7V I2CVDD 4.5V Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 3 LM48557 SNAS486D - JULY 2009 - REVISED MAY 2013 www.ti.com Electrical Characteristics VDD = 4.2V (1) (2) The following specifications apply for AV = 6dB, RL = 1F + 22, C1 = 2.2F, C2 = 2.2F, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM48557 Min (3) Typ (4) Max (3) Units VDD Supply Voltage Range 2.7 4.5 I2CVDD I2C Supply Voltage Range 1.7 4.5 V IDD Quiescent Power Supply Current VIN = 0V, RL = 5 8 mA ISD Shutdown Current 0.01 1 A |VOS| Differential Output Offset Voltage VIH Logic High Input Threshold RESET, VDD = 2.7V to 4.5V VIL Logic Low Input Threshold RESET, VDD = 2.7V to 4.5V AV Gain Shutdown Enabled V VIN = 0V, AV = 0dB 3 12 mV VIN = 0V, AV = 48dB 40 160 mV 1.4 Minimum Gain Setting Volume Control = 000001 -25.5 Maximum Gain Setting Volume Control = 111111 47 AV(MUTE) Mute Attenuation RIN Input Resistance Volume Control = 000000 1 VIN Common Mode Input Voltage Range -1 V 0.4 V -25 -24.5 dB 48 49 dB -90 dB 3 M 1 VP-P RL = 1F + 22, THD+N = 1% 5.5 5.8 15.6 16.4 VP-P 4.0 VRMS f = 1kHz 5.6 VRMS f = 5kHz 2.9 VRMS VO = 4VRMS, f = 1kHz, AV = 48dB 0.05 % f = 1kHz VO Output Voltage f = 5kHz VRMS RL = 2.2F + 10, THD+N = 1% THD+N Total Harmonic Distortion + Noise VDD = 4.2V + 200mVP-P (sine), Inputs AC GND, CIN = 0.1F, AV = 0dB PSRR Power Supply Rejection Ratio (Figure 4) fRIPPLE = 217Hz 80 dB fRIPPLE = 1kHz 80 dB VDD = 4.2V + 200mVP-P (sine), Inputs AC GND, CIN = 0.1F, AV = 48dB f = 1kHz 15 f = 5kHZ 40 dB 40 dB 36 dB 37 dB VCM = 200mVP-P (sine), CIN = 0.1F, AV = 48dB CMRR Common Mode Rejection Ratio (Figure 5) fRIPPLE = 500Hz 16 fRIPPLE = 1kHz fSW Charge Pump Switching Frequency SNR Signal To Noise Ratio OS (1) (2) (3) (4) 4 Output Noise 230 300 VOUT = 5VRMS, f = 1kHz, AV = 48dB 74 AV = 0dB, A-Weighted Filter 20 AV = 48dB, A-weighted Filter 1 370 kHz 30 V dB mV "Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Operating Ratings is not implied. The Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables list specified specifications under the listed Operating Ratings except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Datasheet min/max specification limits are specified by test or statistical analysis. Typical values represent most likely parametric norms at TA = +25C, and at theOperation Rating at the time of product characterization and are not ensured. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 LM48557 www.ti.com SNAS486D - JULY 2009 - REVISED MAY 2013 Electrical Characteristics VDD = 4.2V(1)(2) (continued) The following specifications apply for AV = 6dB, RL = 1F + 22, C1 = 2.2F, C2 = 2.2F, f = 1kHz, unless otherwise specified. Limits apply for TA = 25C. Symbol TWU Parameter Wake Up Time Conditions From shutdown LM48557 Min (3) Typ (4) Max (3) Units 5 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 ms 5 LM48557 SNAS486D - JULY 2009 - REVISED MAY 2013 www.ti.com I2C Interface Characteristics 1.7V I2CVDD 4.5V (1) (2) The following specifications apply for RPU = 1k to I2CVDD, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Min (3) Typ (4) Logic Input High Threshold SDA, SCL VIL Logic Input Low Threshold SDA, SCL VOL Logic Output Low Threshold SDA, ISDA = 3.6mA SDA, SCL, I CVDD = 4.5V SCL Frequency (1) (2) (3) (4) Units V 2 Logic Output High Current Max (3) 0.7 x I2CVDD VIH IOH LM48557 Conditions 0.3 x I2CVDD V 0.35 V 2 A 400 kHz 6 SDA Setup Time 100 5 SDA Stable Time 1 Start Condition Time 100 ns 7 Stop Condition Time 100 ns 0 ns 250 900 ns "Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Operating Ratings is not implied. The Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables list specified specifications under the listed Operating Ratings except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Datasheet min/max specification limits are specified by test or statistical analysis. Typical values represent most likely parametric norms at TA = +25C, and at theOperation Rating at the time of product characterization and are not ensured. 200 mVp-p AUDIO ANALYZER VDD + VDD - IN+ CIN ZL DUT INVCM Figure 4. PSRR Test Circuit VDD AUDIO ANALYZER - + VDD CIN IN+ IN200 mVp-p DUT ZL VCM Figure 5. CMRR Test Circuit 6 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 LM48557 www.ti.com SNAS486D - JULY 2009 - REVISED MAY 2013 Typical Performance Characteristics THD+N vs Frequency VDD = 4.2V, ZL = 1F + 22 AV = 48dB 10 10 1 1 THD + N (%) THD + N (%) THD+N vs Frequency VDD = 3.6V, ZL = 1F + 22 AV = 48dB, VO = 2.5V 0.1 VO = 3VRMS VO = 4VRMS 0.1 0.01 20 100 200 500 1k 2k 0.01 20 5k 10k 20k 100 200 FREQUENCY (Hz) 5k 10k 20k Figure 6. Figure 7. THD+N vs Output Voltage ZL = 1F + 22, AV = 0dB Output Voltage vs Frequency VDD = 4.2V, ZL = 1F + 22 THD+N = 1% 8 1 OUTPUT VOLTAGE (VRMS) 10 THD + N (%) 2k FREQUENCY (Hz) 100 VDD = 4.2V VDD = 3.6V 0.1 0.01 0.001 10m 20m 100m 200m 1 2 5 6 4 2 0 20 10 50 100 200 500 1k OUTPUT VOLTAGE (VRMS) 2k 5k 10k 20k FREQUENCY (Hz) Figure 8. Figure 9. Power Consumption vs Output Voltage VDD = 3.6V, ZL = 1F + 22 Power Consumption vs Output Voltage VDD = 4.2V, ZL = 1F + 22 1400 1000 f = 10kHz POWER CONSUMPTION (mW) POWER CONSUMPTION (mW) 500 1k 800 600 400 f = 1kHz 200 1200 f = 10kHz 1000 800 600 f = 1kHz 400 200 0 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) Figure 10. Figure 11. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 7 LM48557 SNAS486D - JULY 2009 - REVISED MAY 2013 www.ti.com Typical Performance Characteristics (continued) CMRR vs Frequency VDD = 4.2V, VRIPPLE = 200mVP-P, AV = 48dB PSRR vs Frequency VDD = 4.2V, VRIPPLE = 200mVP-P 0 +0 -10 -20 AV = 48 dB -40 PSRR (dB) CMRR (dB) -20 -30 -40 AV = 0 dB -60 -80 -50 -100 -60 20 50 100 200 500 1k 2k 5k 10k 20k -120 20 50 100 200 500 1k 2k FREQUENCY (Hz) Figure 12. Figure 13. Output Voltage vs Supply Voltage ZL = 1F + 22, THD+N = 1% Supply Current vs Supply Voltage No Load OUTPUT VOLTAGE (VRMS) 6 6 5.8 f = 1 kHz 5 SUPPLY CURRENT (mA) 7 5k 10k 20k FREQUENCY (Hz) f = 10 kHz 4 3 2 5.6 5.4 5.2 5 4.8 4.6 4.4 1 4.2 0 2.5 3 3.5 4 4.5 4 2.5 5 3 SUPPLY VOLTAGE (V) 3.5 4 4.5 5 SUPPLY VOLTAGE (V) Figure 14. Figure 15. Charge Pump Output Voltage vs Load Current VDD = 4.2V CHARGE PUMP OUTPUT VOLTAGE (V) 0 -1 -2 -3 -4 -5 0 40 80 120 160 200 CHARGE PUMP LOAD CURRENT (mA) Figure 16. 8 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 LM48557 www.ti.com SNAS486D - JULY 2009 - REVISED MAY 2013 APPLICATION INFORMATION I2C COMPATIBLE INTERFACE The LM48557 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM48557 and the master can communicate at clock rates up to 400kHz. Figure 17 shows the I2C interface timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48557 is a transmit/receive slaveonly device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition (Figure 18). Each data word, device address and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 19). The LM48557 device address is 11011110. I2C BUS FORMAT The I2C bus format is shown in Figure 19. The START signal, the transition of SDA from HIGH to LOW while SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus. The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. Set R/W = 0; the LM48557 is a WRITE-ONLY device and will not respond to R/W = 1. In other words, the LM48557 will not issue an ACK when R/W = 1. Each address bit is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the LM48557. If the LM48557 receives the correct address, the device pulls the SDA line low, generating an acknowledge bit (ACK). Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable while SCL is HIGH. The LM48557 has two registers, Mode Control and Volume Control. The register address and register data are combined into a single byte, the most significant bit (MSB) indicates which register is being addressed. To address the Mode Control register, set the MSB of the data byte to 0, followed by seven bits of register data. To address the Volume Control register, set the MSB of the data byte to 1, followed by seven bits of register data. After the 8-bit register data word is sent, the LM48557 sends another ACK bit. The LM48557 supports single and multi-byte write operations, any number of data bytes can be transmitted to the device between START and STOP conditions. Following the acknowledgement of the last register data word, the master issues a STOP bit, allowing SDA to go high while SCL is high. SDA 10 8 7 6 1 8 2 7 SCL 5 1 3 4 9 Figure 17. I2C Timing Diagram SDA SCL S P START condition STOP condition Figure 18. Start and Stop Diagram Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 9 LM48557 SNAS486D - JULY 2009 - REVISED MAY 2013 www.ti.com SCL START SDA MSB DEVICE ADDRESS LSB R/W ACK MSB REGISTER DATA LSB ACK STOP Figure 19. Example Write Sequence Table 2. Device Address Device Address B7 B6 B5 B4 B3 B2 B1 B0 R/W 1 1 0 1 1 1 1 0 B2 B1 B0 Table 3. Control Registers Register Name B7 B6 Mode Control 0 0 0 0 0 0 MUTE SHDN Volume Control 1 0 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 B5 B4 B3 Table 4. Mode Control Registers (1) BIT NAME B0 SHDN B1 MUTE B2 VALUE DESCRIPTION DEFAULT SETTING 0 Shutdown mode 1 Normal operation 0 Normal operation 1 Device mute, AV = -90dB. RESERVED (1) X Unused, Set to 0 0 B3 RESERVED (1) X Unused, Set to 0 0 B4 TESTMODE 0 Set B4 to 0. B4 = 1 enables TESTMODE. See TEST MODE. 0 B5 RESERVED (1) X Unused, Set to 0 0 B6 RESERVED (1) X Unused, Set to 0 0 B7 REGISTER ADDRESS 0 Set to 0 to access Mode Control register 0 0 0 RESERVED bits are Don't Cares and are ignored by the device. The state of the RESERVED bits does not affect device operation. Table 5. Volume Control Registers BIT NAME VALUE B0:B5 VOL0:VOL5 See Table 6 B6 B7 (1) RESERVED (1) REGISTER ADDRESS DESCRIPTION DEFAULT SETTING Controls amplifier gain/attenuation 0 X Unused, Set to 0 0 1 Set to 1 to access Volume Control register 1 RESERVED bits are Don't Cares and are ignored by the device. The state of the RESERVED bits does not affect device operation. SINGLE AND MULTI-BYTE WRITE OPERATION The LM48557 supports both single-byte and multi-byte write operations. A single-byte write operation begins with the master device transmitting a START condition followed by the device address (Figure 20). After receiving the correct device address, the LM48557 generates an ACK bit. The master device transmits the register data byte, after which the LM48557 generates and ACK bit. Following the ACK, the master issues a STOP condition, completing the singly-byte data transfer. 10 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 LM48557 www.ti.com SNAS486D - JULY 2009 - REVISED MAY 2013 A multi-byte write operation is similar to a single-byte operation, the master device issues a START condition and device address, and the LM48557 responds with an ACK (Figure 21). The master device then transmits the first data byte. Following the LM48557's ACK, the master device does not issue a STOP condition, transmitting a second data byte instead. The LM48557 responds with an ACK bit. The master device can continue to issue data bytes, and the LM48557 will respond with an ACK, until a STOP condition is issued. Once a STOP condition is issued, the LM48557 ignores the I2C bus until the master issues the LM48557's device address. START MSB DEVICE ADDRESS LSB R/W ACK MSB REGISTER DATA LSB ACK STOP Figure 20. Single-Byte Write Example START MSB DEVICE ADDRESS LSB R/W ACK MSB FIRST REGISTER BYTE LSB ACK MSB LSB SUCCESSIVE REGISTER BYTES ACK MSB LSB ACK STOP LAST REGISTER BYTE Figure 21. Multi-Byte Write Example GENERAL AMPLIFIER FUNCTION The LM48557 is a fully differential ceramic speaker driver that utilizes Ti's inverting charge pump technology to deliver over 5.8VRMS to a 1F ceramic speaker while operating from a single 4.2V supply. The low noise, inverting charge pump generates a negative supply voltage (CPVSS) from the positive supply voltage (PVDD). The LM48557 takes advantage of the increased head room created by the charge pump and the bridge-tied load (BTL) architecture, delivering significantly more voltage than a single-ended, single-supply amplifier to the speaker. Table 6. Volume Control Table VOLUME STEP VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 GAIN (dB) 1 (MUTE) 0 0 0 0 0 0 -90 2 0 0 0 0 0 1 -25 3 0 0 0 0 1 0 -22 4 0 0 0 0 1 1 -19 5 0 0 0 1 0 0 -16 6 0 0 0 1 0 1 -13 7 0 0 0 1 1 0 -10 8 0 0 0 1 1 1 -8 9 0 0 1 0 0 0 -6 10 0 0 1 0 0 1 -4 11 0 0 1 0 1 0 -2 12 0 0 1 0 1 1 0 13 0 0 1 1 0 0 2 14 0 0 1 1 0 1 4 15 0 0 1 1 1 0 6 16 0 0 1 1 1 1 8 17 0 1 0 0 0 0 10 18 0 1 0 0 0 1 12 19 0 1 0 0 1 0 14 20 0 1 0 0 1 1 16 21 0 1 0 1 0 0 18 22 0 1 0 1 0 1 20 23 0 1 0 1 1 0 22 24 0 1 0 1 1 1 24 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 11 LM48557 SNAS486D - JULY 2009 - REVISED MAY 2013 www.ti.com Table 6. Volume Control Table (continued) VOLUME STEP VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 GAIN (dB) 25 0 1 1 0 0 0 26 26 0 1 1 0 0 1 28 27 0 1 1 0 1 0 30 28 0 1 1 0 1 1 32 29 0 1 1 1 0 0 34 30 0 1 1 1 0 1 36 31 0 1 1 1 1 0 38 32 0 1 1 1 1 1 40 Do Not Use Volume Steps 33-60 See Table 7 61 1 1 1 1 0 0 42 62 1 1 1 1 0 1 44 63 1 1 1 1 1 0 46 64 1 1 1 1 1 1 48 Table 7. Unused Volume Steps 12 VOLUME STEP VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 GAIN (dB) 33 1 0 0 0 0 0 -90 34 1 0 0 0 0 1 -25 35 1 0 0 0 1 0 -22 36 1 0 0 0 1 1 -19 37 1 0 0 1 0 0 -16 38 1 0 0 1 0 1 -13 39 1 0 0 1 1 0 -10 40 1 0 0 1 1 1 -8 41 1 0 1 0 0 0 -6 42 1 0 1 0 0 1 -4 43 1 0 1 0 1 0 0 44 1 0 1 0 1 1 4 45 1 0 1 1 0 0 8 46 1 0 1 1 0 1 12 47 1 0 1 1 1 0 14 48 1 0 1 1 1 1 16 49 1 1 0 0 0 0 18 50 1 1 0 0 0 1 20 51 1 1 0 0 1 0 22 52 1 1 0 0 1 1 24 53 1 1 0 1 0 0 26 54 1 1 0 1 0 1 28 55 1 1 0 1 1 0 30 56 1 1 0 1 1 1 32 57 1 1 1 0 0 0 34 58 1 1 1 0 0 1 36 59 1 1 1 0 1 0 38 60 1 1 1 0 1 1 40 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 LM48557 www.ti.com SNAS486D - JULY 2009 - REVISED MAY 2013 VOLUME CONTROL The LM48557 has a 64 step volume control, but only 36 steps are recommended for use. Use steps 1 through 32 and steps 61 through 64 to set the gain of the device. Accessing steps 33 through 60 results in the repeated gain conditions shown in Table 7. Steps 33 through 60 are not tested and should not be used. SHUTDOWN FUNCTION The LM48557 features a low-power shutdown mode that disables the device lowers the quiescent current to 0.01A. Set bit B0 (SHDN) of the Mode Control register to 0 to disable the amplifier and charge pump. Set SHDN to 1 for normal operation. Shutdown mode does not clear the I2C register. When re-enabled, the device returns to its previous volume setting. To clear the I2C register, either remove power from the device, or toggle RESET (see RESET section). RESET The LM48557 features an active low reset input. Driving RESET low clears the I2C register. Volume control is set to 000000 (-90dB) and SHDN is set to 0, disabling the device. While RESET is low, the LM48557 ignores any I2C data. After the device is reset, and RESET is driven high, the LM48557 remains in shutdown mode with the volume set to -90dB. Re-enable the device by writing to the I2C register. MUTE The LM48557 features a mute mode. Set bit B1 (MUTE) of the Mode Control register to 1 to mute the device. In mute mode, the gain is set to -90dB, equivalent to the volume step 1. Set MUTE = 0 to unmute the device. Once unmuted, the device returns to its previous volume step. TEST MODE If enabled, TESTMODE does not affect device performance under normal operating conditions. Operating above the recommended supply voltage range with TESTMODE enabled can result in damage to the device. PROPER SELECTION OF EXTERNAL COMPONENTS Power Supply Bypassing/Filtering Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to the device as possible. Place a 1F ceramic capacitor from VDD to GND. Additional bulk capacitance may be added as required. Charge Pump Capacitor Selection Use low ESR ceramic capacitors (less than 100m) for optimum performance. Charge Pump Flying Capacitor (C1) The flying capacitor (C1) affects the load regulation and output impedance of the charge pump. A C1 value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C1 improves load regulation and lowers charge pump output impedance to an extent. Above 2.2F, the RDS(ON) of the charge pump switches and the ESR of C1 and C2 dominate the output impedance. A lower value capacitor can be used in systems where low maximum output power requirements. Charge Pump Hold Capacitor (C2) The value and ESR of the hold capacitor (C2) directly affects the ripple on CPVSS. Increasing the value of C2 reduces output ripple. Decreasing the ESR of C2 reduces both output ripple and charge pump output impedance. A lower value capacitor can be used in systems where low maximum output power requirements. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 13 LM48557 SNAS486D - JULY 2009 - REVISED MAY 2013 www.ti.com Input Capacitor Selection Input capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of the audio source and the bias voltage of the LM48557. The input capacitors create a high-pass filter with the input resistors RIN. The -3dB point of the high pass filter is found using the equation below. f = 1 / 2RINCIN (Hz) (1) Where the value of RIN is given in the Electrical Characteristics Table. High pass filtering the audio signal helps protect the speakers. When the LM48557 is using a single-ended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance matching and improved CMRR and PSRR. COMMON MODE SENSE The LM48557 features a common mode sense pin (VCM, pin A3) that includes additional common mode cancelling circuitry that improves the CMRR. When the volume control is set at a high gain step such as 48dB, any mismatch in the input capacitors would degrade CMRR performance significantly. With the VCM pin connected to the ground of the input source, it takes the input capacitor mismatches out of the equation and therefore improves the CMRR. Another advantage with this feature is that only one input capacitor is needed in the single-ended configuration as opposed to two well matched capacitors. See next section for details of different configurations of the LM48857. SINGLE-ENDED INPUT CONFIGURATION Ground-Referenced Audio Source The LM48557 input stage is compatible with ground-referenced input sources, such as CODECs with an integrated headphone amplifier. Connect either input, IN+ or IN- to the CODEC output, and connect the unused input and VCM to the CODEC output ground (Figure 22). An input coupling capacitor in series with the source and device input is recommended to block the CODEC output offset voltage, minimizing click and pop and zipper noise during volume transitions. IN+ IN- IN- IN+ VCM VCM LM48557 Non-Inverting Configuration LM48557 Inverting Configuration Figure 22. Single-Ended Input Configuration with a Ground-Referenced Source NON-GROUND REFERENCED AUDIO SOURCE Stereo-to-Mono Conversion The LM48557 can convert a single-ended stereo signal to a mono BTL signal (Figure 23). Connect the left and right CODEC outputs in parallel through two equal value resistors to either IN+ or IN-, and connect the unused input and VCM to the CODEC ground. Select the value of the resistors based on the desired frequency response created by the combination of the input resistor and the input coupling capacitor. 14 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 LM48557 www.ti.com SNAS486D - JULY 2009 - REVISED MAY 2013 LEFT LEFT IN+ RIGHT IN- RIGHT IN- IN+ VCM VCM LM48557 LM48557 Non-Inverting Configuration Inverting Configuration Figure 23. Single-Ended Stereo-to-Mono BTL Conversion PCB Layout Guidelines Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due to trace resistance between the LM48557 and the load results in decreased output power and efficiency. Trace resistance between the power supply and ground has the same effect as a poorly regulated supply, increased ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs to minimize losses due to trace resistance, as well as route heat away from the device. Proper grounding improves audio performance, minimizes crosstalk between channels and prevents switching noise from interfering with the audio signal. Use of power and ground planes is recommended. Place all digital components and route digital signal traces as far as possible from analog components and traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines must cross either over or under each other, ensure that they cross in a perpendicular fashion. Table 8. LM48557TL Demoboard Bill of Materials Designator Quantity U1 1 LM48557TL Differential, Mono, Ceramic Speaker Driver with I2C Volume Control, and Reset C1, C2, C5, C6, C7 Description 5 CAP CERAMIC 2.2F 10V X5R 10% 0603 C3, C4 2 CAP .1F 16V CERAMIC X7R 10% 1206 C8 1 CAP TANT LOESR 10F 16V 10% SMD J2 1 CONN SOCKET PCB VERT 16POS .1" 12 CONN HEADER VERT .100 2POS 30Au JU1, JU2, JU3, JU4, VCM, VDD, GND, I2CVDD, IN+, IN-, OUT+, OUTJU5 1 CONN HEADER VERT .100 3POS 30Au R1, R2 2 RES 5.1K OHM 1/10W 5% 0603 SMD R3 1 RES 20K OHM 1/10W 5% 0603 SMD 4 Jumper Shunt w/handle, 30uin gold plated, 0.100" pitch JU1_SH, JU2_SH, JU3_SH, JU5_SH Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 15 LM48557 SNAS486D - JULY 2009 - REVISED MAY 2013 www.ti.com PC Board Layout 16 Figure 24. Silk Screen Figure 25. Top Layer Figure 26. Layer 2 Figure 27. Layer 3 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 LM48557 www.ti.com SNAS486D - JULY 2009 - REVISED MAY 2013 Figure 28. Bottom Layer Figure 29. Bottom Silkscreen Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 17 LM48557 SNAS486D - JULY 2009 - REVISED MAY 2013 www.ti.com Demo Board Schematic Figure 30. LM48557 Demo Board Schematic 18 Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 LM48557 www.ti.com SNAS486D - JULY 2009 - REVISED MAY 2013 Revision History Rev Date Description 1.0 07/08/09 Initial released. 1.01 07/15/09 Deleted the "Tru-GND..." trademark on the cover page. 1.02 08/05/09 Text edits. 1.03 08/06/09 Fixed a typo error. 1.04 01/11/10 Added the LM48557UR package drawing, top markings, and the marketing outline. D 02/05/2013 Changed layout of National Data Sheet to TI format. Submit Documentation Feedback Copyright (c) 2009-2013, Texas Instruments Incorporated Product Folder Links: LM48557 19 PACKAGE OPTION ADDENDUM www.ti.com 2-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LM48557TL/NOPB ACTIVE DSBGA YZR 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM GM2 LM48557TLX/NOPB ACTIVE DSBGA YZR 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM GM2 LM48557UR/NOPB ACTIVE DSBGA YPD 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM GN5 LM48557URX/NOPB ACTIVE DSBGA YPD 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM GN5 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 2-May-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ LM48557TL/NOPB DSBGA LM48557TLX/NOPB LM48557UR/NOPB LM48557URX/NOPB Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant YZR 16 250 178.0 8.4 2.08 2.08 0.76 4.0 8.0 Q1 DSBGA YZR 16 3000 178.0 8.4 2.08 2.08 0.76 4.0 8.0 Q1 DSBGA YPD 16 250 178.0 8.4 2.11 2.11 0.56 4.0 8.0 Q1 DSBGA YPD 16 3000 178.0 8.4 2.11 2.11 0.56 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM48557TL/NOPB DSBGA YZR 16 250 210.0 185.0 35.0 LM48557TLX/NOPB DSBGA YZR 16 3000 210.0 185.0 35.0 LM48557UR/NOPB DSBGA YPD 16 250 210.0 185.0 35.0 LM48557URX/NOPB DSBGA YPD 16 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YPD0016 D 0.3500.045 E URA16XXX (Rev A) D: Max = 1.99 mm, Min = 1.93 mm E: Max = 1.99 mm, Min = 1.93 mm 4215146/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 MECHANICAL DATA YZR0016xxx D 0.6000.075 E TLA16XXX (Rev C) D: Max = 1.99 mm, Min = 1.93 mm E: Max = 1.99 mm, Min = 1.93 mm 4215051/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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