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OP275*
Dual Bipolar/JFET, Audio
Operational Amplier
FEATURES
Excellent Sonic Characteristics
Low Noise: 6 nV/Hz
Low Distortion: 0.0006%
High Slew Rate: 22 V/s
Wide Bandwidth: 9 MHz
Low Supply Current: 5 mA
Low Offset Voltage: 1 mV
Low Offset Current: 2 nA
Unity Gain Stable
SOIC-8 Package
PDIP-8 Package
APPLICATIONS
High Performance Audio
Active Filters
Fast Ampliers
Integrators
PIN CONNECTIONS
GENERAL DESCRIPTION
The OP275 is the rst amplier to feature the Butler Amplier
front end. This new front end design combines both bipolar
and JFET transistors to attain ampliers with the accuracy and
low noise performance of bipolar transistors, and the speed and
sound quality of JFETs. Total Harmonic Distortion plus Noise
equals that of previous audio ampliers, but at much lower
supply currents.
A very low l/f corner of below 6 Hz maintains a at noise density
response. Whether noise is measured at either 30 Hz or 1 kHz,
it is only 6 nV
Hz. The JFET portion of the input stage gives
the OP275 its high slew rates to keep distortion low, even when
large output swings are required, and the 22 V/µs slew rate of the
OP275 is the fastest of any standard audio amplier. Best of all,
this low noise and high speed are accomplished using less than
5 mA of supply current, lower than any standard audio amplier.
Improved dc performance is also provided with bias and offset
currents greatly reduced over purely bipolar designs. Input offset
voltage is guaranteed at 1 mV and is typically less than 200 µV.
This allows the OP275 to be used in many dc-coupled or sum-
ming applications without the need for special selections or the
added noise of additional offset adjustment circuitry.
The output is capable of driving 600 loads to 10 V rms while
maintaining low distortion. THD + Noise at 3 V rms is a low
0.0006%.
The OP275 is specied over the extended industrial (–40°C to
+85°C) temperature range. OP275s are available in both plas-
tic DIP and SOIC-8 packages. SOIC-8 packages are available
in 2500-piece reels. Many audio ampliers are not offered
in SOIC-8 surface-mount packages for a variety of reasons;
however, the OP275 was designed so that it would offer full
performance in surface-mount packaging.
8-Lead Narrow-Body SOIC
(S Sufx)
OP275
OUT A
–IN A
+IN A
V–
OUT B
–IN B
+IN B
V+
1
2
3
45
6
7
8
8-Lead PDIP
(P Sufx)
1
2
3
4
8
7
6
5
OP275
OUT B
–IN B
+IN B
V+OUT A
–IN A
+IN A
V–
*Protected by U.S. Patent No. 5,101,126.
REV. C
–2–
OP275–SPECIFICATIONS
OP275
–3–
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Unit
AUDIO PERFORMANCE
THD + Noise VIN = 3 V rms,
RL = 2 k, f = 1 kHz 0.006 %
Voltage Noise Density en f = 30 Hz 7 nV
Hz
f = 1 kHz 6 nV
Hz
Current Noise Density in f = 1 kHz 1.5 pA
Hz
Headroom THD + Noise 0.01%,
RL = 2 k, VS = ±18 V >12.9 dBu
INPUT CHARACTERISTICS
Offset Voltage VOS 1 mV
–40°C TA +85°C 1.25 mV
Input Bias Current IB VCM = 0 V 100 350 nA
VCM = 0 V, –40°C TA +85°C 100 400 nA
Input Offset Current IOS VCM = 0 V 2 50 nA
VCM = 0 V, –40°C TA +85°C 2 100 nA
Input Voltage Range VCM –10.5 +10.5 V
Common-Mode Rejection Ratio CMRR VCM = ±10.5 V,
–40°C TA +85°C 80 106 dB
Large Signal Voltage Gain AVO RL = 2 k 250 V/mV
RL = 2 k, –40°C TA +85°C 175 V/mV
RL = 600 200 V/mV
Offset Voltage Drift VOS/T 2 µV/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing VO RL = 2 k –13.5 ±13.9 +13.5 V
RL = 2 k, –40°C TA +85°C –13 ±13.9 +13 V
RL = 600 , VS = ±18 V +14, –16 V
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 85 111 dB
VS = ±4.5 V to ±18 V,
–40°C TA +85°C 80 dB
Supply Current ISY VS = ±4.5 V to ±18 V, VO = 0 V,
RL = , –40°C TA +85°C 4 5 mA
VS = ±22 V, VO = 0 V, RL = ,
–40°C TA +85°C 5.5 mA
Supply Voltage Range VS ±4.5 ±22 V
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 k 15 22 V/µs
Full-Power Bandwidth BWP kHz
Gain Bandwidth Product GBP 9 MHz
Phase Margin Øm 62 Degrees
Overshoot Factor VIN = 100 mV, AV = +1,
RL = 600 , CL = 100 pF 10 %
Specications subject to change without notice.
(@ VS = 15.0 V, TA = 25C, unless otherwise noted.)
REV. C REV. C
–2–
OP275–SPECIFICATIONS
OP275
–3–
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . ±7.5 V
Output Short-Circuit Duration to GND3 . . . . . . . . . . Indenite
Storage Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP275G . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . . .300°C
Package Type JA4 JC Unit
8-Lead Plastic DIP (P) 103 43 °C/W
8-Lead SOIC (S) 158 43 °C/W
NOTES
1Absolute maximum ratings apply to packaged parts, unless otherwise noted.
2For supply voltages greater than ±22 V, the absolute maximum input voltage is equal
to the supply voltage.
3Shorts to either supply may destroy the device. See data sheet for full details.
4JA is specied for the worst-case conditions, i.e., JA is specied for device in socket
for PDIP packages; JA is specied for device soldered in circuit board for SOIC
packages.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
OP275GP –40°C to +85°C 8-Lead PDIP N-8
OP275GS –40°C to +85°C 8-Lead SOIC R-8
OP275GS-REEL –40°C to +85°C 8-Lead SOIC R-8
OP275GS-REEL7 –40°C to +85°C 8-Lead SOIC R-8
OP275GSZ* –40°C to +85°C 8-Lead SOIC R-8
OP275GSZ-REEL* –40°C to +85°C 8-Lead SOIC R-8
OP275GSZ-REEL7* –40°C to +85°C 8-Lead SOIC R-8
*Z = Pb-free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the OP275 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. C REV. C
–4–
OP275–Typical Performance Characteristics OP275
–5–
SUPPLY VOLTAGE – V
OUTPUT VOLTAGE SWING – V
25
20
–25 0525
10 15 20
–5
–10
–15
–20
15
5
10
0
T
A
= 25C
R
L
= 2k
+VOM
–VOM
TPC 1. Output Voltage Swing
vs. Supply Voltage
FREQUENCY – Hz
1M 10M
10k 100k
PHASE – Degrees
135
90
45
0
–45
–90
60
50
–20
40
30
20
10
0
–10
GAIN – dB
V
S
=
15V
T
A
= 25
C
MARKER 15 309.059Hz
MAG (A/H) 60.115dB
MARKER 15 309.058Hz
PHASE (A/R) 90.606Deg
TPC 4. Open-Loop Gain,
Phase vs. Frequency
FREQUENCY – Hz
120
100
0
100 1k 10M10k 100k 1M
80
60
40
20
V
S
= 15V
T
A
= 25C
COMMON-MODE REJECTION – dB
TPC 7. Common-Mode
Rejection vs. Frequency
TEMPERATURE – C
OPEN-LOOP GAIN – V/mV
1500
0
–50 –25 100
0 25 50 75
1250
1000
750
500
250
V
S
=
15V
V
O
=
15V
+GAIN
R
L
= 2k
–GAIN
R
L
= 2k
+GAIN
R
L
= 600
–GAIN
R
L
= 600
TPC 2. Open-Loop Gain vs.
Temperature
FREQUENCY – Hz
50
CLOSED-LOOP GAIN – dB
40
–30
1k 10k 100M
100k 1M 10M
30
20
10
0
–10
–20
V
S
=
15V
T
A
= 25
C
A
VCL
= +100
A
VCL
= +10
A
VCL
= +1
TPC 5. Closed-Loop Gain vs.
Frequency
FREQUENCY – Hz
120
100
010 100 1M
1k 10k 100k
80
60
40
20
POWER SUPPLY REJECTION – dB
VS =
15V
TA =
25C
+PSRR
–PSRR
TPC 8. Power Supply Rejection vs.
Frequency
TPC 3. Closed-Loop Gain and
Phase, AV = +1
FREQUENCY – Hz
60
IMPEDANCE –
50
0
100 1k 10M
10k 100k 1M
40
30
20
10
V
S
= 15V
T
A
= 25C
A
VCL
= +1
A
VCL
= +10
A
VCL
= +100
TPC 6. Closed-Loop Output
Impedance vs. Frequency
FREQUENCY – Hz
100
80
–60
1k 10k 100M
100k 1M 10M
60
40
20
0
–20
–40
0
PHASE – Degrees
45
90
135
180
225
270
V
S
=
15V
R
L
= 2k
T
A
= 25
C
OPEN-LOOP GAIN – dB
GAIN
PHASE Ø
m
= 58
TPC 9. Open-Loop Gain,
Phase vs. Frequency
REV. C REV. C
–4–
OP275–Typical Performance Characteristics OP275
–5–
TEMPERATURE – C
GAIN BANDWIDTH PRODUCT – MHz
11
10
7
–50 –25 100
0 25 50 75
9
8
PHASE MARGIN – Degrees
65
60
40
55
50
GBW
Ø
m
TPC 10. Gain Bandwidth Product,
Phase Margin vs. Temperature
25
20
15
10
5
FREQUENCY – Hz
MAXIMUM OUTPUT SWING – V
30
0
1k 10k 10M
100k 1M
T
A
= 25
C
V
S
=
15V
A
VCL
= +1
R
L
= 2k
TPC 13. Maximum Output
Swing vs. Frequency
TEMPERATURE – C
300
INPUT BIAS CURRENT – nA
0
–50 –25 100
0 25 50 75
250
200
150
100
50
V
S
= ±15V
TPC 16. Input Bias Current vs.
Temperature
LOAD CAPACITANCE – pF
100
OVERSHOOT – %
90
00 100 500
200 300 400
40
30
20
10
80
60
70
50
A
VCL
= +1
NEGATIVE EDGE
A
VCL
= +1
POSITIVE EDGE
V
S
= 15V
R
L
= 2k
V
IN
= 100mV p-p
TPC 11. Small Signal Overshoot vs.
Load Capacitance
SUPPLY VOLTAGE – V
5.0
SUPPLY CURRENT – mA
4.5
3.0 0525
10 15
4.0
3.5
20
T
A
= +25C
T
A
= –40C
T
A
= +85C
TPC 14. Supply Current vs.
Supply Voltage
FREQUENCY – Hz
10 100 100
k
1k
5
4
3
2
1
CURRENT NOISE DENSITY – pA/
Hz
V = 15V
T = 25C
S
A
TPC 17. Current Noise Density
vs. Frequency
16
8
0
100 1k 10
k
2
4
6
10
12
14
LOAD RESISTANCE –
T
A
= 25
C
V
S
=
15V
+VOM
–VOM
MAXIMUM OUTPUT SWING – V
TPC 12. Maximum Output
Voltage vs. Load Resistance
TEMPERATURE – C
ABSOLUTE OUTPUT CURRENT – mA
120
20
–50 –25 100
0 25 50 75
110
70
60
50
30
100
90
80
40
V
S
=
15V
SINK
SOURCE
TPC 15. Short-Circuit Current
vs. Temperature
TCV
OS
– V/C
UNITS
500
400
0
0 1 10
2 3 4 5 6 7 8 9
300
200
100
BASED ON 920 OP AMPS
V
S
=
15V
–40
C to +85
C
TPC 18. TCVOS Distribution
REV. C REV. C
–6–
OP275 OP275
–7–
INPUT OFFSET VOLTAGE – V
UNITS
200
160
0
–500–400 500
–300–200–100 0 100 200 300 400
120
80
40
BASED ON 920 OP AMPS V
S
=
15V
T
A
= 25
C
TPC 19. Input Offset (VOS)
Distribution
DIFFERENTIAL INPUT VOLTAGE – V
40
20
00 1.0
35
30
10
5
25
15
SLEW RATE – V/
s
VS =
15V
RL = 2k
TA = 25
C
0.80.60.40.2
TPC 22. Slew Rate vs. Differential
Input Voltage
10
0%
100
90
200ns
5V
TPC 25. Positive Slew Rate
RL = 2 k , VS = ±15 V, AV = +1
SETTLING TIME – ns
STEP SIZE – V
10
8
–10
–2
–4
–6
–8
6
2
4
0
0 100 900
200 300 400 500 600 700 800
+0.1%
+0.01%
–0.1%
–0.01%
TPC 20. Step Size vs. Settling
Time
TPC 23. Slew Rate vs. Temperature
10
0%
100
90
100ns
50mV
TPC 26. Small Signal Response
RL = 2 k , VS = ±5 V, AV = +1
+SR
–SR
CAPACITIVE LOAD – pF
50
45
SLEW RATE – V/s
20 0 100 500200 300 400
40
35
30
25
T
A
=
25
C
V
S
=
15V
TPC 21. Slew Rate vs. Capacitive
Load
10
0%
100
90
200ns
5V
TPC 24. Negative Slew Rate
RL = 2 k , VS = ±15 V, AV = +1
2.5 kHz
0 Hz
CH A: 80.0 V FS
10.0 V/DIV
MKR: 6.23 nV/ Hz
BW: 15.0 MHzMKR: 1 000 Hz
TPC 27. Voltage Noise Density
vs. Frequency VS = ±15 V
REV. C REV. C
–6–
OP275 OP275
–7–
APPLICATIONS
Circuit Protection
OP275 has been designed with inherent short-circuit protection
to ground. An internal 30
resistor, in series with the output,
limits the output current at room temperature to ISC+ = 40 mA
and ISC– = –90 mA, typically, with ±15 V supplies.
However, shorts to either supply may destroy the device when
excessive voltages or currents are applied. If it is possible for a
user to short an output to a supply for safe operation, the output
current of the OP275 should be design-limited to ±30 mA, as
shown in Figure 1.
Total Harmonic Distortion
Total Harmonic Distortion + Noise (THD + N) of the OP275 is
well below 0.001% with any load down to 600
. However, this is
dependent upon the peak output swing. In Figure 2, the THD +
Noise with 3 V rms output is below 0.001%. In Figure 3, THD +
Noise is below 0.001% for the 10 k
and 2 k
loads but increases
to above 0.1% for the 600
load condition. This is a result of the
output swing capability of the OP275. Notice the results in Figure 4,
showing THD versus VIN (V rms). This gure shows that the THD
+ Noise remains very low until the output reaches 9.5 V rms. This
performance is similar to competitive products.
R
FB
FEEDBAC
K
R
X
332
A1 V
OUT
A1 = 1/2 OP275
–
+
Figure 1. Recommended Output Short-Circuit Protection
RL = 600
, 2k
, 10k
VS =
15V
VIN = 3V rms
AV = +1
0.010
0.001
0.000520 100 1k 10k 20
k
FREQUENCY – Hz
THD + NOISE – %
Figure 2. THD + Noise vs. Frequency vs. RLOAD
1
0.001
0.0001
20 100 1k 10k 20
k
THD + NOISE – %
FREQUENCY – Hz
AV = +1
VS = 18V
VIN = 10V rms
80kHz FILTER
600
2k
10k
0.1
0.010
Figure 3. THD + Noise vs. RLOAD; VIN =10 V rms
V
S
= 18V
R
L
= 600
0.010
0.001
0.0001
0.5 1 10
THD + NOISE – %
OUTPUT SWING – V rms
Figure 4. Headroom, THD + Noise vs. Output
Amplitude (V rms); RLOAD = 600 , VSUP = ±18 V
The output of the OP275 is designed to maintain low harmonic
distortion while driving 600
loads. However, driving 600
loads with very high output swings results in higher distortion if
clipping occurs. A common example of this is in attempting to
drive 10 V rms into any load with ±15 V supplies. Clipping will
occur and distortion will be very high. To attain low harmonic
distortion with large output swings, supply voltages may be
increased. Figure 5 shows the performance of the OP275 driving
600
loads with supply voltages varying from ±18 V to ±20 V.
Notice that with ±18 V supplies the distortion is fairly high, while
with ±20 V supplies it is a very low 0.0007%.
SUPPLY VOLTAGE – V
0.0001
0.001
THD – %
0
17
22
18
19
20
21
0.01
0.1
R
L
= 600
V
OUT
= 10V rms @ 1kHz
Figure 5. THD + Noise vs. Supply Voltage
Noise
The voltage noise density of the OP275 is below 7 nV/
Hz from
30 Hz. This enables low noise designs to have good performance
throughout the full audio range. Figure 6 shows a typical OP275
with a 1/f corner at 2.24 Hz.
10Hz
0Hz
CH A: 80.0
V FS 10.0
V/DIV
MKR: 45.6
V/ Hz
BW: 0.145HzMKR: 2.24Hz
Figure 6. 1/f Noise Corner, VS = ±15 V, AV = 1000
REV. C REV. C
OP275
–8–
OP275
–9–
Noise Testing
For audio applications, the noise density is usually the most
important noise parameter. For characterization, the OP275 is
tested using an Audio Precision, System One. The input signal
to the Audio Precision must be amplied enough to measure it
accurately. For the OP275, the noise is gained by approximately
1020 using the circuit shown in Figure 7. Any readings on the
Audio Precision must then be divided by the gain. In imple-
menting this test xture, good supply bypassing is essential.
A
B
OP275
909
100
OP37
909
100
909
100
OP37
4.42k
490
OUTPUT
Figure 7. Noise Test Fixture
Input Overcurrent Protection
The maximum input differential voltage that can be applied
to the OP275 is determined by a pair of internal Zener diodes
connected across its inputs. They limit the maximum differential
input voltage to ±7.5 V. This is to prevent emitter-base junction
breakdown from occurring in the input stage of the OP275 when
very large differential voltages are applied. However, to preserve
the OP275’s low input noise voltage, internal resistances in series
with the inputs were not used to limit the current in the clamp
diodes. In small signal applications, this is not an issue; however,
in applications where large differential voltages can be inadvert-
ently applied to the device, large transient currents can ow
through these diodes. Although these diodes have been designed
to carry a current of ±5 mA, external resistors as shown in Figure 8
should be used in the event that the OP275’s differential voltage
were to exceed ±7.5 V.
OP275
1.4k
1.4k
–
+
2
3
6
Figure 8. Input Overcurrent Protection
Output Voltage Phase Reversal
Since the OP275’s input stage combines bipolar transistors for
low noise and p-channel JFETs for high speed performance, the
output voltage of the OP275 may exhibit phase reversal if either
of its inputs exceeds its negative common-mode input voltage.
This might occur in very severe industrial applications where
a sensor or system fault might apply very large voltages on the
inputs of the OP275. Even though the input voltage range of the
OP275 is ±10.5 V, an input voltage of approximately –13.5 V will
cause output voltage phase reversal. In inverting amplier con-
gurations, the OP275’s internal 7.5 V input clamping diodes will
prevent phase reversal; however, they will not prevent this effect
from occurring in noninverting applications. For these applications,
the x is a simple one and is illustrated in Figure 9. A 3.92 k
resistor in series with the noninverting input of the OP275 cures
the problem.
Figure 9. Output Voltage Phase Reversal Fix
Overload or Overdrive Recovery
Overload or overdrive recovery time of an operational amplier
is the time required for the output voltage to recover to a rated
output voltage from a saturated condition. This recovery time
is important in applications where the amplier must recover
quickly after a large abnormal transient event. The circuit shown
in Figure 10 was used to evaluate the OP275’s overload recovery
time. The OP275 takes approximately 1.2 ms to recover to VOUT =
+10 V and approximately 1.5 µs to recover to VOUT = –10 V.
VIN
VOUT
RL
2.43k
A1 = 1/2 OP275
R2
10k
R1
1k
4V p-p
@100Hz
1
2
3A1
R
S
909k
–
+
Figure 10. Overload Recovery Time Test Circuit
Measuring Settling Time
The design of OP275 combines a high slew rate and a wide gain
bandwidth product to produce a fast settling (tS < 1 µs) amplier
for 8- and 12-bit applications. The test circuit designed to mea-
sure the settling time of the OP275 is shown in Figure 11. This
test method has advantages over false-sum node techniques in
that the actual output of the amplier is measured, instead of an
error voltage at the sum node. Common-mode settling effects are
exercised in this circuit in addition to the slew rate and band-
width effects measured by the false-sum node method. Of course,
a reasonably at-top pulse is required as the stimulus.
The output waveform of the OP275 under test is clamped by
Schottky diodes and buffered by the JFET source follower.
The signal is amplied by a factor of 10 by the OP260 and
then Schottky-clamped at the output to prevent overloading the
oscilloscope’s input amplier. The OP41 is congured as a fast
integrator, which provides overall dc offset nulling.
High Speed Operation
As with most high speed ampliers, care should be taken with
supply decoupling, lead dress, and component placement.
Recommended circuit congurations for inverting and nonin-
verting applications are shown in Figures 12 and 13.
REV. C
REV. C
OP275
–8–
OP275
–9–
+15V
+
0.1F
2
3
8
1
4
V
IN
V
OUT
R
L
2k
–15V
10F
0.1F
1/2
OP275
10F
+
–
+
Figure 12. Unity Gain Follower
0.1
F
+15V
+
10
F
2
3
8
1
4
VIN
VOUT
2k
–15V
10
F
0.1
F
10pF
4.99k
2.49k
4.99k
+
1/2
OP275
–
+
Figure 13. Unity Gain Inverter
In inverting and noninverting applications, the feedback resis-
tance forms a pole with the source resistance and capacitance
(RS and CS) and the OP275’s input capacitance (CIN), as shown
in Figure 14. With RS and RF in the kilohm range, this pole
can create excess phase shift and even oscillation. A small
capacitor, CFB, in parallel and RFB eliminates this problem.
By setting RS (CS + CIN) = RFBCFB, the effect of the feedback
pole is completely removed.
16V–20V
0.1F
V+
5V
RL
1k
D1 D2
+15V
2N4416
1k
D3 D4
OUTPUT
(TO SCOPE)
1F
10k
IC2
RF
2k
750
2N2222A
15k
–15V
1N4148
DUT 1/2 OP260AJ
16V–20V
0.1F
10k
– +
+–
SCHOTTKY DIODES D1–D4 ARE
HEWLETT-PACKARD HP5082-2835
IC1 IS 1/2 OP260AJ
IC2 IS PMI OP41EJ
V–
R
G
222
–
+
–
+–
+
Figure 11. OP275’s Settling Time Test Fixture
R
FB
C
IN
R
S
C
S
C
FB
V
OUT
–
+
Figure 14. Compensating the Feedback Pole
Attention to Source Impedances Minimizes Distortion
Since the OP275 is a very low distortion amplier, careful atten-
tion should be given to source impedances seen by both inputs.
As with many FET-type ampliers, the p-channel JFETs in the
OP275’s input stage exhibit a gate-to-source capacitance that var-
ies with the applied input voltage. In an inverting conguration,
the inverting input is held at a virtual ground and, as such, does
not vary with input voltage. Thus, since the gate-to-source voltage
is constant, there is no distortion due to input capacitance modu-
lation. In noninverting applications, however, the gate-to-source
voltage is not constant. The resulting capacitance modulation
can cause distortion above 1 kHz if the input impedance is
greater than 2 k
and unbalanced.
OP275
VIN
VOUT
RF
RG
RS*
*
RS = RG//RF IF RG//RF > 2k
FOR MINIMUM DISTORTION
–
+
Figure 15. Balanced Input Impedance to Minimize
Distortion in Noninverting Amplier Circuits
Figure 15 shows some guidelines for maximizing the distortion
performance of the OP275 in noninverting applications. The best
way to prevent unwanted distortion is to ensure that the parallel
combination of the feedback and gain setting resistors (RF and
RG) is less than 2 k
. Keeping the values of these resistors small
has the added benets of reducing the thermal noise of the circuit
REV. C
REV. C
OP275
–10–
OP275
–11–
and dc offset errors. If the parallel combination of RF and RG is
larger than 2 k
, then an additional resistor, RS, should be used
in series with the noninverting input. The value of RS is deter-
mined by the parallel combination of RF and RG to maintain the
low distortion performance of the OP275.
Driving Capacitive Loads
The OP275 was designed to drive both resistive loads to 600
and capacitive loads of over 1000 pF and maintain stability. While
there is a degradation in bandwidth when driving capacitive loads,
the designer need not worry about device stability. The graph in
Figure 16 shows the 0 dB bandwidth of the OP275 with capaci-
tive loads from 10 pF to 1000 pF.
10
9
8
7
6
5
4
3
2
1
0
0 200 400 600 800 1000
C
LOAD
– pF
BANDWIDTH – MHz
Figure 16. Bandwidth vs. CLOAD
High Speed, Low Noise Differential Line Driver
The circuit in Figure 17 is a unique line driver widely used in
industrial applications. With ±18 V supplies, the line driver can
deliver a differential signal of 30 V p-p into a 2.5 k
load. The
high slew rate and wide bandwidth of the OP275 combine to
yield a full power bandwidth of 130 kHz while the low noise
front end produces a referred-to-input noise voltage spectral
density of 10 nV/
Hz.
1
2
3A2
1
3
2A1
5
6
7
A3
V
IN
V
O1
V
O2
R3
2k
R9
50
R11
1k
P1
10k
R12
1k
R10
50
R8
2k
R2
2k
R5
2k
R4
2k
R1
2k
R7
2k
V
O2
– V
O1
= V
IN
A1 = 1/2 OP275
A2, A3 = 1/2 OP275
GAIN =
SET R2, R4, R5 = R1 AND R6, R7, R8 = R3
R3
R1
R6
2k
–
+
–
+
–
+
Figure 17. High Speed, Low Noise Differential Line Driver
The design is a transformerless, balanced transmission system
where output common-mode rejection of noise is of paramount
importance. Like the transformer based design, either output can
be shorted to ground for unbalanced line driver applications
without changing the circuit gain of 1. Other circuit gains can be
set according to the equation in the diagram. This allows the
design to be easily set to noninverting, inverting, or differential
operation.
A 3-Pole, 40 kHz Low-Pass Filter
The closely matched and uniform ac characteristics of the OP275
make it ideal for use in GIC (Generalized Impedance Converter)
and FDNR (Frequency-Dependent Negative Resistor) lter
applications. The circuit in Figure 18 illustrates a linear-phase,
3-pole, 40 kHz low-pass lter using an OP275 as an inductance
simulator (gyrator). The circuit uses one OP275 (A2 and A3) for
the FDNR and one OP275 (A1 and A4) as an input buffer and
bias current source for A3. Amplier A4 is congured in a gain
of 2 to set the pass band magnitude response to 0 dB. The ben-
ets of this lter topology over classical approaches are that the
op amp used in the FDNR is not in the signal path and that the
lter’s performance is relatively insensitive to component varia-
tions. Also, the conguration is such that large signal levels can
be handled without overloading any of the lter’s internal nodes.
As shown in Figure 19, the OP275’s symmetric slew rate and low
distortion produce a clean, well behaved transient response.
V
IN
3
2
1
A1
R1
95.3k
R2
787
C1
2200pF
C2
2200pF
R3
1.82k
C3
2200pF
R4
1.87k
R5
1.82k
A2
1
2
3
5
6
7
A3
R6
4.12k
C4
2200pF R7
100k
5
6
7
A4
R8
1k
R9
1k
V
OUT
A1, A4 = 1/2 OP275
A2, A3 = 1/2 OP275
–
+
–
+
–
+
–
+
Figure 18. A 3-Pole, 40 kHz Low-Pass Filter
V
OUT
10V p-p
10kHz
SCALE: VERTICAL–2V/ DIV
HORIZONTAL–10
s/ DIV
10
0%
100
90
Figure 19. Low-Pass Filter Transient Response
REV. C
REV. C
OP275
–10–
OP275
–11–
OP275 SPICE Model
*
* Node assignments
* noninverting input
* inverting input
* positive supply
* negative supply
* output
**
.SUBCKT OP275 1 2 99 50 34
*
* INPUT STAGE & POLE AT 100 MHz
*
R3 5 51 2.188
R4 6 51 2.188
CIN 1 2 3.7E-12
CM1 1 98 7.5E-12
CM2 2 98 7.5E-12
C2 5 6 364E-12
I1 97 4 100E-3
IOS 1 2 1E-9
EOS 9 3 POLY(1) 26 28 0.5E-3 1
Q1 5 2 7 QX
Q2 6 9 8 QX
R5 7 4 1.672
R6 8 4 1.672
D1 2 36 DZ
D2 1 36 DZ
EN 3 1 10 0 1
GN1 0 2 13 0 1E-3
GN2 0 1 16 0 1E-3
*
EREF 98 0 28 0 1
EP 97 0 99 0 1
EM 51 0 50 0 1
*
* VOLTAGE NOISE SOURCE
*
DN1 35 10 DEN
DN2 10 11 DEN
VN1 35 0 DC 2
VN2 0 11 DC 2
*
* CURRENT NOISE SOURCE
*
DN3 12 13 DIN
DN4 13 14 DIN
VN3 12 0 DC 2
VN4 0 14 DC 2
*
* CURRENT NOISE SOURCE
*
DN5 15 16 DIN
DN6 16 17 DIN
VN5 15 0 DC 2
VN6 0 17 DC 2
*
* GAIN STAGE & DOMINANT POLE AT 32 Hz
*
R7 18 98 1.09E6
C3 18 98 4.55E-9
G1 98 18 5 6 4.57E-1
V2 97 19 1.35
V3 20 51 1.35
D3 18 19 DX
D4 20 18 DX
* POLE/ZERO PAIR AT 1.5 MHz/2.7 MHz
*
R8 21 98 1E-3
R9 21 22 1.25E-3
C4 22 98 47.2E-12
G2 98 21 18 28 1E-3
*
* POLE AT 100 MHz
*
R10 23 98 1
C5 23 98 1.59E-9
G3 98 23 21 28 1
*
* POLE AT 100 MHz
*
R11 24 98 1
C6 24 98 1.59E-9
G4 98 24 23 28 1
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT
1 kHz
*
R12 25 26 1E6
C7 25 26 1.5915E-12
R13 26 98 1
E2 25 98 POLY(2) 1 98 2 98 0 2.50
2.50
*
* POLE AT 100 MHz
*
R14 27 98 1
C8 27 98 1.59E-9
G5 98 27 24 28 1
*
* OUTPUT STAGE
*
R15 28 99 100E3
R16 28 50 100E3
C9 28 50 1E-6
ISY 99 50 1.85E-3
R17 29 99 100
R18 29 50 100
L2 29 34 1E-9
G6 32 50 27 29 10E-3
G7 33 50 29 27 10E-3
G8 29 99 99 27 10E-3
G9 50 29 27 50 10E-3
V4 30 29 1.3
V5 29 31 3.8
F1 29 0 V4 1
F2 0 29 V5 1
D5 27 30 DX
D6 31 27 DX
D7 99 32 DX
D8 99 33 DX
D9 50 32 DY
D10 50 33 DY
*
* MODELS USED
*
.MODEL QX PNP(BF=5E5)
.MODEL DX D(IS=1E-12)
.MODEL DY D(IS=1E-15 BV=50)
.MODEL DZ D(IS=1E-15 BV=7.0)
.MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15
AF=1)
.MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1)
.ENDS
REV. C
REV. C
C00298–0–2/04(C)
–12–
OP275
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
(S Sufx)
(R-8)
Dimensions shown in millimeters and (inches)
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
8 5
41
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
8-Lead Plastic Dual-in-Line Package [PDIP]
(P Sufx)
(N-8)
Dimensions shown in inches and (millimeters)
SEATING
PLANE
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79) 0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
8
14
50.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.100 (2.54)
BSC
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
0.015
(0.38)
MIN
Revision History
Location Page
2/04—Data Sheet changed from REV. B to REV. C.
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1/03—Data Sheet changed from REV. A to REV. B.
Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
REV. C