74LV165
8-bit parallel-in/serial-out shift register
Product specification
Supersedes data of 1997 May 15
IC24 Data Handbook
1998 May 07
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74LV1658-bit parallel-in/serial-out shift register
2
1998 May 07 853–1915 19349
FEATURES
•Wide operating voltage: 1.0 to 5.5 V
•Optimized for low voltage applications: 1.0 to 3.6 V
•Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
•Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C
•Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
Tamb = 25°C
•Asynchronous 8-bit parallel load
•Synchronous serial input
•Output capability: standard
•ICC category: MSI
DESCRIPTION
The 74LV165 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT165.
The 74LV165 is an 8-bit parallel-load or serial-in shift register with
complementary serial outputs (Q7 and Q7) available from the last
stage. When the parallel load (PL) input is LOW, parallel data from the
D0 to D7 inputs are loaded into the register asynchronously. When PL
is HIGH, data enters the register serially at the DS input and shifts one
place to the right (Q0→Q1→Q2, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter expansion by
tyin g the Q7 output to the DS input of the succeeding stage.
The clock input is a gated-OR structure which allows one input to be
used as an active LOW clock enable (CE) input. The pin assignment
for the CP and CE inputs is arbitrary and can be reversed for layout
convenience. The LOW-to-HIGH transition of input CE should only
take place while CP HIGH for predictable operation. Either the CP or
the CE should be HIGH before the LOW-to-HIGH transition of PL to
prevent shifting the data when PL is activated.
QUICK REFERENCE DATA
GND = 0 V ; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH
Propagation delay
CE, CP to Q7, Q7
PL to Q7, Q7
D7 to Q7, Q7
CL = 15 pF;
VCC = 3.3 V 18
18
14 ns
fmax Maximum clock frequency 78 MHz
CIInput capacitance 3.5 pF
CPD Power dissipation capacitance per gate VCC = 3.3 V
VI = GND to VCC135 pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V ;
(CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
16-Pin Plastic DIL –40°C to +125°C74LV165 N 74LV165 N SOT38-4
16-Pin Plastic SO –40°C to +125°C74LV165 D 74LV165 D SOT109-1
16-Pin Plastic SSOP T ype II –40°C to +125°C74LV165 DB 74LV165 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +125°C74LV165 PW 74LV165PW DH SOT403-1
PIN CONFIGURATION
SV00585
1
2
3
4
5
6
PL
CP
D4
D5
D6
D7
VCC
CE
D3
16
15
14
13
12
11
7
8
GND
DS
Q7
10
9
Q7
D2
D1
D0
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1PL Asynchronous parallel load
input (active LOW)
2 CP Clock input (LOW to
HIGH, edge-triggered)
7 Q7Complementary output from
the last stage
8 GND Ground (0 V)
9 Q7Serial output from last stage
10 DSSerial data input
11, 12, 13, 14, 3, 4, 5, 6 D0 to D7Parallel data inputs
15 CE Clock enable input
(active LOW)
16 VCC Positive supply voltage
Philips Semiconductors Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07 3
LOGIC SYMBOL
SV00586
9
10
Q7
CE
CP
PL
D7
D6
D5
D4
D3
D2
D0DS
D1
1
215
6
5
4
3
14
13
12
11
Q77
LOGIC SYMBOL (IEEE/IEC)
SV00587
SRG8
3D
2D
2D
C2 [LOAD]
G1 [SHIFT]
11
1
15
2
10
11
12
13
14
3
4
5
67
9
>C3/
FUNCTIONAL DIAGRAM
SV00588
D7
D6
D5
D4
D3
D2
D1
D0
PL
DS
CP
Q79
7
CE
Q7
10
2
15
1
8–BIT SHIFT REGISTER
PARALLEL– IN / SERIAL – OUT
654314131211
LOGIC DIAGRAM
SV00589
D0
DS
CP
CE
PL
SD
D
CP
FF0 FF1 FF2 FF3 FF4 FF5 FF6 FF7
Q
D4
SD
D
CP
Q
D2
SD
D
CP
Q
D6
SD
D
CP
Q
D1
SD
D
CP
Q
D5
SD
D
CP
Q
D3
SD
D
CP
Q
D7
SD
RDRD
RDRD
RDRD
RDRD
D
CP
QQ7
Q7
Q
Philips Semiconductors Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07 4
FUNCTION TABLE
OPERATING MODES
INPUTS Qn REGISTERS OUTPUTS
OPERATING
MODES
PL CE CP DSD0–D7Q0Q1–Q6Q7Q7
Parallel load
L X X X L L L–L L H
Parallel
load
L X X X H H H–H H L
Serial Shift
H L ↑l X L q0–q5q6q6
Serial
Shift
H L ↑h X H q0–q5q6q6
Hold “do nothing” H H X X X q0q1–q6q7q7
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition
X = don’t care
↑= LOW-to-HIGH clock transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
VCC DC supply voltage See Note 1 1.0 3.3 5.5 V
VIInput voltage 0 – VCC V
VOOutput voltage 0 – VCC V
Tamb Operating ambient temperature range in free air See DC and AC
characteristics –40
–40 +85
+125 °C
tr, tfInput rise and fall times VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V to 5.5V
–
–
–
–
–
–
–
–
500
200
100
50 ns/V
NOTE:
1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +7.0 V
IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
IODC output source or sink current
– standard outputs –0.5V < VO < VCC + 0.5V 25 mA
IGND,
ICC
DC VCC or GND current for types with
– standard outputs 50 mA
Tstg Storage temperature range –65 to +150 °C
PTOT
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400 mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07 5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS
SYMBOL PARAMETER TEST CONDITIONS -40°C to +85°C -40°C to +125°CUNIT
MIN TYP1MAX MIN MAX
VCC = 1.2 V 0.9 0.9
V
HIGH level Input VCC = 2.0 V 1.4 1.4
V
V
IH voltage VCC = 2.7 to 3.6 V 2.0 2.0
V
VCC = 4.5 to 5.5 V 0.7VCC 0.7VCC
VCC = 1.2 V 0.3 0.3
V
LOW level Input VCC = 2.0 V 0.6 0.6
V
V
IL voltage VCC = 2.7 to 3.6 V 0.8 0.8
V
VCC = 4.5 to 5.5 0.3VCC 0.3VCC
VCC = 1.2 V ; VI = VIH or VIL; –IO = 100µA 1.2
HIGH l l t t
VCC = 2.0 V ; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8
VOH HIGH level output
voltage
;
all out
p
uts
VCC = 2.7 V ; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 V
voltage
all
out uts
VCC = 3.0 V ; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8
VCC = 4.5 V ; VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3
VO
HIGH level output
volta
g
e; VCC = 3.0 V ; VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20
V
V
OH
g
STANDARD
outputs VCC = 4.5 V ; VI = VIH or VIL; –IO = 12mA 3.60 4.20 3.50
V
VCC = 1.2 V ; VI = VIH or VIL; IO = 100µA 0
LOW l l t t
VCC = 2.0 V ; VI = VIH or VIL; IO = 100µA 0 0.2 0.2
VOL LOW level output
voltage
;
all out
p
uts
VCC = 2.7 V ; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 V
voltage
all
out uts
VCC = 3.0 V ; VI = VIH or VIL; IO = 100µA 0 0.2 0.2
VCC = 4.5 V ; VI = VIH or VIL; IO = 100µA 0 0.2 0.2
VO
LOW level output
volta
g
e; VCC = 3.0 V ; VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50
V
V
OL
g
STANDARD
outputs VCC = 4.5 V ; VI = VIH or VIL; IO = 12mA 0.35 0.55 0.65
V
IIInput leakage
current VCC = 5.5 V ; VI = VCC or GND 1.0 1.0 µA
ICC Quiescent supply
current; MSI VCC = 5.5 V ; VI = VCC or GND; IO = 0 20.0 160 µA
∆ICC Additional
quiescent supply
current per input VCC = 2.7 V to 3.6 V ; V I = VCC – 0.6 V 500 850 µA
NOTE:
1. All typical values are measured at Tamb = 25°C.
Philips Semiconductors Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07 6
AC CHARACTERISTICS
GND = 0V ; tr = tf ≤ 2.5ns; C L = 50pF; RL = 1KΩ
CONDITION
LIMITS
SYMBOL PARAMETER WAVEFORM
CONDITION
–40 to +85 °C–40 to +125 °CUNIT
VCC(V) MIN TYP1MAX MIN MAX
1.2 – 115 –
2.0 – 38 61 – 76
tPLH/tPHL Propagation delay
CE
,
CP to Q
7,
Q
7
Figures 1, 2 2.7 – 27 43 – 54 ns
CE,
CP
to
Q7,
Q7
3.0 to 3.6 – 22236 – 45
4.5 to 5.5 – 15 24 – 30
1.2 – 110 –
2.0 – 35 56 – 70
tPLH/tPHL Propagation delay
PL to Q
7,
Q
7
Figures 1, 2 2.7 – 24 39 – 49 ns
PL
to
Q7,
Q7
3.0 to 3.6 – 20233 – 41
4.5 to 5.5 – 14 22 – 27
1.2 – 90 –
2.0 – 28 45 – 56
tPLH/tPHL Propagation delay
D
7
to Q
7,
Q
7
Figures 1, 2 2.7 – 20 32 – 40 ns
D7
to
Q7,
Q7
3.0 to 3.6 – 17227 – 33
4.5 to 5.5 –11 18 – 22
2.0 34 10 – 41 –
t
Clock Pulse width
Figures 1 2
2.7 25 8 – 30 –
ns
t
wHIGH or LOW
Fig
u
res
1
,
2
3.0 to 3.6 20 72– 24 –
ns
4.5 to 5.5 15 5 – 18 –
2.0 34 10 – 41 –
t
Parallel load pulse
Figures 1 2
2.7 25 8 – 30 –
ns
t
wwidth LOW
Fig
u
res
1
,
2
3.0 to 3.6 20 72– 24 –
ns
4.5 to 5.5 15 5 – 18 –
1.2 – 40 – – –
2.0 24 15 – 30 –
trem Removal time
PL to CP
,
CE Figures 1, 2 2.7 18 11 – 23 – ns
PL
to
CP,
CE
3.0 to 3.6 17 102– 21 –
4.5 to 5.5 12 7 – 15 –
1.2 – –8 – – –
2.0 22 –2 – 26 –
tsu Set-up time
D
S
to CP
,
CE Figures 1, 2 2.7 16 –1 – 19 – ns
DS
to
CP,
CE
3.0 to 3.6 13 –12– 15 –
4.5 to 5.5 9 0 – 10 –
1.2 – 20 – – –
2.0 22 7 – 26 –
tsu Set-up time
CE to CP; CP to CE Figures 1, 2 2.7 16 5 – 19 – ns
CE
to
CP
CP
to
CE
3.0 to 3.6 13 42– 15 –
4.5 to 5.5 9 3 – 10 –
Philips Semiconductors Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07 7
AC CHARACTERISTICS (
Continued
)
GND = 0V ; tr = tf ≤ 2.5ns; C L = 50pF; RL = 1KΩ
SYMBOL
PARAMETER
WAVEFORM
CONDITION –40 to +85 °C–40 to +125 °C
UNIT
SYMBOL
PARAMETER
WAVEFORM
VCC(V) MIN TYP1MAX MIN MAX
UNIT
1.2 – 25 – – –
2.0 22 8 – 26 –
tsu Set-up time
D
n
to PL Figures 1, 2 2.7 16 6 – 19 – ns
Dn
to
PL
3.0 to 3.6 13 52– 15 –
4.5 to 5.5 9 4 – 10 –
1.2 – 20 – – –
Hold time
2.0 22 7 – 26 –
th
Hold
time
Ds to CP, CE
D to PL
Figures 1, 2 2.7 16 5 – 19 – ns
D
n
t
o
PL
3.0 to 3.6 13 4 – 15 –
4.5 to 5.5 9 3 – 10 –
1.2 – –30 – – –
Hold time
2.0 5 –8 – 5 –
th
Hold
time
CE to CP,
CP t CE
Figures 1, 2 2.7 5 –6 – 5 – ns
CP
to
CE
3.0 to 3.6 5 –52– 5 –
4.5 to 5.5 5 –4 – 5 –
2.0 14 40 – 12 –
f
Maximum clock
Figures 1 2
2.7 19 60 – 16 –
MHz
f
max pulse frequency
Fig
u
res
1
,
2
3.0 to 3.6 24 652– 20 –
MH
z
4.5 to 5.5 36 75 – 30 –
NOTES:
1. Unless otherwise stated, all typical values are measured at Tamb = 25°C
2. Typical values are measured at VCC = 3.3 V.
AC WAVEFORMS
VM = 1 . 5 V a t VCC ≥ 2.7 V.
VM = 0 . 5 × VCC at VCC < 2.7 V;
VOL an d V OH are the typical output voltage drop that occur with the
output load.
SV00590
VM
CP INPUT
VI
GND
VOH
VOL
Q7 or Q7
OUTPUT VM
tPLH
tPHL
tW
1/fmax
The changing to output assumes internal Q6 opposite state from Q7.
Figure 1. Clock (CP) to output (Q7 or Q7) propagation delays,
the clock pulse width and the maximum clock frequency.
Note to Figures 1 and 2
The changing to output assumes internal Q6 opposite state from Q7.
SV00591
VM
PL INPUT
CE, CP INPUT
VI
VI
GND
GND
VOL
VOH
Q7 or Q7 OUTPUT VM
VM
trem
tPHL
tW
The changing to output assumes internal Q6 opposite state from Q7.
Figure 2. Parallel load (PL ) pulse width, the parallel load to
output (Q7 or Q7) propagation delays, the parallel load to clock
(CP) and clock enable (CE) removal time.
Philips Semiconductors Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07 8
AC WAVEFORMS
VM = 1 . 5 V a t VCC ≥ 2.7 V.
VM = 0 . 5 × VCC at VCC < 2.7 V;
VOL an d V OH are the typical output voltage drop that occur with the
output load.
SV00592
D7 INPUT VM
VM
VM
Q7 OUTPUT
Q7 OUTPUT
VOL
VOL
GND
VOH
VOH
VI
tPLH tPHL
tPHL tPLH
Figure 3. Data input (Dn) to output (Q7 or Q7) propagation
delays when PL is LOW.
SV00595
VM
VM
CP, CE
INPUT
DS INPUT
CP, CE
INPUT
GND
GND
GND
VI
VI
VI
stable
VM
th
tsu (H)
tW
tsu (L)
tsu
th
th
see note
CE may change only from HIGH-to-LOW while CP is LOW. The shaded
areas indicate when the input is permitted to change for predictable output
performance.
Figure 4. Set -u p a n d h o ld t i m e s f ro m t h e se r i a l d a ta i nput (DS) t o
the clock (CP) and the clock enable (CE) inputs, from the clock
enable input (CE) to the clock input (CP) and from the clock input
(CP) to the clock enable input (CE).
Note to Figure 4
CE may change only from HIGH-to-LOW while CP is LOW. The
shaded areas indicate when the input is permitted to change for
predictable output performance.
SV00593
VM
VM
Dn INPUT
PL INPUT
GND
GND
VI
VI
tsu tsu
tHtH
Figure 5. Set-up and hold times from the data inputs (Dn)
to the parallel load input (PL).
TEST CIRCUIT
PULSE
GENERATOR
RT
Vl
D.U.T.
VO
CLRL= 1k
Vcc
Test Circuit for Outputs
DEFINITIONS
VCC VI
< 2.7V
2.7–3.6V
VCC
2.7V
TEST
tPLH/tPHL
≥4.5 V VCC
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance
50pF
RT = Termination resistance should be equal to ZOUT of pulse generators.
SV00902
Figure 6. Load circuitry for switching times.
Philips Semiconductors Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07 9
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
Philips Semiconductors Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07 10
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Philips Semiconductors Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07 11
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
Philips Semiconductors Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07 12
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
Philips Semiconductors Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07 13
NOTES
Philips Semiconductors Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07 14
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appl iances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-04432
