PCM1740E-2/2KG4 - Texas Instruments

Stereo Audio

DIGITAL-TO-ANALOG CONVERTER

with VCXO and PLL

PCM1740

FEATURES

●COMPLETE DELTA-SIGMA STEREO DAC

●VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR:

27MHz ±150ppm Output with 0V to 3V Input

●PROGRAMMABLE PLL

256fS or 384fS Audio System Clock Output

●DYNAMIC PERFORMANCE:

Dynamic Range: 94dB

SNR: 94dB

THD+N: –89dB

●SAMPLING FREQUENCIES:

16kHz, 22.05kHz, 24kHz

32kHz, 44.1kHz, 48kHz

64kHz, 88.2kHz, 96kHz

●SERIAL AUDIO INTERFACE:

Standard or I2S™ Data Formats

16-, 20-, or 24-Bit Data

●I2C-BUS™ INTERFACE FOR CONTROL

REGISTERS:

Slave Receiver Operation

7-Bit Addressing

Standard Transfer Rate (up to 100kbps)

●PROGRAMMABLE CONTROLS:

Digital Attenuation (256 steps)

Soft Mute

Infinite Zero Detect Mute

De-Emphasis (32kHz, 44.1kHz, 48kHz)

DAC Output Mode

●SINGLE +5V SUPPLY

●SMALL SSOP-24 PACKAGE

DESCRIPTION

The PCM1740 is a complete stereo audio digital-to-

analog converter with on-chip PLL and VCXO. The

PCM1740 is designed specifically for set-top box applica-

tions requiring high-quality audio playback, a precision

tuned 27MHz master clock source, and support for mul-

tiple audio-sampling frequencies.

The stereo digital-to-analog converter (DAC) uses multi-

bit, delta-sigma architecture, which includes an 8x inter-

polation filter, 3rd-order noise shaping, 5-level amplitude

quantization, and an analog low-pass filter. The PCM1740

includes a number of user-programmable functions, which

are accessed via a standard I2C-Bus interface.

APPLICATIONS

●SET-TOP BOXES

●DIGITAL BROADCAST RECEIVERS

PCM1740

PCM

Audio

I/F

and

REGs

VCXO

SCL

SDA

AD1

AD0

XTUN

XT1

XT2

RST

27MHz

Crystal

Oversampling

Digital Filter

and

Sub-Functions

Process DAC

(R)

Counter N

OUT

COM

ZERO

SCKO

(256f

/384f

)

MCKO

(27MHz)

OUT

Counter M

Power Supply

Reset

BCK

LRCK

DATA

Phase

Detector

AGND DGNDV

PGND

DAC

(L) Low-Pass

Filter

and Amp

LPF VCO

SBAS128B – JANUARY 2000 – REVISED MAY 2007

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SoundPLUS is a trademark of Texas Instruments.

I2C-Bus, I2C, and I2S are trademarks of NXP B.V.

All other trademarks are the property of their respective owners.

PCM1740

2SBAS128B

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PIN NAME I/O FUNCTION

1 XT1 — 27MHz Crystal connection.

2 PGND — PLL and VCXO ground.

3 XTUN IN VCXO tune, tuning voltage range from 0V to 3V.

PP — PLL and VCXO power supply, +5V.

5 MCKO OUT Buffered clock output of VCXO.

6 AD0 IN Device address pin for I2C-BUS.(1)

7 AD1 IN Device address pin for I2C-BUS.(1)

8 SCL IN Bit clock input for I2C-BUS interface.

9SDA

IN/OUT

Serial data for I2C-BUS interface.

10 RST IN Reset, active LOW.(2)

11 VOUTR OUT Right-channel analog voltage output.

12 AGND — Analog ground.

13 VCC — Analog power supply, +5V.

14 VOUTL OUT Left-channel analog voltage output.

15 VCOM — DC common-mode voltage output.

16 ZERO OUT Zero flag output, active LOW.(3)

17 BCK IN Bit clock input for serial audio data.(1)

18 DATA IN Serial audio data input.(1)

19 LRCK IN Left and right word clock, equal to the sampling

rate (fS).(1)

20 RSV — Reserved must be open.

21 SCKO OUT System clock output, 256/384 fS.

22 VDD — Digital power supply, +5V.

23 DGND — Digital ground.

24 XT2 — 27MHz Crystal connection.

NOTES: (1) Schmitt trigger input.

(2) Schmitt trigger input with internal pull-up resistor.

(3) Open drain output.

Power Supply Voltage(2) ...................................................................+6.5V

Supply Voltage Differences(3) ........................................................... ±0.1V

GND Voltage Differences(4) .............................................................. ±0.1V

Digital Input Voltage................................................. –0.3V to (VDD + 0.3V)

Analog Input Voltage................................................ –0.3V to (VCC + 0.3V)

Input Current (any pins except supplies) ........................................ ±10mA

Operating Temperature Range ......................................... –25°C to +85°C

Storage Temperature...................................................... –55°C to +125°C

Junction Temperature .................................................................... +150°C

Lead Temperature (soldering, 5s).................................................. +260°C

Package Temperature (IR reflow, peak, 10s) ................................ +235°C

NOTES: (1) Stresses above those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability. (2) VCC, VDD, VPP.

(3) Among VCC, VDD, VPP. (4) Among AGND, DGND, and PGND.

PIN ASSIGNMENTSPIN CONFIGURATION

Top View SSOP

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

handled with appropriate precautions. Failure to observe

proper handling and installation procedures can cause

damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

SPECIFIED

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA

PCM1740E SSOP-24 DB –25°C to +85°C PCM1740E PCM1740E Rails, 58

" " " " PCM1740E PCM1740E/2K Tape and Reel, 2000

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com.

PACKAGE/ORDERING INFORMATION(1)

XT1

PGND

XTUN

VPP

MCKO

AD0

AD1

SCL

SDA

RST

VOUTR

AGND

PCM1740

XT2

DGND

VDD

SCKO

RSV

LRCK

DATA

BCK

ZERO

VCOM

VOUTL

VCC

PCM1740 3

SBAS128B www.ti.com

ELECTRICAL CHARACTERISTICS

All specifications at TA = +25°C, VCC = VDD = VPP = 5.0V, fS = 44.1kHz, system clock = 384fS, 16-bit data, unless otherwise noted.

PCM1740E

PARAMETER CONDITIONS MIN TYP MAX UNITS

RESOLUTION 16 Bits

DATA FORMAT

Audio Interface Format Standard/I2S Selectable

Audio Data Bit Length 16/20/24 Selectable Bits

Audio Data Format MSB First, Two’s Binary Complement

Sampling Frequency (fS) Standard (fS) 32 44.1 48 kHz

Half (fS) 16 22.05 24 kHz

Double (fS) 64 88.2 96 kHz

Internal System Clock Frequency 256fS/384fS

DIGITAL INPUT/OUTPUT

Logic Family Input Logic TTL Compatible

High Level Input Voltage: VIH(1), (2) 2.0 VDC

Low Level Input Voltage: VIL(1), (2) 0.8 VDC

High Level Input Current: IIH(1), (2) VIH = VDD ±10 µA

Low Level Input Current:

IIL(1) VIL = 0V ±10 µA

IIL(2) VIL = 0V –120 µA

High Level Output Voltage: VOH(3) IOH = –2mA VDD – 0.5V VDC

Low Level Output Voltage:

VOL(3) IOL = 4mA 0.5 VDC

VOL(4) IOL = 2mA 0.5 VDC

DIGITAL INPUT/OUTPUT of I2C-BUS INTERFACE

High Level Input Voltage: VIH(5) 3.0 V

Low Level Input Voltage: VIL(5) –0.3 1.5 V

Low Level Output Voltage: VOL(6) 0 0.4 V

Output Fall Time: tOF(7) 250 ns

Input Logic Current: II(8) 10% to 90% of VDD –10 10 µA

Capacitance for each I/O pin: CI(5) 10 pF

VCXO CHARACTERISTICS (MCKO) 27MHz, Fundamental Crystal

Crystal Clock Frequency(9) 27.0000 MHz

Crystal Clock Accuracy(9) ±30 ppm

XTUN Tuning Voltage Range(10) 0 3.0 V

XTUN Input Impedance(10) 60 kΩ

Output Clock Frequency XTUN = 1.3V 27.0000 MHz

Output Clock Accuracy XTUN = 1.3V ±50 ppm

VCXO Tuning Range XTUN = 0V – 3V 300 ppm

Output Clock Duty Cycle 10pF Load 35 45 55 %

Output Clock Jitter Standard Deviation 100 ps

Output Rise Time 20% to 80% VDD, 10pF Load 4 ns

Output Fall Time 80% to 20% VDD, 10pF Load 4 ns

Response Time(11) 10 µs

Power Up Time(12) 5ms

PLL AC CHARACTERISTICS (SCKO)

Output Clock Frequency MCKO = 27.0MHz 4.096 36.864 MHz

Output Clock Duty Cycle 10pF Load 40 50 60 %

Output Clock Jitter Standard Deviation 150 ps

Output Rise Time 20% to 80% VDD, 10pF Load 4 ns

Output Fall Time 80% to 20% VDD, 10pF Load 4 ns

Frequency Transition Time(13) 20 ms

Power Up Time(14) 15 30 ms

DYNAMIC PERFORMANCE(15)

THD+N:

VOUT = 0dB fS = 44.1kHz 0.0035 0.01 %

fS = 96kHz 0.007 %

VOUT = –60dB fS = 44.1kHz 0.0035 0.01 %

fS = 96kHz 0.007 %

Dynamic Range fS = 44.1kHz, EIAJ, A-Weighted 90 94 dB

fS = 96kHz, A-Weighted 90 dB

Signal-to-Noise Ratio(16) fS = 44.1kHz, EIAJ, A-weighted 90 94 dB

fS = 96kHz, A-weighted 90 dB

Channel Separation fS = 44.1kHz 88 92 dB

fS = 96kHz 88 dB

Level Linearity Error VOUT = –90dB ±1.0 dB

PCM1740

4SBAS128B

www.ti.com

DC ACCURACY

Gain Error ±1.0 ±3.0 % of FSR

Gain Mismatch, Channel-to-Channel ±1.0 ±3.0 % of FSR

Bipolar Zero Error ±1.0 % of FSR

ANALOG OUTPUT

Voltage Range Full Scale (0dB) 0.62 VCC VPP

Center Voltage 0.5 VCC VDC

Load Impedance AC Coupled 5 kΩ

DIGITAL FILTER PERFORMANCE

Passband 0.445 fSHz

Stop Band 0.555 fSHz

Passband Ripple ±0.17 dB

Stop Band Attenuation –35 dB

De-Emphasis Error –0.2 +0.55 dB

Delay Time 11.125/fSsec

ANALOG FILTER PERFORMANCE

Frequency Response 20Hz to 20kHz –0.16 dB

20Hz to 40kHz –0.6 dB

POWER SUPPLY REQUIREMENTS

Voltage Range VDD, VCC, VPP +4.5 +5 +5.5 VDC

Supply Current, IDD + ICC + IPP VDD = VCC = VPP = +5V 25 30 mA

Power Dissipation VDD = VCC = VPP = +5V 125 150 mW

TEMPERATURE RANGE

Operation –25 +85 °C

Storage –55 +125 °C

Thermal Resistance,

JA 100 °C/W

NOTES: (1) Pins 6, 7, 18, 19: AD0, AD1, BCK, DATA, LRCK (Schmitt trigger input).

(2) Pin 10: RST (Schmitt trigger input with internal pull-up resistor).

(3) Pins 5, 21: MCKO, SCKO. (4) Pin 16: ZERO (open drain output).

(5) Pins 8, 9: SCL, SDA.

(6) Pin 9: SDA (open drain output, IOL = 3mA).

(7) Pin 9: SDA (from VIHMIN to VILMAX with a bus capacitance from 10pF to 400pF).

(8) Pins 8, 9: SCL, SDA (input current each I/O pin with an input voltage between 0.1VDD and 0.9VDD).

(9) This characteristic is the requirement for crystal oscillator.

(10) Pin 3: XTUN.

(11) The maximum response time when the XTUN is changed.

(12) The maximum delay time from power on to oscillation.

(13) The maximum lock up time when the PLL frequency is changed.

(14) The maximum delay time from power on to lock up.

(15) Dynamic performance specifications are tested with a 20kHz low-pass filter using a Shibasoku distortion analyzer 725°C with 30kHz LPF, 400Hz

HPF, Average-Mode.

(16) SNR is tested with infinite zero detection circuit disabled.

PCM1740E

PARAMETER CONDITIONS MIN TYP MAX UNITS

ELECTRICAL CHARACTERISTICS (Cont.)

All specifications at TA = +25°C, VCC = VDD = VPP = 5.0V, fS = 44.1kHz, system clock = 384fS, 16-bit data, unless otherwise noted.

PCM1740 5

SBAS128B www.ti.com

TYPICAL CHARACTERISTICS

At TA = +25°C, VCC = VDD = +5V, fS = 44.1kHz, fSCKO = 384fS = 16.9344MHz, and 16-bit data, unless otherwise noted.

FREQUENCY RESPONSE

(De-emphasis OFF, f

= 44.1kHz)

Level (dB)

–20

–40

–60

–80

–100 01234

PASSBAND RIPPLE

(De-emphasis OFF, fS = 44.1kHz)

Level (dB)

–0.2

–0.4

–0.6

–0.8

–10 0.20.1 0.3 0.4 0.5

DE-EMPHASIS FREQUENCY RESPONSE (3kHz)

0 5k 10k 15k 20k 25k

Frequency (Hz)

–2

–4

–6

–8

–10

–12

DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)

0 5k 10k 15k 20k 25k

Frequency (Hz)

–2

–4

–6

–8

–10

–12

DE-EMPHASIS FREQUENCY RESPONSE (48kHz)

0 5k 10k 15k 20k 25k

Frequency (Hz)

–2

–4

–6

–8

–10

–12

Level (dB) Level (dB) Level (dB)

DE-EMPHASIS ERROR (3kHz)

0 3628 7256 10884 14512

0 4999.8375 9999.675 14999.5125 19999.35

0 5442 10884 16326 21768

Frequency (Hz)

0.6

0.4

0.2

–0.2

–0.4

–0.6

0.6

0.4

0.2

–0.2

–0.4

–0.6

0.6

0.4

0.2

–0.2

–0.4

–0.6

DE-EMPHASIS ERROR (44.1kHz)

Frequency (Hz)

DE-EMPHASIS ERROR (48kHz)

Frequency (Hz)

Error (dB) Error (dB) Error (dB)

PCM1740

6SBAS128B

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TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, VCC = VDD = +5V, fS = 44.1kHz, FSCKO = 384fS = 16.9344MHz, and 16-bit data, unless otherwise noted.

ANALOG FILTER

(1Hz to 10MHz)

Log Frequency (Hz)

Level (dB)

–20

–40

–60

–80

–100 0 0.20.1 0.1 0.3 0.40.4 0.5

ANALOG FILTER

(1Hz to 20kHz)

Log Frequency (Hz)

Level (dB)

0.05

–0.05

–0.1

–0.15 110 1k100 10k 100k

SUPPLY CURRENT vs SAMPLING FREQUENCY

Sampling Frequency (kHz)

Supply Current (mA)

20 32 64 88.244.1 48 96.0

THD+N (FS), DYNAMIC RANGE, and SNR

vs SUPPLY VOLTAGE

(Temperature = 25°C, 384fS, fS = 44.1kHz)

Supply Voltage (V)

THD+D (FS) (%)

0.005

0.004

0.003

0.002

0.001

0.000

Dynamic Range, SNR (dB)

4.25 4.5 5.254.75 5 5.5 5.75

SNR

THD+N Dynamic Range

THD+N (FS), DYNAMIC RANGE, and SNR

vs TEMPERATURE

(VCC = VDD = VPP = 5V, 384fS, fS = 44.1kHz)

Temperature (°C)

THD+D (FS) (%)

0.005

0.004

0.003

0.002

0.001

0.000

Dynamic Range, SNR (dB)

–50 –25 500 25 75 100

SNR

THD+N Dynamic Range

THD+N (FS), DYNAMIC RANGE, and SNR

vs SAMPLING FREQUENCY

Sampling Frequency (kHz)

THD+D (FS) (%)

0.010

0.008

0.006

0.004

0.002

0.000

Dynamic Range, SNR (dB)

32 64 88.244.1 48 96.0

SNR

THD+N

Dynamic Range

PCM1740 7

SBAS128B www.ti.com

3rd ORDER ∆Σ MODULATOR

Frequency (kHz)

Gain (–dB)

–20

–40

–60

–80

–100

–120

–140

–160 0 5 10 15 20 25

STEREO DIGITAL-TO-ANALOG

CONVERTER

The stereo DACs of the PCM1740 use a multi-level delta-

sigma architecture. Based upon a 3rd-order noise shaper and

a 5-level amplitude quantizer, this section converts the 8x

oversampled, 18-bit input data from the interpolation filter

to a 5-level delta-sigma format. A block diagram of the

multi-level delta-sigma modulator is shown in Figure 1.

This architecture has the advantage of improved stability

and increased tolerance to clock jitter when compared to the

one-bit (2-level) delta-sigma DACs.

The combined oversampling rate of the delta-sigma modu-

lator and the 8x interpolation filter is 48fS for a 384fS system

clock, and 64fS for a 256fS system clock. The theoretical

quantization noise performance for the 5-level delta-sigma

modulator is shown in Figure 2.

The output of the delta-sigma modulator is low-pass filtered

and buffered by an on-chip output amplifier. For best

performance, an external low-pass filter is recommended.

Refer to the Applications Information section of this data

sheet for details regarding DAC output filter recommenda-

tions.

The PCM1740 includes two analog outputs, VOUTL (pin 14)

and VOUTR (pin 11), corresponding to the left and right audio

outputs. The full-scale output amplitude is 0.62 × VCC, or

3.1VPP with a +5V supply and an AC-coupled load of 5kΩ or

greater. The analog outputs are centered about the DC com-

mon-mode voltage, which is typically VCC/2.

The DC common-mode voltage is made available at the

VCOM output (pin 15). This is an unbuffered output, prima-

Out

48fS (384fS)

64fS (256fS)

In 8fS

18-Bit

+++

5-level Quantizer

–

+Z–1

–

+Z–1

FIGURE 2. Quantization Noise Spectrum.

rily used for decoupling purposes. See the Applications

Information section of this data sheet for more information

regarding the use of the VCOM output for biasing external

circuitry.

VOLTAGE CONTROLLED CRYSTAL OSCILLATOR

(VCXO)

The PCM1740 includes an on-chip voltage-controlled crys-

tal oscillator, or VCXO, which is used to generate the

27MHz master clock required by most digital broadcast and

MPEG-2 decoding applications.

FIGURE 1. 5-Level ∆Σ Modulator Block Diagram.

PCM1740

8SBAS128B

www.ti.com

The 27MHz clock is available at the MCKO output (pin 5).

The VCXO output frequency can be precisely tuned using a

control voltage at the XTUN input (pin 3). The tuning range

is 27MHz ±150ppm typical for a 0V to +3V control voltage

range. Figure 3 shows the VCXO equivalent circuit, while

Figure 4 shows the typical tuning curve.

At power up, the VCXO requires 5ms start up time. The

VCXO also exhibits a 10µs settling time in response to

changes in the XTUN control voltage. VCXO operation and

the MCKO output are not affected by the power on or

external reset functions, continuing to operate during the

initialization sequence.

Crystal Selection

The VCXO connects to an external 27MHz crystal via XT1

(pin 1) and XT2 (pin 24). The crystal should be AT-cut,

fundamental mode with ±30ppm accuracy and less than 50Ω

motional resistance. Crystal shunt capacitance should be 3pF

maximum, while load capacitance should be less than 7pF.

Miniature lead type or surface-mount devices are recom-

mended. External load capacitors are not needed, since they

are provided on-chip. The crystal should be placed as close as

possible to the XT1 and XT2 pins to reduce effects of parasitic

capacitance and land resistance.

PROGRAMMABLE PHASE LOCKED LOOP (PLL)

The PCM1740 includes an on-chip PLL for generating a 256fS

or 384fS audio system clock from the 27MHz VCXO output.

A block diagram of the PLL section is shown in Figure 5. The

PLL output clock is used by the digital filter and delta-sigma

modulator circuitry, and is made available at the SCKO output

(pin 21) for use with additional audio converters and signal

processors.

Tuning Voltage (V)

VCXO Output Frequency (MHz)

27.005

27.004

27.003

27.002

27.001

27.000

26.999

26.998

26.997

26.996

26.9950.0 0.5 1.51.0 2.0 2.5 3.0 3.5 4.0

27MHz

Crystal

XTUN

0V to +3V

VCXO MCKO

27MHz ±150ppm

SCKO

256/384f

Frequency

Selection

ROM

Phase

Detector

and

Loop Filter

PLL

N Counter

Frequency Selection

Control Register 3

VCO

M Counter

FIGURE 3. VCXO Equivalent Circuit.

FIGURE 4. VCXO Output Frequency (MCKO) versus

Tuning Voltage (XTUN).

XT1

27MHz

Crystal

27MHz

Tuned Clock

Voltage

Range

0 to 3V

XTUN

XT2

FIGURE 5. PLL Block Diagram.

PCM1740 9

SBAS128B www.ti.com

The PLL can generate one of nine pre-programmed system

clock rates for either 256fS or 384fS output. The PLL output

and sampling frequencies are programmed using Control

and the corresponding PLL output clock rates. The reset

default condition for the PLL is fS = 44.1kHz with SCKO =

384fS, or 16.9344MHz.

RESET OPERATION

POWER-ON RESET

The PCM1740 includes power-on reset circuitry for start up

initialization. The initialization sequence starts when VDD

exceeds 2.2V (typical). The initialization sequence requires

1024 PLL output (or SCKO) clock cycles for completion.

During initialization, both VOUTL and VOUTR are forced to

VCC/2. Figure 6 shows the power-on reset timing, while

Table II shows the reset default settings for user-program-

mable functions. The user should not attempt to write

control registers via the I2C-Bus interface during the initial-

ization sequence.

EXTERNAL RESET

The PCM1740 includes an external reset input, RST (pin

10). This input may be used to force an initialization se-

quence. As shown in Figure 7, the RST pin must be held low

for a minimum of 20ns. The initialization sequence will then

start on the rising edge of RST. Initialization requires 1024

PLL output (or SCKO) clock cycles for completion. During

initialization, both VOUTL and VOUTR are forced to VCC/2.

Table II shows the reset default settings for user-program-

mable functions. The user should not attempt to write

control registers via the I2C-Bus interface during the initial-

ization sequence.

SAMPLING INTERNAL SYSTEM INTERNAL SYSTEM

FREQUENCY (LRCK) Clock - 256fSClock - 384fS

16kHz Half 4.096MHz 6.144MHz

32kHz Normal 8.192MHz 12.288MHz

64kHz Double 16.384MHz 24.576MHz

22.05kHz Half 5.6448MHz 8.4672MHz

44.1kHz Normal 11.2896MHz 16.9344MHz

88.2kHz Double 22.5792MHz 33.8688MHz

24kHz Half 6.144MHz 9.216MHz

48kHz Normal 12.288MHz 18.432MHz

96kHz Double 24.576MHz 36.864MHz

TABLE I. PLL Sampling and System Clock Frequencies.

1024 System Clock Periods

Reset Reset Removal

2.4V

2.2V

2.0V

Internal Reset

System Clock

(SCKO)

1024 System Clock Periods

Reset Reset Removal

System Clock

(SCKO)

Internal Reset

RST tRST

tRST tRST ≥ 20ns

FIGURE 6. Power-On Reset Operation.

FIGURE 7. External Reset Operation.

At power-up, the PLL requires 30ms start up time for

stabilization. The PLL also exhibits a settling time of 20ms

in response to changes in sampling frequency selection.

The PLL output continues to operate during power-on or

external reset sequences, with the sampling frequency set to

fS = 44.1kHz and SCKO = 384fS.

PCM1740

10 SBAS128B

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LRCK

BCK

DATA

SCKO

Frame Sync

Serial Bit Clock

Serial Data Output

Audio Clock

PCM1740Audio DSP/Decoder

14 15 16 123 14 15

1/fs

L_ch R_ch

MSB LSB

LRCIN (pin 4)

(a) Standard Right - Justified Format

(b) I2S Format

BCKIN (pin 6)

AUDIO DATA WORD = 16-BIT

DIN (pin 5) 123 14 15

MSB LSB

18 19 20 1 2 3 18 19

MSB LSB

AUDIO DATA WORD = 20-BIT

DIN (pin 5) 123 18 19

MSB LSB

23 24 1 2 3 22 23

MSB LSB

AUDIO DATA WORD = 24-BIT

DIN (pin 5) 123 22 23

MSB LSB

123 14 15

1/fs

L_ch R_ch

MSB LSB

LRCIN (pin 4)

BCKIN (pin 6)

AUDIO DATA WORD = 16-BIT

DIN (pin 5) 123 14 15

MSB LSB

123 18 19

MSB LSB

AUDIO DATA WORD = 20-BIT

DIN (pin 5) 123 18 19

MSB LSB

123 22 23

MSB LSB

AUDIO DATA WORD = 24-BIT

DIN (pin 5) 123 22 23

MSB LSB

LRCK and BCK Rates

The LRCK input is operated at the sampling frequency, fS.

The BCK input is operated at 32, 48, or 64 times the

sampling frequency. Both LRCK and BCK must be syn-

chronous with the SCKO output for proper operation.

Data Formats

The PCM1740 supports two audio interface formats: Standard

and I2S. These formats are shown in Figure 9. The audio data

word length for the Left and Right channels may be 16-, 20-,

or 24-bits. The audio data word length and format are pro-

grammed using Control Registers 2 and 3. The reset default

condition is Standard format with 16-bit audio data.

Timing Requirements

Figure 10 shows the audio interface timing requirements.

ZERO FLAG OUTPUT

The PCM1740 includes a zero flag output, ZERO (pin 16).

This is an open-drain output, and a 10kΩ pull-up resistor

connected to VDD is recommended when using the ZERO

flag as a logic output.

The PCM1740 includes an infinite zero detection function

that monitors the audio data at the DATA input (pin 18). If

the audio data for both the left and right channels is all zeros

for 65,536 continuous BCK clock cycles, the zero flag will

be activated, turning on a MOSFET switch and connecting

the ZERO pin to ground. This provides an active low output

that may be used to control an external mute circuit, or as a

logic indicator for an audio DSP/decoder or microprocessor.

AUDIO SERIAL INTERFACE

The PCM1740 includes a three-wire serial audio interface.

This includes LRCK (pin 19), BCK (pin 17), and DATA

(pin 18). The LRCK input is the audio left/right clock, which

is used as a latch signal for the interface. The BCK input is

used to clock audio data into the serial port. The DATA

input carries multiplexed data for the left and right audio

channels. Audio data must be Two’s Complement, MSB

first formatted. Figure 8 shows the typical connection be-

tween the PCM1740 audio serial interface and an audio DSP

or decoder.

FIGURE 8. Interfacing the PCM1740 to an Audio DSP.

FIGURE 9. Audio Interface Formats.

PCM1740 11

SBAS128B www.ti.com

Loss of Synchronization

Ideally, LRCK and BCK will be derived from the SCKO

output, ensuring synchronous operation. For other cases, the

PCM1740 includes circuitry to detect loss of synchroniza-

tion between the LRCK and the system clock, SCKO. A loss

of synchronization condition is detected when the phase

relationship between SCKO and LRCK exceeds ±6 BCK

cycles during one sample period, or 1/fS. If a loss of

synchronization condition is detected, the DAC operation

will halt within one sample period and the analog outputs

will be forced to VCC/2 until re-synchronization between

LRCK and SCKO is completed. Figure 11 shows the state of

the analog outputs given a loss of synchronization event.

During the undefined states, as well as transitions between

normal and undefined states, the analog outputs may gener-

ate audible noise.

USER PROGRAMMABLE FUNCTIONS

The PCM1740 includes a number of programmable func-

tions, which are configured using five control registers.

These registers are accessed using the I2C-Bus interface.

This section describes the control registers, while the

I2C-Bus interface is described in a later section. Table II lists

the available functions and their corresponding reset default

condition.

The control register map is shown in Table III. Sub-address

bits B8 through B10 are used to specify the register that is

being written. All reserved bits, shown as “res”, must be set

to ‘0’.

The following pages provide detailed descriptions of the five

control registers and their associated functions. All reserved

bits, shown as “res”, must be set to ‘0’.

FIGURE 10. Audio Interface Timing.

FIGURE 11. Loss of Synchronization and Analog Output State.

SUB ADDRESS BYTE DATA BYTE

TABLE III. Control Register Map.

FUNCTION MODE BY DEFAULT

Audio Data Format Select:

Standard Format/I2S Format Standard Format

Audio Data Word Select:

16-Bit/20-Bit/24-Bit 16-Bit

Polarity of LR-clock Selection Left/Right = HIGH/LOW

De-emphasis Control:

OFF, 32kHz, 44.1kHz, 48kHz OFF

Soft Mute Control OFF

Attenuation Data for Left-channel 0dB

Attenuation Data for Right-channel 0dB

Attenuation Data Mode Control Left-channel, Right-channel Individually

Analog Output Mode Select Stereo Mode

Infinity Zero Detect Mute Control OFF

DACs Operation Control ON

System Clock Select: 256fS/384fS384fS

Sampling Frequency Select:

32kHz Group, 44.1kHz Group, 48kHz Group 44.1kHz Group

Sampling Frequency Multiplier:

Normal/Double/Half Normal, x1

TABLE II. User-Programmable Functions.

Normal Normal

Synchronous Asynchronous

within

1/f

Synchronous

Undefined Data

Undefined

Data

COM

(= 0.5 V

)

22.2/f

State of

Synchronization

OUT

LRCKIN

BCKIN

DIN

1.4V

BCH

BCL

BCKIN Pulse Cycle Time

BCKIN Pulse Width High

BCKIN Pulse Width Low

BCKIN Rising Edge to LRCIN Edge

LRCIN Edge to BCKIN Rising Edge

DIN Set-up Time

DIN Hold Time

: t

BCY

: t

BCH

: t

BCL

: t

: 100ns (min)

: 50ns (min)

: 30ns (min)

BCY

PCM1740

12 SBAS128B

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B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Left Channel Attenuation Data

Default: AL[7:0] = FFHEX

Register 0 is used to set the digital attenuation level for the Left Channel. If the ATC bit in Register 3 is set to ‘1’, then these

data are also used to control the Right Channel attenuation. The attenuation level is defined by the following relationships:

Attenuation (dB) = 20 x log (AL[7:0]DEC ÷ 256), when AL[7:0] = 01HEX (1DEC) through FEHEX (254DEC)

Attenuation (dB) = –∞ (or Mute), when AL[7:0] = 00HEX

Attenuation (dB) = 0dB, when AL[7:0] = FFHEX

The Attenuation Load bit, LD, in Register 4 must be set to ‘1’ in order to update attenuation settings.

If LD is set to ‘0’, the attenuation remains at the previously programmed level, ignoring the new data until LD is set to ‘1’.

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Right Channel Attenuation Data

Default: AR[7:0] = FFHEX

Register 1 is used to set the digital attenuation level for the Right Channel. If the ATC bit in Register 3 is set to ‘1’, then the

Left Channel attenuation data in Register 1 are used to control the Right Channel attenuation. The attenuation level is defined

by the following relationships:

Attenuation (dB) = 20 x log (AR[7:0]DEC ÷ 256), when AR[7:0] = 01HEX (1DEC) through FEHEX (254DEC)

Attenuation (dB) = –∞ (or Mute), when AR[7:0] = 00HEX

Attenuation (dB) = 0dB, when AR[7:0] = FFHEX

The Attenuation Load bit, LD, in Register 4 must be set to ‘1’ in order to update attenuation settings.

If LD is set to ‘0’, the attenuation remains at the previously programmed level, ignoring the new data until LD is set to ‘1’.

MUT Soft Mute Control

The MUT bit controls the soft mute function. Soft mute changes the digital attenuation level for both the Left

and Right channels, stepping from the currently programmed value to infinite attenuation one step per sample

period, or 1/fS. This provides a quiet muting of the outputs without audible noise.

MUT = 0 Soft Mute Disabled (default)

MUT = 1 Soft Mute Enabled

DEM Digital De-Emphasis

The DEM bit controls the digital de-emphasis function, which is valid only for 32kHz, 44.1kHz,

and 48kHz sampling frequencies. The de-emphasis plots are shown in the Typical Characteristics section of this

data sheet.

DEM = 0 De-Emphasis OFF (default)

DEM = 1 De-Emphasis ON

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

PCM1740 13

SBAS128B www.ti.com

IW0 Audio Data Word Length

IW1

The IW0 and IW1 bits are used to select the data word length for the audio serial interface.

The audio data format is selected using the IIS bit in Register 3.

IW1 IW0 Word Length

0 0 16-bits (default)

0 1 20-bits

1 0 24-bits

1 1 Reserved

PL[3:0] Analog Output Mode Select

Bits PL[3:0] are used to set the output mode for the analog outputs. Refer to the table below.

PL3 PL2 PL1 PL0 VOUTLV

OUTR Notes

0 0 0 0 Mute Mute Mute

0 0 0 1 Left Mute

0010Right Mute

0 0 1 1 (L+R)/2 Mute

0 1 0 0 Mute Left

0 1 0 1 Left Left

0110Right Left Reverse

0 1 1 1 (L+R)/2 Left

1 0 0 0 Mute Right

1 0 0 1 Left Right Stereo (default)

1010Right Right

1 0 1 1 (L+R)/2 Right

1 1 0 0 Mute (L+R)/2

1 1 0 1 Left (L+R)/2

1110Right (L+R)/2

1 1 1 1 (L+R)/2 (L+R)/2 Mono

IIS Audio Data Format

The IIS bit is used to select the audio data format, either Standard Right-Justified or I2S.

IIS = 0 Standard Right Justified (default)

IIS = 1 I2S

LRP LRCK Polarity

The LRP bit selects the polarity of left/right clock input (LRCK) when using the Standard Right-Justified audio

data format. This bit has no effect when using the I2S audio data format.

LRP = 0 Left Channel when LRCK = High; Right Channel when LRCK = Low (default)

LRP = 1 Left Channel when LRCK = Low; Right Channel when LRCK = High

ATC Attenuation Mode Control

The ATC bit is used to select independent or common attenuation data for the Left and Right channels.

ATC = 0 Independent: Left Channel uses Register 0 and Right Channel uses Register 1 (default)

ATC = 1 Common: Left and Right Channels both use Register 0

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

PCM1740

14 SBAS128B

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SYS Audio System Clock (or SCKO)

The SYS bit is used to select the system clock (or SCKO) frequency, either 256fS or 384fS.

SYS = 0 384fS (default)

SYS = 1 256fS

DSR0 Sampling Frequency Multiplier

DSR1

The DSR0 and DSR1 bits are used to select the multiplier used in conjunction with the SF0 and SF1 bits.

DSR1 DSR0 Multiplier

0 0 Normal, x1 (default)

0 1 Double, x2

1 0 Half, x 1/ 2

1 1 Reserved

SF0 Sampling Frequency Select

SF1

The SF0 and SF1 bits are used to select the sampling frequency group (32kHz, 44.1kHz, or 48kHz). Frequency

selection must be made with an interval time greater than 20µs. The DSR0 and DSR1 bits, described previously,

are used to select the multiplier.

SF1 SF0 Sampling Frequency Group

0 0 44.1kHz Group ( 22.05kHz, 44.1kHz, or 88.2kHz) (default)

0 1 48 kHz Group (24kHz, 48kHz, or 96kHz)

1 0 32 kHz Group (16kHz, 32kHz, or 64kHz)

1 1 Reserved

LD Attenuation Data Load Control

The LD bit is used to simultaneously set the Left and Right digital attenuation data. When LD is set to ‘1’, the

digital attenuation data given by Registers 0 and 1 are loaded for the Left and Right channels. When LD is set

to ‘0’, updates to Registers 0 and 1 are ignored, and the attenuation settings remain as previously programmed

until LD is set to ‘1’.

LD = 0 Disabled

LD = 1 Enabled: Left and Right Attenuation Data Updated Simultaneously

IZD Infinite Zero Detect Mute

The IZD bit is used to enable/disable the infinite zero detect mute function. The PCM1740 includes infinite zero

detection logic that monitors the audio data at the DATA input (pin 18). If the audio data for both the Left and

Right channels are all zeros for 65,536 continuous BCK clock cycles, the zero flag will be activated and output

amplifier will be disconnected from the output of the delta-sigma modulator. The output amplifier input is

switched to the DC common-mode voltage. This forces VOUTL and VOUTR to VCC/2. The ZERO output flag (pin

16) is not affected by the setting of this bit.

IZD = 0 Disabled (default)

IZD = 1 Enabled

OPE DAC Operation Control

The OPE bit is used to enable/disable the operation of the DACs. When enabled, the DAC outputs are connected

to the output amplifier for normal operation. When disabled, the output amplifier is disconnected from the DAC

output and switched to the DC common-mode voltage. This forces VOUTL and VOUTR to VCC/2.

OPE = 0 Enabled: Normal Operation(default)

OPE = 1 Disabled: Outputs forced to VCC/2

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

PCM1740 15

SBAS128B www.ti.com

I2C-BUS INTERFACE DESCRIPTION

The PCM1740 includes an I2C-Bus interface for writing the

internal control registers. This provides an industry standard

method for interfacing a host CPU control port to the

PCM1740. The PCM1740 operates as a Slave receiver on

the bus, and supports data transfer rates up to 100 kilobits-

per-second (kbps).

The I2C-Bus interface is comprised of four signals: SDA

(pin 9), SCL (pin 8), AD0 (pin 6), and AD1 (pin 7). The SCL

input is the serial data clock, while SDA is the serial data

input. SDA carries start/stop, slave address, sub-address (or

AD0 and AD1 inputs form the lower two bits of the slave

address.

Slave Address

The PCM1740 Slave address consists of seven bits, as shown

in Figure 12. The five most significant bits are fixed, while the

two least significant bits, named A0 and A1, are defined by the

logic levels present at the AD0 and AD1 input pins. This

allows four PCM1740s to reside on the same I2C-Bus.

Bus Operation

Figure 13 shows the typical configuration of the PCM1740 on

the I2C-Bus. The Master transmitter or transmitter/receiver is

typically a microcontroller, or an audio DSP/decoder. The

Master device controls the data transfers on the bus. The

PCM1740 operates as a Slave receiver, and accepts data from

the Master when it is properly addressed. The data transfer

may be comprised of an unlimited number of bytes, or 8-bit

data words. Figure 14 shows the message transfer protocol.

For normal bit transfer on the bus, data on SDA must

be static while SCL is High. Data on SDA may change

High / Low states when SCL is Low. The exception to this

rule is the Start and Stop conditions.

The Start condition is defined by a High-to-Low transition on

SDA while SCL is High, and is denoted with an ‘S’ in Figure

12. The Stop condition is defined by a Low-to-High transition

on SDA while SCL is High, and is denoted with a ‘P’ in Figure

12. The Start and Stop conditions are always generated by the

Master. All data transfers from Master to Slave begin with a

Start condition and end with a Stop condition. The bus is

considered to be busy after the Start condition, and becomes

free some time after the Stop condition.

Master

Transmitter/

Receiver

SCL

SDA

Slave

Receiver

(PCM1740)

Slave

Transmitter/

Receiver

Master

Transmitter/

Receiver

SDA

SCL

Start

Condition Start

Condition StopSlave

Address Slave

Address

R/W R/WACK ACKACKData

1-7 1-78 89 9981-7

NOTES: (1) Clock LOW (min) = 4.7µs; clock HIGH (min) = 4µs.

(2) The dashed line is the acknowledgement of the receiver.

(3) Mark-to space ratio = 1:1 (LOW-to-HIGH).

(4) Maximum number of bytes is unrestriced.

(5) Premature termination of transfer is allowed by generation of STOP condition.

(6) Acknowledge clock bit must be provided by master.

FIGURE 12. Control Data Format.

FIGURE 13. Typical I2C-Bus Configuration.

FIGURE 14. I2C Bus Data Transfer.

Slave Address

1A1A0S10 0

MSB R/W

AB12 B11 B10B15 B14 B13 B09 B08 AB07B06 B02 B01B00B05 B04 B03

Internal Strobe for

Data Latching

Acknowledge

from

Slave

Acknowledge

from

Slave

Acknowledge

from

Slave

Start

from

Master

Stop

from

Master

Sub Address Byte Data Byte

PCM1740

16 SBAS128B

www.ti.com

Data transfer begins with a Start condition, and is immedi-

ately followed by the Slave address and Read/Write bit. The

Read / Write bit is set to ‘0’ for the PCM1740, in order to

write data to the control register specified by the sub-

address. This is followed by an acknowledgment from the

PCM1740, the sub-address (that is, the control register

address), another acknowledgment from the PCM1740, the

control register data, and another acknowledgment from the

PCM1740. What happens after this depends on if the user

wants to continue writing additional control registers, or if

they want to terminate the data transfer. If the user wants to

continue, the acknowledgment is followed by a Start condi-

tion for the next write sequence. If the user decides to

terminate the data transfer, then a Stop condition is gener-

ated by the Master.

The I2C-Bus specification defines timing requirements for

devices connected to the bus. Timing requirements for the

PCM1740 are shown in Figure 15.

Reference

For additional information regarding the I2C-Bus, please

refer to the I2C-Bus Specification available online from

NXP Semiconductors.

FIGURE 15. I2C Bus Timing.

SDA

SCL

S: START condition

Sr: repeated START condition

P: STOP condition

HD; STA

SSr P S

HD; DAT

HIGH

SU; STA

SU; STO

HD; STA

LOW

SU, DAT

BUF

SYMBOL DESCRIPTION MIN TYP MAX UNITS

fSCL SCL Clock Frequency 100 kHz

tHD; STA Hold time (repeated) START condition, 4.0 µs

after this period, the first clock pulse is

generated

tLOW LOW period of the SCL clock 4.7 µs

tHIGH HIGH period of the SCL clock 4.0 µs

tSU:STA

Set-up time for a repeated START condition

4.7 µs

tHD;DAT Data hold time for I2C-BUS devices 0 3.45(2) µs

tSU;DAT Data set-up time 250 ns

tRRise time of both SDA and SCL signals 1000 ns

tFFall time of both SDA and SCL signals 300 ns

tSU;STO Set-up time for STOP condition 4.0 µs

tBUF

Bus free time between a STOP and START

4.7 µs

condition

CBCapacitive load for each bus line 400 pF

VNL Noise margin at the LOW level for each 0.1 VDD V

connected device (including hysteresis)

VNH Noise margin at the HIGH level for each 0.2 VDD V

connected device (including hysteresis)

PCM1740 17

SBAS128B www.ti.com

FIGURE 16. Basic Connection Diagram.

XT1

PGND

XTUN

VPP

MCKO

AD0

AD1

SCL

SDA

RST

VOUTR

AGND

XT2

DGND

VDD

SCKO

RSV

LRCK

DATA

BCK

ZERO

VCOM

VOUTL

VCC

I2C BUS

and Reset

Control

from µP

VCXO

Control

Voltage

(0V to +3V)

27MHz

Master Clock

Low Pass

Filter(2)

Right Channel

Output

From Audio

Decoder

Serial

Interface

256/384fS

to AudioDecoder

and Data Converters

Buffer(1)

10kΩ

Zero Flag

+C4

NOTES: (1) Use buffer when driving multiple nodes.

(2) See applications information section for filter

recommendations.

C1+

PCM1740

27MHz Crystal

C1 to C6 = 1µF to 10µF Capacitors

( Aluminum Electrolytic or tantalum)

Low Pass

Filter(2)

Left Channel

Output

Analog

Ground

+5V

APPLICATIONS INFORMATION

BASIC CONNECTION DIAGRAM

A basic connection diagram is shown in Figure 16. Power

supply and reference decoupling capacitors should be located

as close as possible to the PCM1740 package. The 27MHz

crystal should also be located as close as possible to the

package, to reduce the effects of parasitic capacitance on

VCXO operation.

A single +5V supply is recommended, to avoid issues with

power-supply sequencing and SCR latch-up. It is recom-

mended that this supply be separate from the system digital

power supply. In cases where this is not practical, an

Audio

Serial

I/F

and

REGs

VCXO

AD1

AD0

SCL

SDA

I2C-bus GPIO

XTUN

XTI

XTO

RST

27MHz

Crystal

Interpolation

Filter

and

Programmable

Functions DAC

(R)

Counter N

OUT

COM

ZERO

SCKO

MCKO

To Audio Decoder

and Data Converters

To Other Devices

OUT

Counter M

Power Supply

Reset

BCIN

LRCIN

DIN

AGND DGNDV

PGND

DAC

(L) Low-Pass

Filter

and Output

Amp

Audio

Decoder

MPEG

System Controller

27MHz Reference

Generated by

Receive Counter

Line-Out_L

Line-Out_R

LPFPD VCO

Low-Pass

Filter

and

Analog

Mute

LPF VCXO Control Voltage

Phase

Detec.

FIGURE 17. Typical Application Diagram.

inductor or ferrite bead should be placed in series with the

+5V supply connection to reduce or eliminate high-fre-

quency noise on the supply line.

In cases where overshoot or ringing is present on the LRCK

or BCK signals, a series resistance of 25Ω to 100Ω should

be added. The resistor forms a simple RC filter with the

device input and printed circuit board (PCB) parasitic ca-

pacitance, dampening the overshoot and ringing effects,

while reducing high-frequency noise emissions.

TYPICAL APPLICATION DIAGRAM

Figure 17 shows the PCM1740 being used as part of the

audio sub-system in a set-top box application.

PCM1740

18 SBAS128B

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The VTUN control voltage is generated by the MPEG-2

controller, which compares the MCKO output clock from

the PCM1740 with the clock count received from the trans-

mitter. VTUN is adjusted to retain clock synchronization

between the transmitted and received signals. The SCKO

output is used as the audio master clock for the audio

decoder and additional data converters.

VCOM Output

The unbuffered DC common-mode voltage output, VCOM

(pin 15), is brought out mainly for de-coupling purposes.

VCOM is nominally biased to VCC/ 2. The VCOM output may

be used to bias external circuits, but it must be connected to

a high-impedance node or buffered using a voltage follower.

Figure 18 shows examples of the proper use of the VCOM

output for external biasing applications.

DAC OUTPUT FILTERING

Delta-Sigma DACs utilize noise shaping techniques to im-

prove in-band signal-to-noise (SNR) performance at the

expense of generating increased out of band noise above the

Nyquist frequency, or fS/2. The out-of-band noise must be

low-pass filtered in order to provide optimal converter

performance. This is accomplished by a combination of on-

chip and external low-pass filtering.

The PCM1740 includes an on-chip low-pass filter as part of

the output amplifier stage. The frequency response for the

filter is shown in the Typical Characteristics section

of this data sheet. The –3dB cutoff frequency is fixed at

100kHz.

Figure 19 shows the recommended external low-pass active

filter circuits for dual and single-supply applications. These

circuits are second-order Butterworth filters using the Mul-

tiple Feedback (MFB) circuit arrangement. Both filters have

a cutoff frequency of 30kHz. Figure 19(a) is a dual-supply

filter with a gain of 1.85 (for a standard 2 VRMS line output

level). Figure 19(b) is a single-supply filter with a gain of 1.

Values for the filter components may be calculated using the

FilterPro program, available from the TI web site

(www.ti.com) and local sales offices. For more information

regarding MFB active filter design and the FilterPro pro-

gram, refer to TI Application Report SBFA001.

Since the overall system performance is defined primarily

by the quality of the DACs and their associated analog

output circuitry, op amps designed specifically for audio

applications are recommended for the active filters. TI’s

OPA2134, OPA2353, and OPA2343 dual op amps are ideal

for use with the PCM1740.

FIGURE 18. Using VCOM To Bias External Circuitry.

OUT

Non-Polarized

1µF

PCM1740

1-10µF

COM

PCM1740

OPA337

OPA343 +1-10µF

Use voltage follower

to buffer V

COM

To Bias

Nodes

COM

(a) Biasing an External Active Filter Stage (b) Using a Buffer to Provide Bias for Multiple or

Low Input Impedance Nodes

PCM1740 19

SBAS128B www.ti.com

3.16kΩ

5.76kΩ

10kΩ

220pF

2200pF

1µF

10µF

1µF

10µF

(a) Dual-Supply Filter Circuit

Filtered

Output

OUT

R/L

PCM1740 +V

–V

OPA134 Series

3.83kΩ

15kΩ

220pF

2200pF

(b) Single-Supply Filter Circuit

4.7µF

to 10µF

Filtered

Output

OUT

R/L

COM

PCM1740

1µF

10µF

OPA343/353 Series

FIGURE 19. Recommended Output Filter Circuits.

PCM1740

20 SBAS128B

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DATE REVISION PAGE SECTION DESCRIPTION

—Entire Document Updated format.

2 Electrical Characteristics Changed Low Level Output Voltage VOH to VOL (typo)

14 SF0, SF1 Added sentence regarding interval time must be greater than 20µs.

Figure 12 Changed Figure 12.

Figure 14 Changed Figure 14.

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

5/07 B

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

PCM1740E ACTIVE SSOP DB 24 58 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PCM1740E-2/2K OBSOLETE SSOP DB 24 TBD Call TI Call TI

PCM1740E-2/2KG4 OBSOLETE SSOP DB 24 TBD Call TI Call TI

PCM1740E/2K ACTIVE SSOP DB 24 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PCM1740E/2KG4 ACTIVE SSOP DB 24 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PCM1740EG4 ACTIVE SSOP DB 24 58 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 16-Jun-2009

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

PCM1740E/2K SSOP DB 24 2000 330.0 17.4 8.5 8.6 2.4 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jun-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

PCM1740E/2K SSOP DB 24 2000 336.6 336.6 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jun-2008

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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