MCB1114 - ARM - Datasheet.Directory

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1. General description

The LPC1111/12/13/14 are a ARM Cortex-M0 based, low-cost 32-bit MCU family,

designed for 8/16-bit micr ocontroller applications, of fering performance, low power, simple

instruction set and memory addressing together with reduced code size compared to

existing 8/16-bit architectures.

The LPC1111/12/13/14 operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC1111/12/13/14 includes up to 32 kB of flash

memory, up to 8 kB of data memory, one Fast-mode Plus I2C-bu s in te r fac e, one

RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose

timers, a 10-bit ADC, and up to 42 general purpose I/O pins.

2. Features

ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), or 8 kB (LPC1111) on-chip flash

programming memory.

8 kB, 4 kB, or 2 kB SRAM.

In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

Serial interfaces:

UART with fractional baud rate generation, internal FIFO, and RS-485 support.

Two SPI controllers with SSP features and with FIFO and multi-protocol

capabilities (second SPI on LQFP48 and PLCC44 packages only).

I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a

data rate of 1 Mbit/s with multiple address recognition and monitor mode.

Other periph er als :

Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors.

Four general purpose timers/counters with a total of four capture inputs and 13

match outpu ts.

Programmable WatchDog Timer (WDT).

System tick timer.

Serial Wire Debug.

High-current output driver (20 mA) on one pin.

High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.

LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash and

8 kB SRAM

Rev. 00.11 — 13 November 2009 Objective data sheet

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NXP Semiconductors LPC1111/12/13/14

Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, and Deep power-down modes.

Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

Single 3.3 V power supply (1.8 V to 3.6 V).

10-bit ADC with input multiplexing among 8 pins.

GPIO pins can be used as edge and level sensitive interrupt sources.

Clock output function with divider that can reflect the system oscillator clock, IRC

clock, CPU clock, and the Watchdog clock.

Processor wake-up fro m Deep-sleep mode via a dedicated star t logic using up to 13 of

the functional pins.

Brownout detect with four separate thresholds for interrupt and one threshold for

forced reset.

Power-On Reset (POR).

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as

a system clock.

PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the main oscillator, the internal RC oscillator,

or the watchdog oscillator.

Available as 48-pin LQFP package, 33-pin HVQFN package, and 44-pin PLCC

package.

3. Applications

eMetering

Lighting

Industrial networking

Alarm systems

White goods

4. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

LPC1111FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 x 7 x 0.85 mm n/a

LPC1111FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 x 7 x 0.85 mm n/a

LPC1112FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 x 7 x 0.85 mm n/a

LPC1112FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 x 7 x 0.85 mm n/a

LPC1113FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 x 7 x 0.85 mm n/a

LPC1113FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 x 7 x 0.85 mm n/a

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NXP Semiconductors LPC1111/12/13/14

4.1 Ordering options

LPC1114FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 x 7 x 0.85 mm n/a

LPC1114FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no

leads; 33 terminals; body 7 x 7 x 0.85 mm n/a

LPC1113FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x

1.4 mm sot313-2

LPC1114FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x

1.4 mm sot313-2

LPC1114 FA44/301 PLCC44 PLCC44; plastic leaded chip carrier; 44 leads sot187-2

Table 1. Ordering information …continued

Type number Package

Name Description Version

Table 2. Ordering options

Type number Flash Total

SRAM UART

RS-485 I2C/

Fast+ SPI ADC

channels Package

LPC1111

LPC1111FHN33/101 8 kB 2 kB 1 1 1 8 HVQFN33

LPC1111FHN33/201 8 kB 4 kB 1 1 1 8 HVQFN33

LPC1112

LPC1112 FHN3 3/101 16 kB 2 kB 1 1 1 8 HVQFN33

LPC1112FHN33/201 16 kB 4 kB 1 1 1 8 HVQFN33

LPC1113

LPC1113FHN33/201 24 kB 4 kB 1 1 1 8 HVQFN33

LPC1113FHN33/301 24 kB 8 kB 1 1 1 8 HVQFN33

LPC1113 FBD48 /301 24 kB 8 kB 1 1 2 8 LQFP48

LPC1114

LPC1114FHN33/201 32 kB 4 kB 1 1 1 8 HVQFN33

LPC1114FHN33/301 32 kB 8 kB 1 1 1 8 HVQFN33

LPC1114 FBD48 /301 32 kB 8 kB 1 1 2 8 LQFP48

LPC1114FA44/301 32 kB 8 kB 1 1 2 8 PLCC44

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5. Block diagram

(1) LQFP48 and PLCC44 packages only.

Fig 1. LPC1111/12/13/14 block diagram

SRAM

2/4/8 kB

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

FLASH

8/16/24/32 kB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

XTALIN

XTALOUT RESET

clocks and

controls

SWD

LPC1111/12/13/14

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slave

slave slave

ROM

slave

AHB-LITE BUS

GPIO ports

PIO0/1/2/3

CLKOUT

IRC

POR

SPI0

10-bit ADC

UART

32-bit COUNTER/TIMER 0

I2C-BUS

WDT

IOCONFIG

CT32B0_MAT[3:0]

AD[7:0]

CT32B0_CAP0

SDA

SCL

RXD

TXD

DTR, DSR(1), CTS,

DCD(1), RI(1), RTS

SYSTEM CONTROL

PMU

32-bit COUNTER/TIMER 1

CT32B1_MAT[3:0]

CT32B1_CAP0

16-bit COUNTER/TIMER 1

CT16B1_MAT[1:0]

CT16B1_CAP0

16-bit COUNTER/TIMER 0

CT16B0_MAT[2:0]

CT16B0_CAP0

SCK0, SSEL0

MISO0, MOSI0

SCK1, SSEL1

MISO1, MOSI1

SPI1(1)

system bus

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6. Pinning information

6.1 Pinning

Fig 2. Pin configuration LQFP48 package

LPC1113FBD48/301

LPC1114FBD48/301

PIO2_6 PIO3_0/DTR

PIO2_0/DTR/SSEL1 TRST/PIO1_2/AD3/CT32B1_MAT1

RESET/PIO0_0 TDO/PIO1_1/AD2/CT32B1_MAT0

PIO0_1/CLKOUT/CT32B0_MAT2 TMS/PIO1_0/AD1/CT32B1_CAP0

VSSIO TDI/PIO0_11/AD0/CT32B0_MAT3

XTALIN PIO2_11/SCK0

XTALOUT PIO1_10/AD6/CT16B1_MAT1

VDD(IO) SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO1_8/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1

PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0

PIO2_7 PIO2_2/DCD/MISO1

PIO2_8 PIO2_10

PIO2_1/DSR/SCK1 PIO3_3/RI

PIO0_3 PIO1_7/TXD/CT32B0_MAT1

PIO0_4/SCL PIO1_6/RXD/CT32B0_MAT0

PIO0_5/SDA PIO1_5/RTS/CT32B0_CAP0

PIO1_9/CT16B1_MAT0 VDD(3V3)

PIO3_4 PIO3_2/DCD

PIO2_4 PIO1_11/AD7

PIO2_5 VSS

PIO3_5 PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO0_6/SCK0 SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO0_7/CTS

PIO2_9

PIO2_3/RI/MOSI1

PIO3_1/DSR

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Fig 3. Pin configuration PLCC44 package

LPC1114FA44/301

RESET/PIO0_0 TRST/PIO1_2/AD3/CT32B1_MAT1

PIO0_1/CLKOUT/CT32B0_MAT2 TDO/PIO1_1/AD2/CT32B1_MAT0

VSSIO TMS/PIO1_0/AD1/CT32B1_CAP0

XTALIN TDI/PIO0_11/AD0/CT32B0_MAT3

XTALOUT PIO2_11/SCK0

VDD(IO) PIO1_10/AD6/CT16B1_MAT1

PIO1_8/CT16B1_CAP0 SWCLK/PIO0_10/SCK0/CT16B0_MAT2

PIO0_2/SSEL0/CT16B0_CAP0 PIO0_9/MOSI0/CT16B0_MAT1

PIO2_7 PIO0_8/MISO0/CT16B0_MAT0

PIO2_8 PIO2_2/DCD/MISO1

PIO2_1/DSR/SCK1 PIO2_10

PIO0_3 PIO2_0/DTR/SSEL1

PIO0_4/SCL PIO2_6

PIO0_5/SDA PIO1_7/TXD/CT32B0_MAT1

PIO1_9/CT16B1_MAT0 PIO1_6/RXD/CT32B0_MAT0

PIO3_4 PIO1_5/RTS/CT32B0_CAP0

PIO2_4 VDD(3v3)

PIO2_5 PIO1_11/AD7

PIO3_5 VSS

PIO0_6/SCK0 PIO1_4/AD5/CT32B1_MAT3/WAKEUP

PIO0_7/CTS SWDIO/PIO1_3/AD4/CT32B1_MAT2

PIO2_9 PIO2_3/RI/MOSI1

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Fig 4. Pin configuration HVQFN 33 package

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Transparent top view

PIO0_8/MISO0/CT16B0_MAT0

PIO1_8/CT16B1_CAP0

PIO0_2/SSEL0/CT16B0_CAP0

PIO0_9/MOSI0/CT16B0_MAT1

VDD(IO) SWCLK/PIO0_10/SCK0/CT16B0_MAT2

XTALOUT PIO1_10/AD6/CT16B1_MAT1

XTALIN TDI/PIO0_11/AD0/CT32B0_MAT3

PIO0_1/CLKOUT/CT32B0_MAT2 TMS/PIO1_0/AD1/CT32B1_CAP0

RESET/PIO0_0 TDO/PIO1_1/AD2/CT32B1_MAT0

PIO2_0/DTR TRST/PIO1_2/AD3/CT32B1_MAT1

PIO0_3

PIO0_4/SCL

PIO0_5/SDA

PIO1_9/CT16B1_MAT0

PIO3_4

PIO3_5

PIO0_6/SCK0

PIO0_7/CTS

PIO1_7/TXD/CT32B0_MAT1

PIO1_6/RXD/CT32B0_MAT0

PIO1_5/RTS/CT32B0_CAP0

VDD(3V3)

PIO3_2

PIO1_11/AD7

PIO1_4/AD5/CT32B1_MAT3/WAKEUP

SWDIO/PIO1_3/AD4/CT32B1_MAT2

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

terminal 1

index area

33 VSS

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NXP Semiconductors LPC1111/12/13/14
6.2 Pin description
 
Table 3. LPC1113/14 pin description table (LQFP48 package)
Symbol Pin Type Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual di rection and function 
controls for each bit. The operation of port 0 pins depends on the function 
selected through the IOCONFIG register block.
RESET/PIO0_0 3 I RESET — External reset input: A LOW on this pin resets the device, 
causing I/O ports and peripherals to take on their default states, and 
processor execution to begin at address 0. 
I/O PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/
CT32B0_MAT2 4[1] I/O PIO0_1 — General purpose digital input/output pin. A LOW level on this pin 
during reset starts the ISP command handler.
OCLKOUT — Clockout pin.
OCT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 10[1] I/O PIO0_2 — General purpose digital input/output pin.
OSSEL0 — Slave Select for SPI0.
ICT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 14[1] I/O PIO0_3 — General purpose digital input/output pin. 
PIO0_4/SCL 15[2] I/O PIO0_4 — General purpose digital input/output pin.
I/O SCL — I2C-bus clock input/output. High-current sink only if I2C Fast-mode 
Plus is selected in the I/O configuration register.
PIO0_5/SDA 16[2] I/O PIO0_5 — General purpose digital input/output pin. 
I/O SDA — I2C-bus data input/output. High-current sink only if I2C Fast-mode 
Plus is selected in the I/O configuration register.
PIO0_6/SCK0 22[1] I/O PIO0_6 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
PIO0_7/CTS 23[1] I/O PIO0_7 — General purpose digital input/output pin (high-current output 
driver).
ICTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 27[1] I/O PIO0_8 — General purpose digital input/output pin.
I/O MISO0 — Master In Slave Out for SPI0.
OCT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 28[1] I/O PIO0_9 — General purpose digital input/output pin.
I/O MOSI0 — Master Out Slave In for SPI0.
OCT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/CT16B0_MAT2 29[1] ISWCLK — Serial wire clock and test clock TCK for JTAG interface.
I/O PIO0_10 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
OCT16B0_MAT2 — Match output 2 for 16-bit timer 0.
TDI/PIO0_11/
AD0/CT32B0_MAT3 32[3] ITDI — Test Data In for JTAG interface.
I/O PIO0_11 — General purpose digital input/output pin.
IAD0 — A/D converter, input 0.
OCT32B0_MAT3 — Match output 3 for 32-bit timer 0.

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PIO1_0 to PIO1_11 I/O Port 1 — Port 1 is a 12-bi t I/O port with individual direction and function 
controls for each bit. The operation of port 1 pins depends on the function 
selected through the IOCONFIG register block.
TMS/PIO1_0/
AD1/CT32B1_CAP0 33[3] ITMS — Test Mode Select for JTAG interface.
I/O PIO1_0 — General purpose digital input/output pin.
IAD1 — A/D converter, input 1.
ICT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
TDO/PIO1_1/
AD2/CT32B1_MAT0 34[3] OTDO — Test Data Out for JTAG interface.
I/O PIO1_1 — General purpose digital input/output pin.
IAD2 — A/D converter, input 2.
OCT32B1_MAT0 — Match output 0 for 32-bit timer 1.
TRST/PIO1_2/
AD3/CT32B1_MAT1 35[3] ITRST — Test Reset for JTAG interface.
I/O PIO1_2 — General purpose digital input/output pin.
IAD3 — A/D converter, input 3.
OCT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/AD4/
CT32B1_MAT2 39[3] I/O SWDIO — Serial wire debug input/output.
I/O PIO1_3 — General purpose digital input/output pin.
IAD4 — A/D converter, input 4.
OCT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/AD5/
CT32B1_MAT3/WAKEUP 40[3] I/O PIO1_4 — General purpose digital input/output pin.
IAD5 — A/D converter, input 5.
OCT32B1_MAT3 — Match output 3 for 32-bit timer 1.
IWAKEUP — Deep power-down mode wake-up pin.
PIO1_5/RTS/
CT32B0_CAP0 45[1] I/O PIO1_5 — General purpose digital input/output pin.
ORTS — Request To Send output for UART.
ICT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0 46[1] I/O PIO1_6 — General purpose digital input/output pin.
IRXD — Receiver input for UART.
OCT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 47[1] I/O PIO1_7 — General purpose digital input/output pin.
OTXD — Transmitter output for UART.
OCT32B0_MAT1 — Match output 1 for 32-bit timer 0. 
PIO1_8/CT16B1_CAP0 9[1] I/O PIO1_8 — General purpose digital input/output pin.
ICT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9/CT16B1_MAT0 17[1] I/O PIO1_9 — General purpose digital input/output pin.
OCT16B1_MAT0 — Match output 0 for 16-bit timer 1.
PIO1_10/AD6/
CT16B1_MAT1 30[3] I/O PIO1_10 — General purpose digital input/output pin.
IAD6 — A/D converter, input 6.
OCT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO1_11/AD7 42[3] I/O PIO1_11 — General purpose digital input/output pin.
IAD7 — A/D converter, input 7.
Table 3. LPC1113/14 pin description table (LQFP48 package) …continued
Symbol Pin Type Description

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PIO2_0 to PIO2_11 I/O Port 2 — Port 2 is a 12-bi t I/O port with individual direction and function 
controls for each bit. The operation of port 2 pins depends on the function 
selected through the IOCONFIG register block.
PIO2_0/DTR/SSEL1 2[1] I/O PIO2_0 — General purpose digital input/output pin.
ODTR — Data Terminal Ready output for UART.
OSSEL1 — Slave Select for SPI1.
PIO2_1/DSR/SCK1 13[1] I/O PIO2_1 — General purpose digital input/output pin.
IDSR — Data Set Ready input for UART.
I/O SCK1 — Serial clock for SPI1.
PIO2_2/DCD/MISO1 26[1] I/O PIO2_2 — General purpose digital input/output pin.
IDCD — Data Carrier Detect input for UART.
I/O MISO1 — Master In Slave Out for SPI1.
PIO2_3/RI/MOSI1 38[1] I/O PIO2_3 — General purpose digital input/output pin.
IRI — Ring Indicator input for UART.
I/O MOSI1 — Master Out Slave In for SPI1.
PIO2_4 19[1] I/O PIO2_4 — General purpose digital input/output pin.
PIO2_5 20[1] I/O PIO2_5 — General purpose digital input/output pin.
PIO2_6 1[1] I/O PIO2_6 — General purpose digital input/output pin.
PIO2_7 11[1] I/O PIO2_7 — General purpose digital input/output pin.
PIO2_8 12[1] I/O PIO2_8 — General purpose digital input/output pin.
PIO2_9 24[1] I/O PIO2_9 — General purpose digital input/output pin.
PIO2_10 25[1] I/O PIO2_10 — General purpose digital input/output pin.
PIO2_11/SCK0 31[1] I/O PIO2_11 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
PIO3_0 to PIO3_5 I/O Port 3 — Port 3 is a 12-bit I/O port with individual direction and function 
controls for each bit. The operation of port 3 pins depends on the function 
selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 
are not available.
PIO3_0/DTR 36[1] I/O PIO3_0 — General purpose digital input/output pin.
ODTR — Data Terminal Ready output for UART.
PIO3_1/DSR 37[1] I/O PIO3_1 — General purpose digital input/output pin.
IDSR — Data Set Ready input for UART.
PIO3_2/DCD 43[1] I/O PIO3_2 — General purpose digital input/output pin.
IDCD — Data Carrier Detect input for UART.
PIO3_3/RI 48[1] I/O PIO3_3 — General purpose digital input/output pin.
IRI — Ring Indicator input for UART.
PIO3_4 18[1] I/O PIO3_4 — General purpose digital input/output pin.
PIO3_5 21[1] I/O PIO3_5 — General purpose digital input/output pin.
VDD(IO) 8[4] I 3.3 V input/output supply voltage.
VDD(3V3) 44[4] I 3.3 V supply voltage to the internal regulator and the ADC. Also used as the 
ADC reference voltage.
VSSIO 5 I Ground.
Table 3. LPC1113/14 pin description table (LQFP48 package) …continued
Symbol Pin Type Description

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DRAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA
LPC1111_12_13_14_0 © NXP B.V . 2009. All rights reserved.
Objective data sheet Rev. 00.11 — 13 November 2009  11 of 53
NXP Semiconductors LPC1111/12/13/14
[1] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[2] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. 
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. 
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.
[4] Tie together VDD(3V3) and VDD(IO) externally. If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference 
between both supplies is smaller than or equal to 0.5 V.
[5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded 
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
 
XTALIN 6[5] I Input to the oscillator circuit and internal clock generator circuits. Input 
voltage must not exceed 1.8 V.
XTALOUT 7[5] O Output from th e oscillator ampli f ier.
VSS 41 I Ground.
Table 3. LPC1113/14 pin description table (LQFP48 package) …continued
Symbol Pin Type Description
Table 4. LPC1114 p in  description table (PLCC44 package)
Symbol Pin Type Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual di rection and function 
controls for each bit. The operation of port 0 pins depends on the function 
selected through the IOCONFIG register block.
RESET/PIO0_0 7 I RESET — External reset input: A LOW on this pin resets the device, 
causing I/O ports and peripherals to take on their default states, and 
processor execution to begin at address 0. 
I/O PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/
CT32B0_MAT2 8[1] I/O PIO0_1 — General purpose digital input/output pin. A LOW level on this pin 
during reset starts the ISP command handler.
OCLKOUT — Clockout pin.
OCT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 14[1] I/O PIO0_2 — General purpose digital input/output pin.
OSSEL0 — Slave Select for SPI0.
ICT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 18[1] I/O PIO0_3 — General purpose digital input/output pin. 
PIO0_4/SCL 19[2] I/O PIO0_4 — General purpose digital input/output pin.
I/O SCL — I2C-bus clock input/output. High-current sink only if I2C Fast-mode 
Plus is selected in the I/O configuration register.
PIO0_5/SDA 20[2] I/O PIO0_5 — General purpose digital input/output pin. 
I/O SDA — I2C-bus data input/output. High-current sink only if I2C Fast-mode 
Plus is selected in the I/O configuration register.
PIO0_6/SCK0 26[1] I/O PIO0_6 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
PIO0_7/CTS 27[1] I/O PIO0_7 — General purpose digital input/output pin (high-current output 
driver).
ICTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 31[1] I/O PIO0_8 — General purpose digital input/output pin.
I/O MISO0 — Master In Slave Out for SPI0.
OCT16B0_MAT0 — Match output 0 for 16-bit timer 0.

DRAFT 
DRAFT DRAFT DR
DRAFT DRAFT DRAFT DRAF
DRAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA
LPC1111_12_13_14_0 © NXP B.V . 2009. All rights reserved.
Objective data sheet Rev. 00.11 — 13 November 2009  12 of 53
NXP Semiconductors LPC1111/12/13/14
PIO0_9/MOSI0/
CT16B0_MAT1 32[1] I/O PIO0_9 — General purpose digital input/output pin.
I/O MOSI0 — Master Out Slave In for SPI0.
OCT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/
SCK0/CT16B0_MAT2 33[1] ISWCLK — Serial wire clock and test clock TCK for JTAG interface.
I/O PIO0_10 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
OCT16B0_MAT2 — Match output 2 for 16-bit timer 0.
TDI/PIO0_11/
AD0/CT32B0_MAT3 36[3] ITDI — Test Data In for JTAG interface.
I/O PIO0_11 — General purpose digital input/output pin.
IAD0 — A/D converter, input 0.
OCT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_11 I/O Port 1 — Port 1 is a 12-bi t I/O port with individual direction and function 
controls for each bit. The operation of port 1 pins depends on the function 
selected through the IOCONFIG register block.
TMS/PIO1_0/
AD1/CT32B1_CAP0 37[3] ITMS — Test Mode Select for JTAG interface.
I/O PIO1_0 — General purpose digital input/output pin.
IAD1 — A/D converter, input 1.
ICT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
TDO/PIO1_1/
AD2/CT32B1_MAT0 38[3] OTDO — Test Data Out for JTAG interface.
I/O PIO1_1 — General purpose digital input/output pin.
IAD2 — A/D converter, input 2.
OCT32B1_MAT0 — Match output 0 for 32-bit timer 1.
TRST/PIO1_2/
AD3/CT32B1_MAT1 39[3] ITRST — Test Reset for JTAG interface.
I/O PIO1_2 — General purpose digital input/output pin.
IAD3 — A/D converter, input 3.
OCT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/AD4/
CT32B1_MAT2 41[3] I/O SWDIO — Serial wire debug input/output.
I/O PIO1_3 — General purpose digital input/output pin.
IAD4 — A/D converter, input 4.
OCT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/AD5/
CT32B1_MAT3/WAKEUP 42[3] I/O PIO1_4 — General purpose digital input/output pin.
IAD5 — A/D converter, input 5.
OCT32B1_MAT3 — Match output 3 for 32-bit timer 1.
IWAKEUP — Deep power-down mode wake-up pin.
PIO1_5/RTS/
CT32B0_CAP0 2[1] I/O PIO1_5 — General purpose digital input/output pin.
ORTS — Request To Send output for UART.
ICT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0 3[1] I/O PIO1_6 — General purpose digital input/output pin.
IRXD — Receiver input for UART.
OCT32B0_MAT0 — Match output 0 for 32-bit timer 0.
Table 4. LPC1114 p in  description table (PLCC44 package) …continued
Symbol Pin Type Description

DRAFT 
DRAFT DRAFT DR
DRAFT DRAFT DRAFT DRAF
DRAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA
LPC1111_12_13_14_0 © NXP B.V . 2009. All rights reserved.
Objective data sheet Rev. 00.11 — 13 November 2009  13 of 53
NXP Semiconductors LPC1111/12/13/14
PIO1_7/TXD/
CT32B0_MAT1 4[1] I/O PIO1_7 — General purpose digital input/output pin.
OTXD — Transmitter output for UART.
OCT32B0_MAT1 — Match output 1 for 32-bit timer 0. 
PIO1_8/CT16B1_CAP0 13[1] I/O PIO1_8 — General purpose digital input/output pin.
ICT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9/CT16B1_MAT0 21[1] I/O PIO1_9 — General purpose digital input/output pin.
OCT16B1_MAT0 — Match output 0 for 16-bit timer 1.
PIO1_10/AD6/
CT16B1_MAT1 34[3] I/O PIO1_10 — General purpose digital input/output pin.
IAD6 — A/D converter, input 6.
OCT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO1_11/AD7 44[3] I/O PIO1_11 — General purpose digital input/output pin.
IAD7 — A/D converter, input 7.
PIO2_0 to PIO2_11 I/O Port 2 — Port 2 is a 12-bi t I/O port with individual direction and function 
controls for each bit. The operation of port 2 pins depends on the function 
selected through the IOCONFIG register block.
PIO2_0/DTR/SSEL1 6[1] I/O PIO2_0 — General purpose digital input/output pin.
ODTR — Data Terminal Ready output for UART.
OSSEL1 — Slave Select for SPI1.
PIO2_1/DSR/SCK1 17[1] I/O PIO2_1 — General purpose digital input/output pin.
IDSR — Data Set Ready input for UART.
I/O SCK1 — Serial clock for SPI1.
PIO2_2/DCD/MISO1 30[1] I/O PIO2_2 — General purpose digital input/output pin.
IDCD — Data Carrier Detect input for UART.
I/O MISO1 — Master In Slave Out for SPI1.
PIO2_3/RI/MOSI1 40[1] I/O PIO2_3 — General purpose digital input/output pin.
IRI — Ring Indicator input for UART.
I/O MOSI1 — Master Out Slave In for SPI1.
PIO2_4 23[1] I/O PIO2_4 — General purpose digital input/output pin.
PIO2_5 24[1] I/O PIO2_5 — General purpose digital input/output pin.
PIO2_6 5[1] I/O PIO2_6 — General purpose digital input/output pin.
PIO2_7 15[1] I/O PIO2_7 — General purpose digital input/output pin.
PIO2_8 16[1] I/O PIO2_8 — General purpose digital input/output pin.
PIO2_9 28[1] I/O PIO2_9 — General purpose digital input/output pin.
PIO2_10 29[1] I/O PIO2_10 — General purpose digital input/output pin.
PIO2_11/SCK0 35[1] I/O PIO2_11 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
PIO3_0 to PIO3_5 I/O Port 3 — Port 3 is a 12-bit I/O port with individual direction and function 
controls for each bit. The operation of port 3 pins depends on the function 
selected through the IOCONFIG register block. Pins PIO3_0 to PIO3_3 and 
PIO3_6 to PIO3_11 are not available.
PIO3_4 22[1] I/O PIO3_4 — General purpose digital input/output pin.
PIO3_5 25[1] I/O PIO3_5 — General purpose digital input/output pin.
Table 4. LPC1114 p in  description table (PLCC44 package) …continued
Symbol Pin Type Description

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 14 of 53

NXP Semiconductors LPC1111/12/13/14

[1] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[2] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.

[4] Tie together VDD(3V3) and VDD(IO) externally. If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference

between both supplies is smaller than or equal to 0.5 V.

[5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

VDD(IO) 12[4] I 3.3 V input/output supply voltage.

VDD(3V3) 1[4] I 3.3 V supply voltage to the internal regulator and the ADC. Also used as the

ADC reference voltage.

VSSIO 9 I Ground.

XTALIN 10[5] I Input to the oscillator circuit and inte rnal clock generator circuits. Input

voltage must not exceed 1.8 V.

XTALOUT 11[5] O Output from the osc il l a to r amp li fier.

VSS 43 I Ground.

Table 4. LPC1114 p in description table (PLCC44 package) …continued

Symbol Pin Type Description

DRAFT 
DRAFT DRAFT DR
DRAFT DRAFT DRAFT DRAF
DRAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA
LPC1111_12_13_14_0 © NXP B.V . 2009. All rights reserved.
Objective data sheet Rev. 00.11 — 13 November 2009  15 of 53
NXP Semiconductors LPC1111/12/13/14
 
Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) 
Symbol Pin Type Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and function 
controls for each bit. The operation of port 0 pins depends on the function 
selected through the IOCONFIG register block.
RESET/PIO0_0 2 I RESET — External reset input: A LOW on this pin resets the device, 
causing I/O ports and peripherals to take on their default states, and 
processor execution to begin at address 0. 
I/O PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/
CT32B0_MAT2 3[1] I/O PIO0_1 — General purpose digital input/output pin. A LOW level on this pin 
during reset starts the ISP command handler.
OCLKOUT — Clock out pin.
OCT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0 8[1] I/O PIO0_2 — General purpose digital input/output pin.
OSSEL0 — Slave select for SPI0.
ICT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 9[1] I/O PIO0_3 — General purpose digital input/output pin. 
PIO0_4/SCL 10[2] I/O PIO0_4 — General purpose digital input/output pin.
I/O SCL — I2C-bus clock input/output. High-current sink only if I2C Fast-mode 
Plus is selected in the I/O configuration register.
PIO0_5/SDA 11[2] I/O PIO0_5 — General purpose digital input/output pin.
I/O SDA — I2C-bus data input/o u tp ut . Hi g h-current sink onl y  if I2C Fast-mode 
Plus is selected in the I/O configuration register.
PIO0_6/SCK0 15[1] I/O PIO0_6 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
PIO0_7/CTS 16[1] I/O PIO0_7 — General purpose digital input/output pin (high-current output 
driver).
ICTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0 17[1] I/O PIO0_8 — General purpose digital input/output pin.
I/O MISO0 — Master In Slave Out for SPI0.
OCT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1 18[1] I/O PIO0_9 — General purpose digital input/output pin.
I/O MOSI0 — Master Out Slave In for SPI0.
OCT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK/PIO0_10/SCK0/
CT16B0_MAT2 19[1] ISWCLK — Serial wire clock and test clock TCK for JTAG interface.
I/O PIO0_10 — General purpose digital input/output pin.
I/O SCK0 — Serial clock for SPI0.
OCT16B0_MAT2 — Match output 2 for 16-bit timer 0.
TDI/PIO0_11/AD0/
CT32B0_MAT3 21[3] ITDI — Test Data In for JTAG interface.
I/O PIO0_11 — General purpose digital input/output pin.
IAD0 — A/D converter, input 0.
OCT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_11 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and function 
controls for each bit. The operation of port 1 pins depends on the function 
selected through the IOCONFIG register block.

DRAFT 
DRAFT DRAFT DR
DRAFT DRAFT DRAFT DRAF
DRAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA
LPC1111_12_13_14_0 © NXP B.V . 2009. All rights reserved.
Objective data sheet Rev. 00.11 — 13 November 2009  16 of 53
NXP Semiconductors LPC1111/12/13/14
TMS/PIO1_0/AD1/
CT32B1_CAP0 22[3] ITMS — Test Mode Select for JTAG interface.
I/O PIO1_0 — General purpose digital input/output pin.
IAD1 — A/D converter, input 1.
ICT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
TDO/PIO1_1/AD2/
CT32B1_MAT0 23[3] OTDO — Test Data Out for JTAG interface.
I/O PIO1_1 — General purpose digital input/output pin.
IAD2 — A/D converter, input 2.
OCT32B1_MAT0 — Match output 0 for 32-bit timer 1.
TRST/PIO1_2/AD3/
CT32B1_MAT1 24[3] ITRST — Test Reset for JTAG interface.
I/O PIO1_2 — General purpose digital input/output pin.
IAD3 — A/D converter, input 3.
OCT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO/PIO1_3/AD4/
CT32B1_MAT2 25[3] I/O SWDIO — Serial wire debug input/output.
I/O PIO1_3 — General purpose digital input/output pin.
IAD4 — A/D converter, input 4.
OCT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4/AD5/
CT32B1_MAT3/WAKEUP 26[3] I/O PIO1_4 — General purpose digital input/output pin.
IAD5 — A/D converter, input 5.
OCT32B1_MAT3 — Match output 3 for 32-bit timer 1.
IWAKEUP — Deep power-down mode wake-up pin.
PIO1_5/RTS/
CT32B0_CAP0 30[1] I/O PIO1_5 — General purpose digital input/output pin.
ORTS — Request To Send outp ut for UART.
ICT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6/RXD/
CT32B0_MAT0 31[1] I/O PIO1_6 — General purpose digital input/output pin.
IRXD — Receiver input for UART.
OCT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7/TXD/
CT32B0_MAT1 32[1] I/O PIO1_7 — General purpose digital input/output pin.
OTXD — Transmit ter output for UART.
OCT32B0_MAT1 — Match output 1 for 32-bit timer 0. 
PIO1_8/CT16B1_CAP0 7[1] I/O PIO1_8 — General purpose digital input/output pin.
ICT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9/CT16B1_MAT0 12[1] I/O PIO1_9 — General purpose digital input/output pin.
OCT16B1_MAT0 — Match output 0 for 16-bit timer 1.
PIO1_10/AD6/
CT16B1_MAT1 20[3] I/O PIO1_10 — General purpose digital input/output pin.
IAD6 — A/D converter, input 6.
OCT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO1_11/AD7 27[3] I/O PIO1_11 — General purpose digital input/output pin.
IAD7 — A/D converter, input 7.
PIO2_0 I/O Port 2 — Port 2 is a 12-bit I/O port with individual direction and function 
controls for each bit. The operation of port 2 pins depends on the function 
selected through the IOCONFIG register block. Pins PIO2_1 to PIO2_11 
are not available.
Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package)  …continued
Symbol Pin Type Description

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 17 of 53

NXP Semiconductors LPC1111/12/13/14

[1] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[2] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant.

[4] Tie together VDD(3V3) and VDD(IO) externally. If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference

between both supplies is smaller than or equal to 0.5 V.

[5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

PIO2_0/DTR 1[1] I/O PIO2_0 — General purpose digital input/output pin.

ODTR — Data Terminal Ready output for UART.

PIO3_0 to PIO3_5 I/O Port 3 — Port 3 is a 12-bit I/O port with individual direction and function

controls for each bit. The operation of port 3 pins depends on the function

selected through the IOCONFIG register block. Pins PIO3_0, PIO3_1,

PIO3_3 and PIO3_6 to PIO3_11 are not availabl e.

PIO3_2 28[1] I/O PIO3_2 — General purpose digital input/output pin.

PIO3_4 13[1] I/O PIO3_4 — General purpose digital input/output pin.

PIO3_5 14[1] I/O PIO3_5 — General purpose digital input/output pin.

VDD(IO) 6[4] I 3.3 V input/output supply voltage.

VDD(3V3) 29[4] I 3.3 V supply voltage to the internal DC-DC converter and the ADC. Also

used as the ADC reference voltage.

XTALIN 4[5] I Input to the oscillator circuit and internal clock generator circuits. Input

voltage must not exceed 1.8 V.

XTALOUT 5[5] O Output from th e oscillator amplifier.

VSS 33 - Thermal pad. Connect to ground.

Table 5. LPC1111/12/13/14 pin description table (HVQFN33 package) …continued

Symbol Pin Type Description

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 18 of 53

NXP Semiconductors LPC1111/12/13/14

7. Functional description

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption.

7.2 On-chip flash program memory

The LPC1111/12/13/14 contain 32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), or

8 kB (LPC1111) of on-chip flash memory.

7.3 On-chip SRAM

The LPC1111/12/13/14 contain a total of 8 kB, 4 kB, or 2 kB on-chip static RAM memory.

7.4 Memory map

The LPC1111/12/13/14 incorporates several distinct memory regions, shown in the

following figures. Figure 5 shows the overall map of the entire address space from the

user program viewpoint following reset. The interrupt vector area supports address

remapping.

The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128

peripherals. The APB peripheral area is 1 megabyte in size and is divided to allow for up

to 64 peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This

allows simplifying the address decoding for each peripheral.

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 19 of 53

NXP Semiconductors LPC1111/12/13/14

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.5.1 Features

•Controls system exceptions and peripheral interrupts.

(1) LQFP48/PLCC44 packages only.

Fig 5. LPC1111/12/13/14 memory map

0x5000 0000

0x5001 0000

0x5002 0000

0x5020 0000

AHB peripherals

127- 4 reserved

GPIO PIO1

0x5003 0000

0x5004 0000

GPIO PIO2

GPIO PIO3

GPIO PIO0

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 8000

0x4005 C000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

WDT

32-bit counter/timer 0

32-bit counter/timer 1

ADC

UART

PMU

I2C-bus

10 - 13 reserved

reserved

21 - 19 reserved

23 - 31 reserved

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x0000 2000

0x1000 2000

0x1000 1000

0x1000 0800

0x1FFF 0000

0x1FFF 4000

0x2000 0000

0x4000 0000

0x4008 0000

0x5000 0000

0x5020 0000

0xFFFF FFFF

reserved

APB peripherals

AHB peripherals

8 kB SRAM (LPC1113/14/301)

0x1000 0000

4 kB SRAM (LPC1111/12/13/14/201)

2 kB SRAM (LPC1111/12/101)

LPC1111/12/13/14

8 kB on-chip flash (LPC1111)

0x0000 4000

0x0000 6000

16 kB on-chip flash (LPC1112)

0x0000 8000

32 kB on-chip flash (LPC1114)

24 kB on-chip flash (LPC1113)

16 kB boot ROM

0x0000 0000

0x0000 0200

active interrupt vectors

+ 512 byte

002aae699

SPI0

16-bit counter/timer 1

16-bit counter/timer 0

IOCONFIG

system control

22 SPI1(1)

reserved

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•In the LPC1111/12/13/14, the NVIC supports 32 vectored interrupt s including up to 13

inputs to the start logic from individual GPIO pins.

•8 programmable interrupt priority levels, with hardware priority level masking

•Relocatable vector table.

•Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral devi ce has one interrupt line con nected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be

programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.6 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be conn ected to the appro priate pins prior to being activated and pr ior

to any related interrup t(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back as well as the current state of the port pins.

LPC1111/12/13/14 use accelerated GPIO functions:

•GPIO registers are a dedicated AHB peripher al and are accessed through the AHB so

that the fastest possible I/O timing can be achieved.

•Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be

programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.7.1 Features

•Bit level set and clear registers allow a single instr uction to set or clear any nu mber of

bits in one port.

•Direction control of individual bits.

•All I/O default to inputs with pull-ups enabled after reset.

•Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG

block for each GPIO pin.

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7.8 UART

The LPC1111/12/13/14 contains one UART.

Support for RS-4 85 /9 -b it mo d e allo ws bo th software addr ess detection and auto m ati c

address detection using 9-bit mode.

The UART includes a fractional baud rate gen erator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.8.1 Features

•16 Byte Receive and Tr ansmit FIFOs.

•Register locations conform to 16C550 industry standard.

•Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

•Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

•Fractional divider for baud rate control and FIFO control mechan ism tha t en ab le s

software flow control implementation.

•Support for RS-4 85 /9 -b it mo d e.

•Support for modem control.

7.9 SPI serial I/O controller

The LPC1111/12/13/14 contain two SPI controllers on the LQFP48/PLCC44 packages

and one SPI controller on the HVQFN33 packages (SPI0). Both SPI controllers support

SSP features.

The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a sing le mas te r and a si ng le

slave can communicate on the bus during a given data transfer. The SPI supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

7.9.1 Features

•Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

•Synchronous serial communication

•Master or slave operation

•8-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

7.10 I2C-bus serial I/O controller

The LPC1111/12/13/14 contain one I2C-bus controller.

The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a r eceiver-o nly device ( e.g., an LCD driver) or a tra nsmitter with the

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capability to both receive and send information (such as memory). Transmitters and/or

receivers can oper ate in eithe r master or sl ave mo de, dependin g on wheth er the chip has

to initiate a data transfer or is only addressed. The I2C is a mu lti-m a ste r bu s an d can be

controlled by more than one bus master connected to it.

7.10.1 Features

•The I2C-interface is a st andar d I2C compliant bu s interface with open- drain pin s. I2C0

also supports Fast mode plus with bit rates up to 1 Mbit/s.

•Easy to configure as master, slave, or master/slave.

•Programmable clocks allow versatile rate control.

•Bidirectional data transfer between masters and slaves.

•Multi-master bus (no central master).

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Serial clock synchronization allows devices with differ ent bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake mech anism to suspend and

resume serial transfer.

•The I2C-bus can be used for test and diagnostic purposes.

•The I2C-bus controller support s multiple ad dress recognition and a bus monitor mode.

7.11 10-bit ADC

The LPC1111/12/13/14 contains one ADC. It is a single 10-bit successive approximation

ADC with eight channels.

7.11.1 Features

•10-bit successive approximation ADC.

•Input multiplexing among 8 pins.

•Power-down mode.

•Measurement range 0 V to VDD(3V3).

•10-bit conver sio n time ≥ 2.44 μs.

•Burst conversion mode for single or multiple inputs.

•Optional conversion on transition of input pin or Timer Match signal.

•Individual result registers for each ADC channel to reduce interrupt overhead.

7.12 General purpose external event counters/timers

The LPC1111/12/13/14 includes two 32-bit co unter/timers and two 16-bit counter/timers.

The counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes one capture input to tr ap the timer value

when an input signal transitions, optionally generating an interrupt.

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7.12.1 Features

•A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

•Counter or timer op er a tion .

•One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

•Four match registers per timer tha t allow :

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generation.

–Reset timer on match with optional interrupt generation.

•Up to four external outputs corresponding to match registers, with the following

capabilities:

–Set LOW on match.

–Set HIGH on match.

–Toggle on match.

–Do nothing on match.

7.13 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval.

7.14 Watchdog timer

The purpose of the watchdog is to reset the mi crocontroller within a reasonable amount of

time if it enters an erroneous state. When enabled, the watchdog will generate a system

reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined

amount of time.

7.14.1 Features

•Internally resets chip if not periodically reloaded.

•Debug mode.

•Enabled by soft ware but requires a har dware reset or a watchdog reset/interrupt to be

disabled.

•Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 32-bit timer with internal prescaler.

•Selectable time period from (Tcy(WDCLK) ×256 ×4) to (Tcy(WDCLK) ×232 ×4) in

multiples of Tcy(WDCLK) ×4.

•The W atchdog Clock (WDCLK) source can be selected from the Internal RC oscillator

(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential

timing choices of Watchdog operation under different power reduction conditions. It

also provides the ability to run the WDT from an entirely internal source that is not

dependent on an external crystal and its associated components and wiring for

increased reliability.

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7.15 Clocking and power control

7.15.1 Crystal oscillators

The LPC1111/12/13/14 include three independent oscillators. These are the system

oscillator , the Internal RC oscillator (IRC), and the W atchdog oscillator . Each oscillator can

be used for more than one purpose as required in a particular application.

Following reset, the LPC1111/12/13/14 will operate from the Internal RC oscillator until

switched by software. This allows systems to oper ate without any extern al cryst al and the

bootloader code to operate at a known frequency.

See Figure 6 for an overview of the LPC1111/12/13/14 clock generation.

Fig 6. LPC1111/12/13/14 clocking generation block diagram

SYSTEM PLL

IRC oscillator

system oscillator

watchdog oscilllator

watchdog oscillator

IRC oscillator

watchdog oscillator

MAINCLKSEL

(main clock select)

SYSPLLCLKSEL

(system PLL clock select)

SYSTEM CLOCK

DIVIDER

AHB clock 0

(system)

AHBCLKCTRL[1:18]

(AHB clock enable)

AHB clocks 1 to 18

(memories

and peripherals)

SPI0 PERIPHERAL

CLOCK DIVIDER SPI0

SPI1 PERIPHERAL

CLOCK DIVIDER SPI1

UART PERIPHERAL

CLOCK DIVIDER UART

SYSTICK TIMER

CLOCK DIVIDER

WDT CLOCK

DIVIDER

SYSTICK

timer

WDT

WDTUEN

(WDT clock update enable)

watchdog oscillator

IRC oscillator

system oscillator CLKOUT PIN CLOCK

DIVIDER CLKOUT pin

CLKOUTUEN

(CLKOUT update enable)

002aae514

main clock

system clock

IRC oscillator

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7.15.1.1 Internal RC oscillator

The IRC may be used as the clock so urce for th e WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or an y chip reset, the LPC1111/12/13/14 use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.15.1.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL. The ARM processor clock frequency is referred to as CCLK elsewhere in this

document.

7.15.2 System PLL (PLL0)

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce th e ou tp ut clock . Since the

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

The PLL is turned off and bypassed following a chip reset and may be enabled by

software. The program must configure and activate the PLL, wait for the PLL to lock, and

then connect to the PLL as a clock source. The PLL settling time is 100 μs.

7.15.3 Clock output

The LPC1111/12/13/14 features a clock output function that routes the IRC oscillator, the

system oscillator, the watchdog oscillator, or the main clock to an output pin.

7.15.4 Wake-up process

The LPC1111/12/13/14 begin operation at power-up and when awakened from Deep

power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows

chip operation to resume quickly. If the main oscillator or the PLL is needed by the

application, software will need to enable these features and wait for them to stabilize

before they are used as a clock source.

7.15.5 Power control

The LPC1111/12/13/14 support a variety of power control features. There are three

special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep

power-down mode. The CPU clock rate may also be controlled as needed by changing

clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This

allows a trade-off of power versus processing speed based on application requirements.

In addition, a register is provided for shutting down the clocks to individual on-chip

peripherals, allowing fine tuning of power consumption by eliminating all dynamic power

use in any periph era ls th at ar e no t req uired for the a pplica tion. Selected per ipher als have

their own clock divide r wh ich pr ovides even better power control.

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7.15.5.1 Sleep mode

When Sleep mode is entered, the clock to the core is stoppe d. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.15.5.2 Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition analog blocks are shut

down for increased power savings. The user can configure the Deep-sleep mode to a

large extend, selecting any of the oscillators, any of the PLLs, BOD, the ADC, and the

flash to be shut down or remain powered during Deep-sleep mode. The user can also

select which of the oscillators and analog blocks will be powered up after the chip exits

from Deep-sleep mode.

The GPIO pins (up to 15 pins total) serve as external wake-up pins to a dedicated start

logic to wake up the chip from Deep-sleep mode.

The timing of the wake-up process from Deep-sleep mode depends on which blocks are

selected to be powered down during deep-sleep.

For lowest power consumption, the clock source should be switched to IRC before

entering Deep-sleep mode, all oscillators and PLLs should be turned off during

deep-sleep, and the IRC should be selected as clock source when the chip wakes up from

deep-sleep. The IRC can be switched on and off glitch-free and provide s a clea n clock

signal after start-up.

If power consumption is not a concern, any of the os cillators and/or PLLs can be left

running in Deep-sleep mode to obtain short wake-up times when waking up from

deep-sleep.

7.15.5.3 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The LPC1111/12/13/14 can wake up from Deep power-down mode via the

WAKEUP pin.

7.16 System control

7.16.1 Reset

Reset has four sources on the LPC1111/12/13/14: the RESET pin, the Watchdog reset,

power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a

Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage

attains a usable level, starts the IRC and initializes the fla sh co nt ro ller.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

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7.16.2 Brownout detection

The LPC1111/12/13/14 includes four levels for monito ring the voltage on the VDD(3V3) pin.

If this voltage falls below one of the four selected levels, the BOD asserts an interrupt

signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable

signal by reading a dedicated st atus register. An additional threshold level can be selected

to cause a forced reset of the chip.

7.16.3 Code security (Code Read Protection - CRP)

This feature of the LPC1111/12/13/14 allows user to enable different levels of security in

the system so that access to the on-chip flash and use of the JTAG and ISP can be

restricted. When needed, CRP is invoked by programming a specific pattern into a

dedicated flash location. IAP commands are not affected by the CRP.

There are three levels of Code Read Protection:

1. CRP1 disables access to chip via the JTAG and allows par tial flash update (excluding

flash sector 0) using a limited set of the ISP commands. This mode is useful when

CRP is required and flash field updates are needed but all sectors can not be erased.

2. CRP2 disables ac ce ss to ch ip via th e JTAG and only allows full fla sh er ase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to chip via

the JTAG pins and the ISP. This mode effectively disables ISP overr ide using PIO0_1

pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

UART0.

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be

disabled. For details see the LPC11xx user manual.

7.16.4 APB interface

The APB peripherals are located on one APB bus.

7.16.5 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the Boot ROM.

7.16.6 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

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7.16.7 Memory mapping control

The Cortex-M0 incorp orates a mechanism that allows remapping the interrupt vector table

to alternate locations in the memory map. This is controlled via the Vector Table Offset

The vector table may be located anywhere within the bottom 1 GB of Cortex-M0 address

space. The vector table must be located on a 128 word (512 byte) boundary.

7.17 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four

breakpoints and two watchpoints is supported.

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8. Limiting values

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Dependent on package type.

[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD(3V3) supply voltage (3.3 V) core and external

rail 1.8 3.6 V

VDD(IO) input/output supply voltage on pin VDDIO 1.8 3.6 V

VIinput voltage 5 V tolerant I/O

pins; only valid

when the VDD(IO)

supply voltage is

present

[2] −0.5 +5.5 V

IDD supply current per supply pin [3] - 100 mA

ISS ground current per ground pin [3] - 100 mA

Ilatch I/O latch-up current −(0.5VDD(IO)) < VI <

(1.5VDD(IO));

Tj < 125 °C

- 100 mA

Tstg storage temperature [4] −65 +150 °C

Tj(max) maximum junction temperature - 150 °C

Ptot(pack) total power dissipation (per package) based on package

heat transfer, not

device power

consumption

-1.5W

Vesd electrostatic discharge voltage human body

model; all pins [5] −5000 +5000 V

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9. Static characteristics

Table 7. Static characteristics

Tamb =

−

C to +85

C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD(3V3) supply voltage (3.3 V) 1.8 3.3 3.6 V

VDD(IO) input/output supply

voltage 1.8 3.3 3.6 V

IDD supply current active mode;

VDD(3V3) =3.3V;

Tamb =25°C; code

while(1){}

executed from flash; all

peripherals enabled

CCLK = 10 MHz - <tbd> - mA

CCLK = 50 MHz - <tbd> - mA

Sleep mode;

VDD(3V3) = 3.3 V;

Tamb =25°C

-<tbd>-μA

Deep-sleep mode;

VDD(3V3) = 3.3 V;

Tamb =25°C

-<tbd>-μA

Deep power-down mode;

VDD(3V3) = 3.3 V;

Tamb =25°C

-<tbd>-μA

Standard port pins, RESET

IIL LOW-level input current VI= 0 V; on-chip pull-up

resistor disabled --3μA

IIH HIGH-level input

current VI=V

DD(IO); on-chip

pull-down resistor

disabled

--3μA

IOZ OFF-state output

current VO=0V; V

O=V

DD(IO);

on-chip pull-up/down

resistors disabled

--3μA

VIinput voltage pin configured to provide

a digital function [2][3][4] 0- 5.0V

VOoutput voltage output active 0 - VDD(IO) V

VIH HIGH-level input

voltage 2.0--V

VIL LOW-level input voltage - - 0.8 V

Vhys hysteresis voltage - 0.4 - V

VOH HIGH-level output

voltage IOH =−4 mA [5] VDD(IO) −

0.4 --V

VOL LOW-level output

voltage IOL =4 mA [5] --0.4V

IOH HIGH-level output

current VOH =V

DD(IO) −0.4 V [5] −4--mA

IOL LOW-level output

current VOL =0.4V [5] 4--mA

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IOHS HIGH-level short-circuit 
output current VOH =0V [6] --−45 mA
IOLS LOW-level short-circuit 
output current VOL =V
DD(IO) [6] --50mA
Ipd pull-down current VI=5V 10 50 150 μA
Ipu pull-up current VI=0V −15 −50 −85 μA
VDD(IO) <V
I<5V 000μA
High-drive output pin (PIO0_7)
IIL LOW-level input current VI= 0 V; on-chip pull-up 
resistor disabled --3μA
IIH HIGH-level input 
current VI=V
DD(IO); on-chip 
pull-down resistor 
disabled
--3μA
IOZ OFF-state output 
current VO=0V; V
O=V
DD(IO); 
on-chip pull-up/down 
resistors disabled
--3μA
VIinput voltage pin configured to provide 
a digital function [2][3][4] 0- 5.0V
VOoutput voltage  output active 0 - VDD(IO) V
VIH HIGH-level input 
voltage 2.0--V
VIL LOW-level input voltage - - 0.8 V
Vhys hysteresis voltage 0.4 - - V
VOH HIGH-level output 
voltage IOH =−4 mA [5] VDD(IO) − 
0.4 --V
VOL LOW-level output 
voltage IOL =4 mA [5] --0.4V
IOH HIGH-level output 
current VOH =V
DD(IO) −0.4 V [5] 20--mA
IOL LOW-level output 
current VOL =0.4V [5] 4--mA
IOHS HIGH-level short-circuit 
output current VOH =0V [6] 10 50 150 μA
IOLS LOW-level short-circuit 
output current VOL =V
DD(IO) [6] −15 −50 −85 μA
Ipd pull-down current VI=5V 000μA
Ipu pull-up current VI=0V --3μA
VDD(IO) <V
I<5V --3μA
I2C-bus pins (PIO0_4 and PIO0_5)
VIH HIGH-level input 
voltage 0.7VDD(IO) --V
VIL LOW-level input voltage - - 0.3VDD(IO) V
Vhys hysteresis voltage - 0.5VDD(IO) -V
VOL LOW-level output 
voltage IOLS = 20 mA [5] --0.4V
Table 7. Static characteristics …continued
Tamb =
−
40
°
C to +85
°
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit

DRAFT 
DRAFT DRAFT DR
DRAFT DRAFT DRAFT DRAF
DRAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA
LPC1111_12_13_14_0 © NXP B.V . 2009. All rights reserved.
Objective data sheet Rev. 00.11 — 13 November 2009  32 of 53
NXP Semiconductors LPC1111/12/13/14
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. 
[2] Including voltage on outputs in 3-state mode.
[3] VDD(3V3) and VDD(IO) supply voltages must be present.
[4] 3-state outputs go into 3-state mode when VDD(IO) is grounded.
[5] Accounts for 100 mV voltage drop in all supply lines.
[6] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[7] To VSS.
 
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[2] Conditions: VSS =0V, V
DD(3V3) =3.3V.
[3] The ADC is monotonic, there are no missing codes.
[4] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 7.
[5] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after 
appropriate adjustment of gain and offset errors. See Figure 7.
[6] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the 
ideal curve. See Figure 7.
[7] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset 
error, and the straight line which fits the ideal transfer curve. See Figure 7.
[8] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated 
ADC and the ideal transfer curve. See Figure 7.
ILI input leakage current VI=V
DD(IO) [7] -24μA
VI=5V - 10 22 μA
Oscillator pins
Vi(xtal) crystal input voltage 0 1.8 1.95 V
Vo(xtal) crystal output voltage 0 1.8 1.95 V
Table 7. Static characteristics …continued
Tamb =
−
40
°
C to +85
°
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
Table 8. ADC static characteristics
Tamb =
−
40
°
C to +85
°
C unless otherwise specified; ADC frequen cy 4.5 MHz, VDD(3V3) = 2.5 V to 3.6 V.
Symbol Parameter Conditions Min Typ[1] Max Unit
VIA analog input vol tage 0 - VDD(3V3) V
Cia analog input capacitance - - 1 pF
EDdifferential linearity error [2][3][4] -± 1- LSB
EL(adj) integral non-linearity [2][5] -± 1.5 - LSB
EOoffset error [2][6] -± 2.5 - LSB
EGgain error [2][7] -0.5-%
ETabsolute er ror [2][8] -± 3- LSB

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 33 of 53

NXP Semiconductors LPC1111/12/13/14

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 7. ADC characteristics

002aae787

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VDD(3V3) − VSS

1024

offset

error

gain

error

offset error

VIA (LSBideal)

1 LSB =

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 34 of 53

NXP Semiconductors LPC1111/12/13/14

9.1 BOD static characteristics

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC11xx

user manual.

9.2 Power consumption

Table 9. BOD static characteristics[1]

Tamb =25

Symbol Parameter Conditions Min Typ Max Unit

Vth threshold voltage interrupt level 0

assertion - 1.69 - V

de-assertion - 1.84 - V

interrupt level 1

assertion - 2.29 - V

de-assertion - 2.44 - V

interrupt level 2

assertion - 2.59 - V

de-assertion - 2.74 - V

interrupt level 3

assertion - 2.87 - V

de-assertion - 2.98 - V

reset level 0

assertion - 1.49 - V

de-assertion - 1.64 - V

Conditions: Tamb = 25 °C; active mode entered executing code from flash; core voltage 3.3 V; all

peripherals enabled but not configured to run.

Fig 8. Supply current at different core frequencies in active mo de

X (X)

X XXXX

001aac984

(X)

<tbd>

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 35 of 53

NXP Semiconductors LPC1111/12/13/14

Conditions: Tamb = 25 °C; active mode entered executing code from flash; all peripherals enabled

but not configured to run.

Fig 9. Supp ly cur r en t at different core vo ltages in active mo de

Conditions: active mode entered executing code from flash; core voltage 3.3 V; all peripherals

enabled but not configured to run.

Fig 10. Supply current at di fferent temperatures in active mode

X (X)

X XXXX

001aac984

(X)

<tbd>

X (X)

X XXXX

001aac984

(X)

<tbd>

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 36 of 53

NXP Semiconductors LPC1111/12/13/14

9.3 Electrical pin characteristics

Conditions: VDD(IO) = 3.3 V; Tamb = 25 °C.

Fig 11. I2C-bus current (IIL vs. VIL)

Conditions: VDD(IO) = 3.3 V; Tamb = 25 °C.

Fig 12. High drive output (IOH vs. VOH) on pin PIO0_7

IIN (mA)

0 1208040

002aae336

500

1000

2000

VIN

(mV)

002aae337

IOUT (mA)

0 1006040 8020

VOUT

(V)

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 37 of 53

NXP Semiconductors LPC1111/12/13/14

Measured on pins Pn.m; VDD(3V3) = x.x V.

Fig 13. Typical LOW-level output IOL current versus LOW-level output VOL

Measured on pins Pn.m; VDD(3V3) = x.x V.

Fig 14. Typical HIGH-level output IOH current versus HIGH-level output voltage VOH

X (X)

X XXXX

001aac984

(X)

<tbd>

X (X)

X XXXX

001aac984

(X)

<tbd>

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 38 of 53

NXP Semiconductors LPC1111/12/13/14

Measured on pins Pn.m; VDD(3V3) = x.x V.

Fig 15. Typical pull-up cur ren t Ipu versus input voltage Vi

Measured on pins Pn.m; VDD(3V3) = x.x V.

Fig 16. Typical pull-down cur rent Ipd versus input voltage Vi

X (X)

X XXXX

001aac984

(X)

<tbd>

X (X)

X XXXX

001aac984

(X)

<tbd>

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 39 of 53

NXP Semiconductors LPC1111/12/13/14

10. Dynamic characteristics

10.1 Flash memory

[1] Number of program/erase cycles.

10.2 External clock

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

Table 10. Flash characteristics

Tamb =

−

C to +85

C, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance [1] 10000 - - cycles

tret retention time powered 10 - - years

unpowered 20 - - years

Table 11. Dynamic characteristic: external clock

Tamb =

−

C to +85

C; VDD(3V3) over specified ranges.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc oscillator frequency 1 - 25 MHz

Tcy(clk) clock cycle time 40 - 1000 ns

tCHCX clock HIGH time Tcy(clk) ×0.4 - - ns

tCLCX clock LOW time Tcy(clk) ×0.4 - - ns

tCLCH clock rise time - - 5 ns

tCHCL clock fall time - - 5 ns

Fig 17. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)

CHCL

CLCX

CHCX

cy(clk)

CLCH

002aaa907

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 40 of 53

NXP Semiconductors LPC1111/12/13/14

10.3 Internal oscillators

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.

Table 12. Dynamic characteristic: internal osc illators

Tamb =

−

C to +85

C; VDD(3V3) over specified ranges.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MHz

conditions: <tbd>

Fig 18. Internal RC oscillator frequency vs. temperatu re

conditions: <tbd>

Fig 19. Internal RC oscillator frequency vs. core voltage

X (X)

X XXXX

001aac984

(X)

<tbd>

X (X)

X XXXX

001aac984

(X)

<tbd>

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 41 of 53

NXP Semiconductors LPC1111/12/13/14

10.4 I2C-bus

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Main clock frequency 10 MHz; system clock divider AHBCLKDIV = 0x1; I2C-bus interface configured in master mode.

[3] Bus capacitance Cb = 550 pF; external pull-up resistance of 103 Ω.

Table 13. Dynamic characteristic: I2C-bus pins (Fast-mode Plus)

Tamb =

−

C to +85

C; VDD(3V3) = VDD(IO) = 3.3 V.[1][2][3]

Symbol Parameter Conditions Min Typ Max Unit

fSCL SCL clock frequency - - 1 MHz

tffall time - - 45 ns

tSU;DAT data set-up time - 50 - - ns

Fig 20. I2C-bus pins clock timing

002aae860

SU;DAT

HIGH

LOW

SDA

SCL

DRAFT 
DRAFT DRAFT DR
DRAFT DRAFT DRAFT DRAF
DRAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA
LPC1111_12_13_14_0 © NXP B.V . 2009. All rights reserved.
Objective data sheet Rev. 00.11 — 13 November 2009  42 of 53
NXP Semiconductors LPC1111/12/13/14
10.5 SPI interfaces
 
[1] Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the 
main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI  SCR parameter (specified in the SSP0CR0 register), 
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] Tamb = −40 °C to 85 °C; VDD(3V3) = 2.0 V to 3.6 V; VDD(IO) = 2.0 V to 3.6 V.
[3] Tcy(clk) = 12 × Tcy(PCLK).
[4] Tamb = 25 °C; VDD(3V3) = 3.3 V; VDD(IO) = 3.3 V.
Table 14. Dynamic characteristics of SPI pins in SPI mode
Symbol Parameter Conditions Min Typ Max Unit
Tcy(PCLK) PCLK cycle time 13.9 - - ns
Tcy(clk) clock cycle time [1] 27.8 - - ns
SPI master (in SPI mode)
tDS data set-up time  in SPI mode [2] 15 - Tcy(clk) ns
tDH data hold time in SPI mode [2] --0ns
tv(Q) data output valid time in SPI mode [2] - - 10 ns
th(Q) data output hold time in SPI mode [2] --0ns
SPI slave (in SPI mode)
tDS data set-up time  in SPI mode [3][4] 0--ns
tDH data hold time in SPI mode [3][4] 3 × Tcy(PCLK) + 4 - - ns
tv(Q) data output valid time in SPI mode [3][4] --3 × Tcy(PCLK) + 11 ns
th(Q) data output hold time in SPI mode [3][4] --2 × Tcy(PCLK) + 5 ns

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 43 of 53

NXP Semiconductors LPC1111/12/13/14

Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 21. SPI master timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk) tclk(H) tclk(L)

tDS tDH

tv(Q)

D ATA V ALID D ATA V ALID

th(Q)

SCK (CPOL = 1)

D ATA V ALID D ATA V ALID

MOSI

MISO

tDS tDH

D ATA V ALID D ATA V ALID

th(Q)

D ATA V ALID D ATA V ALID

tv(Q)

CPHA = 1

CPHA = 0

002aae829

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 44 of 53

NXP Semiconductors LPC1111/12/13/14

Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 22. SPI slave timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk) tclk(H) tclk(L)

tDS tDH

tv(Q)

D ATA V ALID D ATA V ALID

th(Q)

SCK (CPOL = 1)

D ATA V ALID D ATA V ALID

MOSI

MISO

tDS tDH

tv(Q)

D ATA V ALID D ATA V ALID

th(Q)

D ATA V ALID D ATA V ALID

CPHA = 1

CPHA = 0

002aae830

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 45 of 53

NXP Semiconductors LPC1111/12/13/14

11. Application information

11.1 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommende d that the inpu t be coupled throug h a cap acitor with

Ci = 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground Cg which attenuate s the input volt age by a facto r Ci/(Ci + Cg). In slave

mode, a minimum of 200 mV(RMS) is needed.

11.2 XTAL Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors Cx1,Cx2, and Cx3 in case of

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

order to keep the no ise couple d in via th e PCB as sm all as po ss ible . A lso parasitic s

should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

11.3 Standard I/O pad configuration

Figure 24 shows the possible pin modes for standard I/O pins. The pull-up and pull-down

resistors (Rpu and Rpd) can be enabled or disabled. The default value for each standard

port pin is input with Rpu enabled. For deta ils on pin modes an d hysteresis control, see the

LPC11 xx user manual.

Fig 23. Slave mode operation of the on-chip oscillator

LPC1xxx

XTALIN

100 pF Cg

002aae788

DRAFT

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DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 46 of 53

NXP Semiconductors LPC1111/12/13/14

Fig 24. Standard I/O pad configuration

VDD(IO)

VSS

Rpd

Rpu

enable

output

input

002aae828

hysteresis

control

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 47 of 53

NXP Semiconductors LPC1111/12/13/14

12. Package outline

Fig 25. Package outline SOT313-2 (LQFP48)

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 1.6 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 7.1

6.9 0.5 9.15

8.85 0.95

0.55 7

0.12 0.10.21

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2 MS-026136E05 00-01-19

03-02-25

D(1) (1)(1)

7.1

6.9

9.15

8.85

0.95

0.55

vMB

vMA

36 25

detail X

(A )

0 2.5 5 mm

scale

pin 1 index

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 48 of 53

NXP Semiconductors LPC1111/12/13/14

Fig 26. Package outline PLCC44

UNIT A A1

min.

max. bpeywv β

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.57

4.19 0.51 3.05 0.53

0.33

0.021

0.013

16.66

16.51 1.27 17.65

17.40 2.16 45o

0.18 0.10.18

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

SOT187-2

D(1) E(1)

16.66

16.51

HDHE

17.65

17.40

ZD(1)

max. ZE(1)

max.

2.16

0.81

0.66

1.22

1.07

0.180

0.165 0.02 0.12

0.25

0.01 0.656

0.650 0.05 0.695

0.685 0.085

0.007 0.0040.007

1.44

1.02

0.057

0.040

0.656

0.650 0.695

0.685

eDeE

16.00

14.99

0.63

0.59

16.00

14.99

0.63

0.59 0.085

0.032

0.026 0.048

0.042

2939

717

detail X

(A )

AA4

βk

vMB

vMA

pin 1 index

112E10 MS-018 EDR-7319

0 5 10 mm

scale

99-12-27

01-11-14

inches

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 49 of 53

NXP Semiconductors LPC1111/12/13/14

Fig 27. Package outline (HVQFN33)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

- - -

hvqfn33_po

09-03-17

09-03-23

Unit

mm max

nom

min

1.00

0.85

0.80

0.05

0.02

0.00 0.2 7.1

7.0

6.9

4.85

4.70

4.55

7.1

7.0

6.9 0.65 4.55 0.75

0.60

0.45 0.1

A(1)

Dimensions

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;

33 terminals; body 7 x 7 x 0.85 mm

A1b

0.35

0.28

0.23

(1) DhE(1) Eh

4.85

4.70

4.55

1e2

4.55

0.1

0.05

0.08

0 2.5 5 mm

scale

terminal 1

index area

detail X

AC B

vCw

terminal 1

index area Dh

L9 16

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFT DRAF

DRAFT DRAFT DRAFT DRAFT DRAFT D

DRAFT DRAFT DRAFT DRAFT DRAFT DRAFT DRA

Objective data sheet Rev. 00.11 — 13 November 2009 50 of 53

NXP Semiconductors LPC1111/12/13/14

13. Abbreviations

Ta ble 15. Ab breviations

Acronym Description

ADC Analog-to-Di gital Converter

AHB Advanced High-performance Bus

AMBA Advanced Microcontroller Bus Architecture

APB Advanced Peripheral Bus

BOD BrownOut Detection

ETM Embedded Trace Macrocell

GPIO General Purpose Input/Output

PLL Phase-Locked Loop

SPI Serial Peripheral Interface

SSI Serial Synchronous Interface

TTL Transistor-Transistor Logic

UART Universal Asynchronous Receiver/Transmitter

DRAFT

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Objective data sheet Rev. 00.11 — 13 November 2009 51 of 53

NXP Semiconductors LPC1111/12/13/14

14. Revision history

Table 16. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC1111_12_13_14_0.11 <tbd> Objective data sheet - LPC1111_12_13_0.09

Modifications: •Part LPC111 4 added.

•Parts LPC1111/101, LPC1112/101 ad ded.

•Flash and SRAM configuration change d (see Table 2).

LPC1111_12_13_0.09 <tbd> Objective data sheet - LPC1111_13_0.06

Modifications: •Part LPC111 2 added.

•PLCC44 package added.

LPC1111_13_0.06 <tbd> Objective data sheet - LPC1111_13_0.05

Modifications: SWO removed from pin description

LPC1111_13_0.05 <tbd> Objective data sheet - LPC1111_13_0.04

Modifications: Editorial updates.

LPC1111_13_0.04 <tbd> Objective data sheet - LPC11xx_0.03

Modifications: SPI1 interface added for LQFP48 packages.

LPC11xx_0.03 <tbd> Object iv e da ta sheet - -

DRAFT

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Objective data sheet Rev. 00.11 — 13 November 2009 52 of 53

NXP Semiconductors LPC1111/12/13/14

15. Legal information

16. Data sheet st atus

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.1 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

16.2 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconduct ors does not give any repr esentatio ns or

warranties, expressed or impli ed, as to the accuracy or completen ess of such

information and shall have no liability for th e consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, milit ary, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ra tings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyri ghts, patents or

other industrial or intellectual property right s.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

16.3 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

DRAFT

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NXP Semiconductors LPC1111/12/13/14

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 November 2009

Document identifier: LPC1111_12_13_14_0

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

7 Functional description . . . . . . . . . . . . . . . . . . 18

7.1 ARM Cortex-M0 processor. . . . . . . . . . . . . . . 18

7.2 On-chip flash program memory . . . . . . . . . . . 18

7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 18

7.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.5 Nested Vectored Interrupt Controller (NVIC) . 19

7.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.5.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 20

7.6 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 20

7.7 Fast general purpose parallel I/O. . . . . . . . . . 20

7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.8 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.9 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 21

7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.10 I2C-bus serial I/O controller . . . . . . . . . . . . . . 21

7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.11 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.12 General purpose external event

counters/timers. . . . . . . . . . . . . . . . . . . . . . . . 22

7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.13 System tick timer . . . . . . . . . . . . . . . . . . . . . . 23

7.14 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 23

7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.15 Clocking and power control . . . . . . . . . . . . . . 24

7.15.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 24

7.15.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 25

7.15.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 25

7.15.2 System PLL (PLL0) . . . . . . . . . . . . . . . . . . . . 25

7.15.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.15.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 25

7.15.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.15.5.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.15.5.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 26

7.15.5.3 Deep power-down mode . . . . . . . . . . . . . . . . 26

7.16 System control . . . . . . . . . . . . . . . . . . . . . . . . 26

7.16.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.16.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 27

7.16.3 Code security (Code Read Protecti on - CRP) 27

7.16.4 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 27

7.16.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.16.6 External in te rru p t inputs. . . . . . . . . . . . . . . . . 27

7.16.7 Memory mapping control . . . . . . . . . . . . . . . . 28

7.17 Emulation and debugging . . . . . . . . . . . . . . . 28

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29

9 Static characteristics . . . . . . . . . . . . . . . . . . . 30

9.1 BOD static characteristics . . . . . . . . . . . . . . . 34

9.2 Power consumption . . . . . . . . . . . . . . . . . . . 34

9.3 Electrical pin characteristics. . . . . . . . . . . . . . 36

10 Dynamic characteristics. . . . . . . . . . . . . . . . . 39

10.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 39

10.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 39

10.3 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 40

10.4 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.5 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 42

11 Application information . . . . . . . . . . . . . . . . . 45

11.1 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11.2 XTAL Printed Circuit Board (PCB) layout

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11.3 Standard I/O pad configuration . . . . . . . . . . . 45

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 47

13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 50

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 51

15 Legal information . . . . . . . . . . . . . . . . . . . . . . 52

16 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 52

16.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

16.2 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 52

16.3 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52

17 Contact information . . . . . . . . . . . . . . . . . . . . 52

18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53