MAX149BCAP - Maxim Integrated Products, Inc.

General Description

The MAX148/MAX149 10-bit data-acquisition systems

combine an 8-channel multiplexer, high-bandwidth

track/hold, and serial interface with high conversion

speed and low power consumption. They operate from a

single +2.7V to +5.25V supply, and sample to 133ksps.

Both devices’ analog inputs are software configurable for

unipolar/bipolar and single-ended/differential operation.

The 4-wire serial interface connects directly to SPI™/

QSPI™ and MICROWIRE™ devices without external

logic. A serial-strobe output allows direct connection to

TMS320-family digital signal processors. The MAX148/

MAX149 use either the internal clock or an external serial-

interface clock to perform successive-approximation

analog-to-digital conversions.

The MAX149 has an internal 2.5V reference, while the

MAX148 requires an external reference. Both parts have

a reference-buffer amplifier with a ±1.5% voltage-

adjustment range.

These devices provide a hard-wired SHDN pin and a

software-selectable power-down, and can be pro-

grammed to automatically shut down at the end of a con-

version. Accessing the serial interface automatically

powers up the MAX148/MAX149, and the quick turn-on

time allows them to be shut down between all conver-

sions. This technique can cut supply current to under

60µA at reduced sampling rates.

The MAX148/MAX149 are available in a 20-pin DIP and a

20-pin SSOP.

For 4-channel versions of these devices, see the

MAX1248/MAX1249 data sheet.

________________________Applications

Portable Data Logging Data Acquisition

Medical Instruments Battery-Powered Instruments

Pen Digitizers Process Control

____________________________Features

♦8-Channel Single-Ended or 4-Channel

Differential Inputs

♦Single-Supply Operation: +2.7V to +5.25V

♦Internal 2.5V Reference (MAX149)

♦Low Power: 1.2mA (133ksps, 3V supply)

54µA (1ksps, 3V supply)

1µA (power-down mode)

♦SPI/QSPI/MICROWIRE/TMS320-Compatible

4-Wire Serial Interface

♦Software-Configurable Unipolar or Bipolar Inputs

♦20-Pin DIP/SSOP Packages

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

________________________________________________________________

Maxim Integrated Products

VDD

I/O

SCK (SK)

MOSI (SO)

MISO (SI)

VSS

SHDN

SSTRB

DOUT

DIN

SCLK

COM

AGND

DGND

VDD

CH7

4.7µF

0.1µF

CH0

0V TO

+2.5V

ANALOG

INPUTS

MAX149 CPU

+3V

VREF

0.01µFREFADJ

__________Typical Operating Circuit

19-0464; Rev 2; 5/98

PART†

MAX148ACPP

MAX148BCPP

MAX148ACAP 0°C to +70°C

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

20 Plastic DIP

20 SSOP

EVALUATION KIT

AVAILABLE

Ordering Information

Ordering Information continued at end of data sheet.

†

Contact factory for availability of alternate surface-mount

packages.

MAX148BCAP 0°C to +70°C 20 SSOP

INL

(LSB)

±1/2

±1

±1/2

±1

SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.

Pin Configuration appears at end of data sheet.

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 408-737-7600 ext. 3468.

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

VDD = +2.7V to +5.25V; COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);

MAX149—4.7µF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; TA= TMIN to TMAX; unless

otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD to AGND, DGND................................................. -0.3V to 6V

AGND to DGND...................................................... -0.3V to 0.3V

CH0–CH7, COM to AGND, DGND............ -0.3V to (VDD + 0.3V)

VREF, REFADJ to AGND........................... -0.3V to (VDD + 0.3V)

Digital Inputs to DGND.............................................. -0.3V to 6V

Digital Outputs to DGND........................... -0.3V to (VDD + 0.3V)

Digital Output Sink Current.................................................25mA

Continuous Power Dissipation (TA= +70°C)

Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW

SSOP (derate 8.00mW/°C above +70°C) ................... 640mW

CERDIP (derate 11.11mW/°C above +70°C).............. 889mW

Operating Temperature Ranges

MAX148_C_P/MAX149_C_P.............................. 0°C to +70°C

MAX148_E_P/MAX149_E_P............................ -40°C to +85°C

MAX148_MJP/MAX149_MJP........................ -55°C to +125°C

Storage Temperature Range............................ -60°C to +150°C

Lead Temperature (soldering, 10sec)............................ +300°C

µs1.5tACQ

Differential Nonlinearity

Track/Hold Acquisition Time ns30Aperture Delay

6µs

35 65

tCONV

Conversion Time (Note 5) 5.5 7.5

MHz1.0Full-Power Bandwidth MHz2.25Small-Signal Bandwidth dB-75Channel-to-Channel Crosstalk dB70SFDRSpurious-Free Dynamic Range dB-70THDTotal Harmonic Distortion dB66SINADSignal-to-Noise + Distortion Ratio

LSB±0.05

Channel-to-Channel Offset

Matching

ppm/°C±0.25Gain Temperature Coefficient

±0.5

<50

Bits10Resolution

Gain Error (Note 3) ±1

Aperture Jitter

Offset Error

LSB

±1.0

INLRelative Accuracy (Note 2)

LSB±1DNL ±0.15 ±1 LSB

±0.15 ±2

UNITSMIN TYP MAXSYMBOLPARAMETER

External clock = 2MHz, 12 clocks/conversion

Internal clock, SHDN = VDD

Internal clock, SHDN = FLOAT

MAX14_A

-3dB rolloff

65kHz, 2.500Vp-p (Note 4)

Up to the 5th harmonic

MAX14_A

MAX14_B

No missing codes over temperature

MAX14_A

MAX14_B

CONDITIONS

LSB

±2MAX14_B

DC ACCURACY (Note 1)

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)

CONVERSION RATE

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

_______________________________________________________________________________________ 3

Multiplexer Leakage Current

µA0.01 10Shutdown VREF Input Current kΩ18 25VREF Input Resistance µA100 150VREF Input Current

1.0 VDD +

50mV

VREF Input Voltage Range

(Note 9)

pF16Input Capacitance

1.8 MHz

0.225

Internal Clock Frequency

µA±0.01 ±1

UNITSMIN TYP MAXSYMBOLPARAMETER

SHDN = FLOAT

VREF = 2.500V

SHDN = VDD

On/off leakage current, VCH_ = 0V or VDD

CONDITIONS

ELECTRICAL CHARACTERISTICS (continued)

VDD = +2.7V to +5.25V; COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);

MAX149—4.7µF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; TA= TMIN to TMAX; unless

otherwise noted.)

V2.470 2.500 2.530VREF Output Voltage TA= +25°C (Note 7) mA30VREF Short-Circuit Current ±30MAX149 mV0.35Load Regulation (Note 8) 0mA to 0.2mA output load 0Internal compensation mode µF

4.7

Capacitive Bypass at VREF External compensation mode µF0.01Capacitive Bypass at REFADJ %±1.5REFADJ Adjustment Range

VDD -

0.5

REFADJ Buffer-Disable Threshold

µF

Capacitive Bypass at VREF Internal compensation mode

2.00 V/V

2.06

Reference Buffer Gain

4.7

MAX148

MAX149

External compensation mode

±10 µA

±50

REFADJ Input Current MAX148

MAX149

ppm/°CVREF Temperature Coefficient

0 to VREF V

±VREF / 2

Input Voltage Range, Single-

Ended and Differential (Note 6) Unipolar, COM = 0V

Bipolar, COM = VREF / 2

0.1 2.0 MHz

0 2.0

External Clock Frequency Data transfer only

CONVERSION RATE (continued)

ANALOG/COM INPUTS

INTERNAL REFERENCE (MAX149 only, reference buffer enabled)

EXTERNAL REFERENCE AT VREF (Buffer disabled)

EXTERNAL REFERENCE AT REFADJ

IDD

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

VDD = +2.7V to +5.25V; COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);

MAX149—4.7µF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; TA= TMIN to TMAX; unless

otherwise noted.)

3.0

VIH

DIN, SCLK, CS Input High Voltage VDD > 3.6V

mV±0.3PSRSupply Rejection (Note 12) Full-scale input, external reference = 2.500V,

VDD = 2.7V to 5.25V

pF15CIN

DIN, SCLK, CS Input Capacitance µA±0.01 ±1IIN

DIN, SCLK, CS Input Leakage V0.2VHYST

DIN, SCLK, CS Input Hysteresis V0.8VIL

DIN, SCLK, CS Input Low Voltage

2.0

µA±4.0IS

SHDN Input Current V0.4VSL

SHDN Input Low Voltage

VVDD - 0.4VSH

SHDN Input High Voltage

SHDN = 0V or VDD

nA±100

SHDN Maximum Allowed

Leakage, Mid Input

VVDD / 2VFLT

SHDN Voltage, Floating

SHDN = FLOAT

UNITSMIN TYP MAXSYMBOLPARAMETER

(Note 10)

VIN = 0V or VDD

VDD ≤3.6V

CONDITIONS

µA±0.01 ±10IL

Three-State Leakage Current VVDD - 0.5VOH

Output Voltage High

0.8

VOL

Output Voltage Low 0.4

pF15COUT

Three-State Output Capacitance CS = VDD (Note 10)

CS = VDD

ISOURCE = 0.5mA

ISINK = 16mA

ISINK = 5mA

2.70 5.25

1.2 2.0

Operating mode,

full-scale input (Note 11)

3.5 15

Full power-down 1.2 10

1.6 3.0

V1.1 VDD - 1.1VSM

SHDN Input Mid Voltage

Positive Supply Current

VDD

Positive Supply Voltage V

IDD

µA

30 70

DIGITAL INPUTS (DIN, SCLK, CS, SHDN)

DIGITAL OUTPUTS (DOUT, SSTRB)

POWER REQUIREMENTS

Fast power-down (MAX149)IDD

VDD = 5.25V

VDD = 3.6V

VDD = 5.25V

VDD = 3.6V

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

_______________________________________________________________________________________ 5

Figure 1

__________________________________________Typical Operating Characteristics

(VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)

0 256 512 768 1024

INTEGRAL NONLINEARITY

vs. CODE

0.10

0.05

-0.10

-0.05

MAX148/9-01

CODE

INL (LSB)

0.125

2.25 2.75 4.25

INTEGRAL NONLINEARITY

vs. SUPPLY VOLTAGE

0.100

0.075

0.050

0.025

SUPPLY VOLTAGE (V)

INL (LSB)

3.75 5.253.25 4.75

MAX148/9-02

MAX149

MAX148

0.025

0.050

0.075

0.100

0.125

-60 -20 20 60 100 140

INTEGRAL NONLINEARITY

vs. TEMPERATURE

TEMPERATURE (°C)

INL (LSB)

MAX148/9-03

MAX148

MAX149

VDD = 2.7V

TIMING CHARACTERISTICS

(VDD = +2.7V to +5.25V, TA= TMIN to TMAX, unless otherwise noted.)

Note 1: Tested at VDD = 2.7V; COM = 0V; unipolar single-ended input mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: MAX149—internal reference, offset nulled; MAX148—external reference (VREF = +2.500V), offset nulled.

Note 4: Ground “on” channel; sine wave applied to all “off” channels.

Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 6: The common-mode range for the analog inputs is from AGND to VDD.

Note 7: Sample tested to 0.1% AQL.

Note 8: External load should not change during conversion for specified accuracy.

Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.

Note

10:

Guaranteed by design. Not subject to production testing.

Note

11:

The MAX148 typically draws 400µA less than the values shown.

Note

12:

Measured as

VFS(2.7V) - VFS(5.25V)

Internal clock mode only (Note 7)

External clock mode only, Figure 2

External clock mode only, Figure 1

DIN to SCLK Setup

Figure 1

Figure 2

Figure 1

MAX14_ _C/E

CONDITIONS

MAX14_ _M ns

20 240

Figure 1

tCSH

ns240tSTR

CS Rise to SSTRB Output Disable ns240tSDV

CS Fall to SSTRB Output Enable 240tSSTRB

SCLK Fall to SSTRB ns

200tCL

SCLK Pulse Width Low ns200SCLK Pulse Width High ns0

CS to SCLK Rise Hold ns100tCSS

CS to SCLK Rise Setup ns240tTR

CS Rise to Output Disable ns240tDV

CS Fall to Output Enable

tCH

20 200

tDO

SCLK Fall to Output Data Valid

ns0tDH

DIN to SCLK Hold

µs1.5tACQ

Acquisition Time

0tSCK

SSTRB Rise to SCLK Rise

ns100tDS

UNITSMIN TYP MAXSYMBOLPARAMETER

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

6 _______________________________________________________________________________________

2.00

0.502.25 2.75

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

1.75

1.25

1.50

1.00

0.75

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

3.75 5.253.25 4.25 4.75

MAX148/9-04

RL = ∞

CODE = 1010101000 CLOAD = 50pF

MAX148

MAX149

CLOAD = 20pF

02.25 2.75

SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

3.0

2.5

1.5

2.0

1.0

0.5

SUPPLY VOLTAGE (V)

SHUTDOWN SUPPLY CURRENT (µA)

3.75 5.253.25 4.25 4.75

MAX148/9-05

FULL POWER-DOWN

2.5020

2.49902.25 2.75

MAX149

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

2.5015

2.5005

2.5010

2.5000

2.4995

SUPPLY VOLTAGE (V)

INTERNAL REFERENCE VOLTAGE (V)

3.75 5.253.25 4.25 4.75

MAX148/9-06

0.8

0.9

1.0

1.1

1.2

1.3

-60 -20 20 60 100 140

SUPPLY CURRENT vs. TEMPERATURE

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

MAX148/9-07

MAX148

MAX149

RLOAD = ∞

CODE = 1010101000

0.4

0.8

1.2

1.6

2.0

-60 -20 20 60 100 140

SHUTDOWN CURRENT

vs. TEMPERATURE

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

MAX148/9-08

2.494

2.495

2.496

2.497

2.498

2.499

2.500

2.501

-60 -20 20 60 100 140

MAX149

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

TEMPERATURE (°C)

INTERNAL REFERENCE VOLTAGE (V)

MAX148/9-09

VDD = 2.7V

VDD = 3.6V

VDD = 5.25V

____________________________Typical Operating Characteristics (continued)

(VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

_______________________________________________________________________________________ 7

______________________________________________________________Pin Description

VDD

DGND

DOUT

CLOAD

50pF CLOAD

50pF

DGND

DOUT

a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL

VDD

DGND

DOUT

CLOAD

50pF CLOAD

50pF

DGND

DOUT

a) VOH to High-Z b) VOL to High-Z

Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time

Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.REFADJ12

Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX148/MAX149 begin the

A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses

high for one clock period before the MSB decision. High impedance when CS is high (external clock

mode).

SSTRB16

Serial-Data Input. Data is clocked in at SCLK’s rising edge.DIN17

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is

high impedance.

Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets

the conversion speed. (Duty cycle must be 40% to 60%.)

SCLK19

Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.

In internal reference mode (MAX149 only), the reference buffer provides a 2.500V nominal output,

externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling

REFADJ to VDD.

VREF11

Analog GroundAGND13

Digital GroundDGND14

Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.

DOUT15

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX148/MAX149 down; otherwise, they are

fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode.

Letting SHDN float puts the reference-buffer amplifier in external compensation mode.

SHDN

Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be

stable to ±0.5LSB.

COM9

Sampling Analog InputsCH0–CH71–8

FUNCTIONNAME

Positive Supply VoltageVDD

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

8 _______________________________________________________________________________________

_______________Detailed Description

The MAX148/MAX149 analog-to-digital converters

(ADCs) use a successive-approximation conversion

technique and input track/hold (T/H) circuitry to convert

an analog signal to a 10-bit digital output. A flexible seri-

al interface provides easy interface to microprocessors

(µPs). Figure 3 is a block diagram of the MAX148/

MAX149.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog com-

parator is illustrated in the equivalent input circuit

(Figure 4). In single-ended mode, IN+ is internally

switched to CH0–CH7, and IN- is switched to COM. In

differential mode, IN+ and IN- are selected from the fol-

lowing pairs: CH0/CH1, CH2/CH3, CH4/CH5, and

CH6/CH7. Configure the channels with Tables 2 and 3.

In differential mode, IN- and IN+ are internally switched

to either of the analog inputs. This configuration is

pseudo-differential to the effect that only the signal at IN+

is sampled. The return side (IN-) must remain stable within

±0.5LSB (±0.1LSB for best results) with respect to AGND

during a conversion. To accomplish this, connect a 0.1 µF

capacitor from IN- (the selected analog input) to AGND.

During the acquisition interval, the channel selected

as the positive input (IN+) charges capacitor CHOLD.

The acquisition interval spans three SCLK cycles and

ends on the falling SCLK edge after the last bit of the

input control word has been entered. At the end of the

acquisition interval, the T/H switch opens, retaining

charge on CHOLD as a sample of the signal at IN+.

The conversion interval begins with the input multiplexer

switching CHOLD from the positive input (IN+) to the

negative input (IN-). In single-ended mode, IN- is simply

COM. This unbalances node ZERO at the comparator’s

input. The capacitive DAC adjusts during the remainder

of the conversion cycle to restore node ZERO to 0V

within the limits of 10-bit resolution. This action is equiv-

alent to transferring a 16pF x [(VIN+) - (VIN-)] charge

from CHOLD to the binary-weighted capacitive DAC,

which in turn forms a digital representation of the analog

input signal.

Track/Hold

The T/H enters its tracking mode on the falling clock

edge after the fifth bit of the 8-bit control word has been

shifted in. It enters its hold mode on the falling clock

edge after the eighth bit of the control word has been

shifted in. If the converter is set up for single-ended

inputs, IN- is connected to COM, and the converter

samples the “+” input. If the converter is set up for dif-

ferential inputs, IN- connects to the “-” input, and the

difference of |IN+ - IN-|is sampled. At the end of the

conversion, the positive input connects back to IN+,

and CHOLD charges to the input signal.

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens, and more time must be

INPUT

SHIFT

LOGIC

INT

CLOCK

OUTPUT

SHIFT

+1.21V

REFERENCE

(MAX149)

T/H

ANALOG

INPUT

MUX 10+2-BIT

SAR

ADC

DOUT

SSTRB

VDD

DGND

AGND

SCLK

DIN

COM

REFADJ

VREF

OUT

REF

CLOCK

+2.500V

20k

*A ≈ 2.00 (MAX148)

CH6 7

CH4 5

CH2 3

CH0 1

CH7 8

CH5 6

CH3 4

CH1 2

MAX148

MAX149

SHDN

≈ 2.06*

Figure 3. Block Diagram

CH0

CH2

CH4

CH6

CH1

CH3

CH5

CH7

COM

CSWITCH

TRACK

T/H

SWITCH

RIN

CHOLD

HOLD

CAPACITIVE DAC

VREF

ZERO COMPARATOR

–+

16pF

SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.

DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.

AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES

FROM THE SELECTED IN+

CHANNEL TO THE SELECTED

IN- CHANNEL.

INPUT

MUX

Figure 4. Equivalent Input Circuit

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

_______________________________________________________________________________________ 9

allowed between conversions. The acquisition time,

tACQ, is the maximum time the device takes to acquire

the signal, and is also the minimum time needed for the

signal to be acquired. It is calculated by the following

equation: tACQ = 7 x (RS+ RIN) x 16pF

where RIN = 9kΩ, RS= the source impedance of the

input signal, and tACQ is never less than 1.5µs. Note

that source impedances below 4kΩdo not significantly

affect the ADC’s AC performance.

Higher source impedances can be used if a 0.01µF

capacitor is connected to the individual analog inputs.

Note that the input capacitor forms an RC filter with the

input source impedance, limiting the ADC’s signal

bandwidth.

Input Bandwidth

The ADC’s input tracking circuitry has a 2.25MHz

small-signal bandwidth, so it is possible to digitize

high-speed transient events and measure periodic sig-

nals with bandwidths exceeding the ADC’s sampling

rate by using undersampling techniques. To avoid

high-frequency signals being aliased into the frequency

band of interest, anti-alias filtering is recommended.

Analog Input Protection

Internal protection diodes, which clamp the analog input

to VDD and AGND, allow the channel input pins to swing

from AGND - 0.3V to VDD + 0.3V without damage.

However, for accurate conversions near full scale, the

inputs must not exceed VDD by more than 50mV or be

lower than AGND by 50mV.

If the analog input exceeds 50mV beyond the sup-

plies, do not forward bias the protection diodes of

off channels over 2mA.

Quick Look

To quickly evaluate the MAX148/MAX149’s analog perfor-

mance, use the circuit of Figure 5. The MAX148/MAX149

require a control byte to be written to DIN before each

conversion. Tying DIN to +3V feeds in control bytes of

$FF (HEX), which trigger single-ended unipolar conver-

sions on CH7 in external clock mode without powering

down between conversions. In external clock mode, the

SSTRB output pulses high for one clock period before

the most significant bit of the conversion result is shift-

ed out of DOUT. Varying the analog input to CH7 will

alter the sequence of bits from DOUT. A total of 15

clock cycles is required per conversion. All transitions

of the SSTRB and DOUT outputs occur on the falling

edge of SCLK.

0.1µF

VDD

DGND

AGND

COM

SCLK

DIN

DOUT

SSTRB

SHDN

+3V

N.C.

0.01µF CH7

+3V REFADJ

VREF

0.1µF

0V TO

+2.500V

ANALOG

INPUT

OSCILLOSCOPE

CH1 CH2 CH3 CH4

* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)

OPTIONAL FOR MAX149,

REQUIRED FOR MAX148

MAX148

MAX149

+3V

2MHz

OSCILLATOR

SCLK

SSTRB

DOUT*

2.5V

1000pF

COMP

VOUT

+3V

MAX872

Figure 5. Quick-Look Circuit

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

10 ______________________________________________________________________________________

How to Start a Conversion

Start a conversion by clocking a control byte into DIN.

With CS low, each rising edge on SCLK clocks a bit from

DIN into the MAX148/MAX149’s internal shift register.

After CS falls, the first arriving logic “1” bit defines the

control byte’s MSB. Until this first “start” bit arrives, any

number of logic “0” bits can be clocked into DIN with no

effect. Table 1 shows the control-byte format.

The MAX148/MAX149 are compatible with SPI/

QSPI and MICROWIRE devices. For SPI, select the cor-

rect clock polarity and sampling edge in the SPI control

registers: set CPOL = 0 and CPHA = 0. MICROWIRE,

SPI, and QSPI all transmit a byte and receive a byte at

the same time. Using the

Typical Operating Circuit,

the

simplest software interface requires only three 8-bit

transfers to perform a conversion (one 8-bit transfer to

configure the ADC, and two more 8-bit transfers to clock

out the conversion result). See Figure 20 for MAX148/

MAX149 QSPI connections.

BIT NAME DESCRIPTION

7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.

6 SEL2 These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).

5 SEL1

4 SEL0

3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an

analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range

from -VREF/2 to +VREF/2.

2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-

ended mode, input signal voltages are referred to COM. In differential mode, the voltage

difference between two channels is measured (Tables 2 and 3).

1 PD1 Selects clock and power-down modes.

0(LSB) PD0 PD1 PD0 Mode

0 0 Full power-down

0 1 Fast power-down (MAX149 only)

1 0 Internal clock mode

1 1 External clock mode

Table 1. Control-Byte Format

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

(MSB) (LSB)

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

0 0 0 + –

1 0 0 + –

0 0 1 + –

1 0 1 + –

0 1 0 + –

1 1 0 + –

0 1 1 + –

1 1 1 + –

Table 2. Channel Selection in Single-Ended Mode (SGL/DDIIFF= 1)

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

______________________________________________________________________________________ 11

Simple Software Interface

Make sure the CPU’s serial interface runs in master

mode so the CPU generates the serial clock. Choose a

clock frequency from 100kHz to 2MHz.

1) Set up the control byte for external clock mode and

call it TB1. TB1 should be of the format: 1XXXXX11

binary, where the Xs denote the particular channel

and conversion mode selected.

2) Use a general-purpose I/O line on the CPU to pull

CS low.

3) Transmit TB1 and, simultaneously, receive a byte

and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 hex) and, simulta-

neously, receive byte RB2.

5) Transmit a byte of all zeros ($00 hex) and, simulta-

neously, receive byte RB3.

6) Pull CS high.

Figure 6 shows the timing for this sequence. Bytes RB2

and RB3 contain the result of the conversion, padded

with one leading zero, two sub-LSB bits, and three trail-

ing zeros. The total conversion time is a function of the

serial-clock frequency and the amount of idle time

between 8-bit transfers. To avoid excessive T/H droop,

make sure the total conversion time does not exceed

120µs.

Digital Output

In unipolar input mode, the output is straight binary

(Figure 17). For bipolar input mode, the output is twos

complement (Figure 18). Data is clocked out at the

falling edge of SCLK in MSB-first format.

Clock Modes

The MAX148/MAX149 may use either an external

serial clock or the internal clock to perform the succes-

sive-approximation conversion. In both clock modes,

the external clock shifts data in and out of the

SSTRB

SCLK

DIN

DOUT

1 4 8 12 16 20 24

START

SEL2 SEL1 SEL0 UNI/

BIP SGL/

DIF PD1 PD0

MSB B8 B7 B6 B5 B4 B3 B2 B1 S0S1

LSB

ACQUISITION

(fSCLK = 2MHz)

IDLE

FILLED WITH

ZEROS

IDLE

CONVERSION

tACQ

A/D STATE

RB1 RB2 RB3

1.5µs

Figure 6. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with fSCLK

≤

2MHz)

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

0 0 0 + –

0 0 1 + –

0 1 0 + –

0 1 1 + –

1 0 0 – +

1 0 1 – +

1 1 0 – +

1 1 1 – +

Table 3. Channel Selection in Differential Mode (SGL/DDIIFF= 0)

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

12 ______________________________________________________________________________________

MAX148/MAX149. The T/H acquires the input signal as

the last three bits of the control byte are clocked into

DIN. Bits PD1 and PD0 of the control byte program the

clock mode. Figures 7–10 show the timing characteris-

tics common to both modes.

External Clock

In external clock mode, the external clock not only shifts

data in and out, but it also drives the analog-to-digital

conversion steps. SSTRB pulses high for one clock

period after the last bit of the control byte. Succes-

sive-approximation bit decisions are made and appear

at DOUT on each of the next 12 SCLK falling edges

(Figure 6). SSTRB and DOUT go into a high-impedance

state when CS goes high; after the next CS falling edge,

SSTRB outputs a logic low. Figure 8 shows the SSTRB

timing in external clock mode.

The conversion must complete in some minimum time,

or droop on the sample-and-hold capacitors may

degrade conversion results. Use internal clock mode if

the serial-clock frequency is less than 100kHz, or if

serial-clock interruptions could cause the conversion

interval to exceed 120µs.

Internal Clock

In internal clock mode, the MAX148/MAX149 generate

their own conversion clocks internally. This frees the µP

• • •

• • • • • •

• • •

tSDV

tSSTRB

PD0 CLOCKED IN

tSTR

SSTRB

SCLK

tSSTRB

• • • • • • •

•

Figure 8. External Clock Mode SSTRB Detailed Timing

• • •

SCLK

DIN

DOUT

tCSH tCSS tCL

tDS tDH

tDV

tCH

tDO tTR

tCSH

Figure 7. Detailed Serial-Interface Timing

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

______________________________________________________________________________________ 13

from the burden of running the SAR conversion clock

and allows the conversion results to be read back at the

processor’s convenience, at any clock rate from 0MHz

to 2MHz. SSTRB goes low at the start of the conversion

and then goes high when the conversion is complete.

SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),

during which time SCLK should remain low for best

noise performance.

An internal register stores data when the conversion is

in progress. SCLK clocks the data out of this register at

any time after the conversion is complete. After SSTRB

goes high, the next falling clock edge produces the

MSB of the conversion at DOUT, followed by the

remaining bits in MSB-first format (Figure 9). CS does

not need to be held low once a conversion is started.

Pulling CS high prevents data from being clocked into

the MAX148/MAX149 and three-states DOUT, but it

does not adversely affect an internal clock mode con-

version already in progress. When internal clock mode

is selected, SSTRB does not go into a high-

impedance state when CS goes high.

Figure 10 shows the SSTRB timing in internal clock

mode. In this mode, data can be shifted in and out of

the MAX148/MAX149 at clock rates exceeding 2.0MHz if

the minimum acquisition time (tACQ) is kept above 1.5µs.

Data Framing

The falling edge of CS does not start a conversion.

The first logic high clocked into DIN is interpreted as a

start bit and defines the first bit of the control byte. A

conversion starts on SCLK’s falling edge, after the eighth

SSTRB

SCLK

DIN

DOUT

1 4 8 12 18 20 24

START

SEL2 SEL1 SEL0 UNI/

BIP SGL/

DIF PD1 PD0

MSB B8 B7 S0S1

LSB FILLED WITH

ZEROS

IDLE

CONVERSION

7.5µs MAX

(SHDN = FLOAT)

2 3 5 6 7 9 10 11 19 21 22 23

tCONV

ACQUISITION

(fSCLK = 2MHz)

IDLE

A/D STATE 1.5µs

Figure 9. Internal Clock Mode Timing

PD0 CLOCK IN

tSSTRB

tCSH

tCONV

tSCK

SSTRB

SCLK

DOUT

tCSS

tDO

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

Figure 10. Internal Clock Mode SSTRB Detailed Timing

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

14 ______________________________________________________________________________________

bit of the control byte (the PD0 bit) is clocked into DIN.

The start bit is defined as follows:

The first high bit clocked into DIN with CS low any

time the converter is idle; e.g., after V DD is applied.

The first high bit clocked into DIN after bit 3 of a con-

version in progress is clocked onto the DOUT pin.

If CS is toggled before the current conversion is com-

plete, the next high bit clocked into DIN is recognized as

a start bit; the current conversion is terminated, and a

new one is started.

The fastest the MAX148/MAX149 can run with CS held

low between conversions is 15 clocks per conversion.

Figure 11a shows the serial-interface timing necessary to

perform a conversion every 15 SCLK cycles in external

clock mode. If CS is tied low and SCLK is continuous,

guarantee a start bit by first clocking in 16 zeros.

Most microcontrollers (µCs) require that conversions

occur in multiples of 8 SCLK clocks; 16 clocks per con-

version is typically the fastest that a µC can drive the

MAX148/MAX149. Figure 11b shows the serial-

interface timing necessary to perform a conversion every

16 SCLK cycles in external clock mode.

__________ Applications Information

Power-On Reset

When power is first applied, and if SHDN is not pulled

low, internal power-on reset circuitry activates the

MAX148/MAX149 in internal clock mode, ready to con-

vert with SSTRB = high. After the power supplies stabi-

lize, the internal reset time is 10µs, and no conversions

should be performed during this phase. SSTRB is high

on power-up and, if CS is low, the first logical 1 on DIN

is interpreted as a start bit. Until a conversion takes

place, DOUT shifts out zeros. (Also see Table 4.)

Reference-Buffer Compensation

In addition to its shutdown function, SHDN selects inter-

nal or external compensation. The compensation

affects both power-up time and maximum conversion

speed. The100kHz minimum clock rate is limited by

droop on the sample-and-hold and is independent of

the compensation used.

Float SHDN to select external compensation. The

Typical Operating Circuit

uses a 4.7µF capacitor at

VREF. A 4.7µF value ensures reference-buffer stability

and allows converter operation at the 2MHz full clock

speed. External compensation increases power-up

time (see the

Choosing Power-Down Mode

section and

Table 4).

Pull SHDN high to select internal compensation.

Internal compensation requires no external capacitor at

VREF and allows for the shortest power-up times. The

maximum clock rate is 2MHz in internal clock mode

and 400kHz in external clock mode.

Choosing Power-Down Mode

You can save power by placing the converter in a low-

current shutdown state between conversions. Select full

power-down mode or fast power-down mode via bits 1

and 0 of the DIN control byte with SHDN high or floating

(Tables 1 and 5). In both software power-down modes,

the serial interface remains operational, but the ADC

does not convert. Pull SHDN low at any time to shut

down the converter completely. SHDN overrides bits 1

and 0 of the control byte.

Full power-down mode turns off all chip functions that

draw quiescent current, reducing supply current to 2µA

(typ). Fast power-down mode turns off all circuitry

except the bandgap reference. With fast power-down

mode, the supply current is 30µA. Power-up time can be

shortened to 5µs in internal compensation mode.

Table 4 shows how the choice of reference-buffer com-

pensation and power-down mode affects both power-up

REFERENCE

BUFFER

REFERENCE-

BUFFER

COMPENSATION

MODE

VREF

CAPACITOR

(µF)

POWER-DOWN

MODE

POWER-UP

DELAY

(µs)

MAXIMUM

SAMPLING RATE

(ksps)

Enabled Internal — Fast 5 26

Enabled Internal — Full 300 26

Enabled External 4.7 Fast See Figure 14c 133

Enabled External 4.7 Full See Figure 14c 133

Disabled — — Fast 2 133

Disabled — — Full 2 133

Table 4. Typical Power-Up Delay Times

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

______________________________________________________________________________________ 15

delay and maximum sample rate. In external compensa-

tion mode, power-up time is 20ms with a 4.7µF compen-

sation capacitor when the capacitor is initially fully

discharged. From fast power-down, start-up time can be

eliminated by using low-leakage capacitors that do not

discharge more than 1/2LSB while shut down. In power-

down, leakage currents at VREF cause droop on the ref-

erence bypass capacitor. Figures 12a and 12b show

the various power-down sequences in both external and

internal clock modes.

SCLK

DIN

DOUT

S CONTROL BYTE 0 CONTROL BYTE 1S

CONVERSION RESULT 0

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

CONVERSION RESULT 1

SSTRB

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

CONTROL BYTE 2S

18 115 158 1

Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing

SCLK

DIN

DOUT

1 8 16 1 8 16

CONTROL BYTE 0 CONTROL BYTE 1S

CONVERSION RESULT 0

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 B9 B8 B7 B6

CONVERSION RESULT 1

• • •

Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing

POWERED UP HARDWARE

POWER-

DOWN POWERED UP

POWERED UP

10 + 2 DATA BITS 10 + 2 DATA BITS INVALID

DATA

VALID

DATA

EXTERNAL

SXXXXX1 1 S 0 0

X XXXX X X X X X

S 1 1

SOFTWARE

POWER-DOWN

MODE

DOUT

DIN

CLOCK

MODE

SHDN SETS EXTERNAL

CLOCK MODE SETS EXTERNAL

CLOCK MODE

SETS SOFTWARE

POWER-DOWN

Figure 12a. Timing Diagram Power-Down Modes, External Clock

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

16 ______________________________________________________________________________________

Table 6. Hard-Wired Power-Down

and Internal Clock Frequency

PD1 PD0 DEVICE MODE

0 0 Full Power-Down

0 1 Fast Power-Down

1 0 Internal Clock

1 1 External Clock

Table 5. Software Power-Down

and Clock Mode

Figure 13. Average Supply Current vs. Conversion Rate with

External Reference

1000

10,000

0.10.1

AVERAGE SUPPLY CURRENT

vs. CONVERSION RATE

WITH EXTERNAL REFERENCE

100

CONVERSION RATE (Hz)

AVERAGE SUPPLY CURRENT (µA)

1 10010 1k 10k 1M100k

MAX148/9-13

VREF = VDD = 3.0V

RLOAD = ∞

CODE = 1010101000

1 CHANNEL

8 CHANNELS

Figure 14a. MAX149 Supply Current vs. Conversion Rate,

FULLPD

100

10.01 0.1 1

AVERAGE SUPPLY CURRENT

vs. CONVERSION RATE

(USING FULLPD)

CONVERSION RATE (Hz)

AVERAGE SUPPLY CURRENT (µA)

10010 1k

MAX148/9-F14A

RLOAD = ∞

CODE = 1010101000

8 CHANNELS

1 CHANNEL

POWER-DOWN POWERED UP

POWERED UP

DATA VALID DATA VALID

INTERNAL

SXXXXX1 0 S 0 0

X XXXX S

MODE

DOUT

DIN

CLOCK

MODE SETS INTERNAL

CLOCK MODE SETS

POWER-DOWN

CONVERSION

SSTRB

Figure 12b. Timing Diagram Power-Down Modes, Internal Clock

N/AN/APower-Down0 1.8MHzExternalEnabledFloating 225kHzInternalEnabled1

INTERNAL

CLOCK

FREQUENCY

REFERENCE-

BUFFER

COMPENSATION

DEVICE

MODE

SHDN

STATE

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

______________________________________________________________________________________ 17

Software Power-Down

Software power-down is activated using bits PD1 and PD0

of the control byte. As shown in Table 5, PD1 and PD0

also specify the clock mode. When software shutdown is

asserted, the ADC operates in the last specified clock

mode until the conversion is complete. Then the ADC

powers down into a low quiescent-current state. In internal

clock mode, the interface remains active and conversion

results may be clocked out after the MAX148/MAX149

enter a software power-down.

The first logical 1 on DIN is interpreted as a start bit

and powers up the MAX148/MAX149. Following

the start bit, the data input word or control byte also

determines clock mode and power-down states. For

example, if the DIN word contains PD1 = 1, then the

chip remains powered up. If PD0 = PD1 = 0, a

power-down resumes after one conversion.

Hardware Power-Down

Pulling SHDN low places the converter in hardware

power-down (Table 6). Unlike software power-down

mode, the conversion is not completed; it stops coin-

cidentally with SHDN being brought low. SHDN also

controls the clock frequency in internal clock mode.

Letting SHDN float sets the internal clock frequency to

1.8MHz. When returning to normal operation with SHDN

floating, there is a tRC delay of approximately 2MΩx CL,

where CLis the capacitive loading on the SHDN pin.

Pulling SHDN high sets internal clock frequency to

225kHz. This feature eases the settling-time requirement

for the reference voltage. With an external reference, the

MAX148/MAX149 can be considered fully powered up

within 2µs of actively pulling SHDN high.

Power-Down Sequencing

The MAX148/MAX149 auto power-down modes can

save considerable power when operating at less than

maximum sample rates. Figures 13, 14a, and 14b show

the average supply current as a function of the sam-

pling rate. The following discussion illustrates the vari-

ous power-down sequences.

Lowest Power at up to 500

Conversions/Channel/Second

The following examples show two different power-down

sequences. Other combinations of clock rates, compen-

sation modes, and power-down modes may give lowest

power consumption in other applications.

Figure 14a depicts the MAX149 power consumption for

one or eight channel conversions utilizing full power-

down mode and internal-reference compensation. A

0.01µF bypass capacitor at REFADJ forms an RC filter

with the internal 20kΩreference resistor with a 0.2ms

time constant. To achieve full 10-bit accuracy, 8 time

constants or 1.6ms are required after power-up.

Waiting this 1.6ms in FASTPD mode instead of in full

power-up can reduce power consumption by a factor

of 10 or more. This is achieved by using the sequence

shown in Figure 15.

10,000

10.1 1

AVERAGE SUPPLY CURRENT

vs. CONVERSION RATE

(USING FASTPD)

1000

100

CONVERSION RATE (Hz)

AVERAGE SUPPLY CURRENT (µA)

100 1M10 1k 10k 100k

MAX148/9-F14B

RLOAD = ∞

CODE = 1010101000

8 CHANNELS

1 CHANNEL

Figure 14c. Typical Reference-Buffer Power-Up Delay vs. Time

in Shutdown

2.0

0.001 0.01 0.1 1 10

TYPICAL REFERENCE-BUFFER POWER-UP

DELAY vs. TIME IN SHUTDOWN

1.5

1.0

0.5

TIME IN SHUTDOWN (sec)

POWER-UP DELAY (ms)

MAX148/9-F14C

Figure 14b. MAX149 Supply Current vs. Conversion Rate,

FASTPD

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

18 ______________________________________________________________________________________

Lowest Power at Higher Throughputs

Figure 14b shows the power consumption with

external-reference compensation in fast power-down,

with one and eight channels converted. The external

4.7µF compensation requires a 75µs wait after

power-up with one dummy conversion. This graph

shows fast multi-channel conversion with the lowest

power consumption possible. Full power-down mode

may provide increased power savings in applications

where the MAX148/MAX149 are inactive for long peri-

ods of time, but where intermittent bursts of high-speed

conversions are required.

Internal and External References

The MAX149 can be used with an internal or external

reference voltage, whereas an external reference is

required for the MAX148. An external reference can be

connected directly at VREF or at the REFADJ pin.

An internal buffer is designed to provide 2.5V at

VREF for both the MAX149 and the MAX148. The

MAX149’s internally trimmed 1.21V reference is buf-

fered with a 2.06 gain. The MAX148’s REFADJ pin is

also buffered with a 2.00 gain to scale an external 1.25V

reference at REFADJ to 2.5V at VREF.

Internal Reference (MAX149)

The MAX149’s full-scale range with the internal refer-

ence is 2.5V with unipolar inputs and ±1.25V with bipo-

lar inputs. The internal reference voltage is adjustable

to ±1.5% with the circuit in Figure 16.

External Reference

With both the MAX149 and MAX148, an external refer-

ence can be placed at either the input (REFADJ) or the

output (VREF) of the internal reference-buffer amplifier.

The REFADJ input impedance is typically 20kΩfor the

MAX149, and higher than 100kΩfor the MAX148. At

OUTPUT CODE

FULL-SCALE

TRANSITION

11 . . . 111

11 . . . 110

11 . . . 101

00 . . . 011

00 . . . 010

00 . . . 001

00 . . . 000 1 2 3

(COM) FS

FS - 3/2LSB

FS = VREF + COM

ZS = COM

INPUT VOLTAGE (LSB)

1LSB = VREF

1024

Figure 17. Unipolar Transfer Function, Full Scale (FS) = VREF

+ COM, Zero Scale (ZS) = COM

+3.3V

510k

24k

100k

0.01µF

12 REFADJ

MAX149

Figure 16. MAX149 Reference-Adjust Circuit

1 0 0

DIN

REFADJ

VREF

1.21V

2.50V

1 0 1 1 11 1 0 0 1 0 1

FULLPD FASTPD NOPD FULLPD FASTPD

1.6ms WAIT

COMPLETE CONVERSION SEQUENCE

tBUFFEN ≈ 75µs

τ = RC = 20kΩ x CREFADJ

(ZEROS) CH1 CH7 (ZEROS)

Figure 15. MAX149 FULLPD/FASTPD Power-Up Sequence

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

______________________________________________________________________________________ 19

VREF, the DC input resistance is a minimum of 18kΩ.

During conversion, an external reference at VREF must

deliver up to 350µA DC load current and have 10Ωor

less output impedance. If the reference has a higher

output impedance or is noisy, bypass it close to the

VREF pin with a 4.7µF capacitor.

Using the REFADJ input makes buffering the external

reference unnecessary. To use the direct VREF input,

disable the internal buffer by tying REFADJ to VDD. In

power-down, the input bias current to REFADJ is typi-

cally 25µA (MAX149) with REFADJ tied to VDD. Pull

REFADJ to AGND to minimize the input bias current in

power-down.

Transfer Function

Table 7 shows the full-scale voltage ranges for unipolar

and bipolar modes.

The external reference must have a temperature coeffi-

cient of 20ppm/°C or less to achieve accuracy to within

1LSB over the 0°C to +70°C commercial temperature

range.

Figure 17 depicts the nominal, unipolar input/output

(I/O) transfer function, and Figure 18 shows the bipolar

input/output transfer function. Code transitions occur

halfway between successive-integer LSB values.

Output coding is binary, with 1LSB = 2.44mV (2.500V /

1024) for unipolar operation, and 1LSB = 2.44mV

[(2.500V / 2 - -2.500V / 2) / 1024] for bipolar operation.

011 . . . 111

011 . . . 110

000 . . . 010

000 . . . 001

000 . . . 000

111 . . . 111

111 . . . 110

111 . . . 101

100 . . . 001

100 . . . 000

- FS COM*

INPUT VOLTAGE (LSB)

OUTPUT CODE

ZS = COM

+FS - 1LSB

*COM VREF / 2

+ COM

FS = VREF

-FS = + COM

-VREF

1LSB = VREF

1024

≤

Figure 18. Bipolar Transfer Function, Full Scale (FS) =

VREF / 2 + COM, Zero Scale (ZS) = COM

+3V +3V GND

SUPPLIES

DGND+3VDGNDCOM

AGNDVDD

DIGITAL

CIRCUITRY

MAX148

MAX149

R* = 10Ω

*OPTIONAL

Figure 19. Power-Supply Grounding Connection

UNIPOLAR MODE BIPOLAR MODE

Full Scale Zero Scale Positive Zero Negative

Full Scale Scale Full Scale

VREF + COM COM VREF / 2 COM -VREF / 2

+ COM + COM

Table 7. Full Scale and Zero Scale

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

20 ______________________________________________________________________________________

Layout, Grounding, and Bypassing

For best performance, use printed circuit boards.

Wire-wrap boards are not recommended. Board layout

should ensure that digital and analog signal lines are

separated from each other. Do not run analog and digi-

tal (especially clock) lines parallel to one another, or

digital lines underneath the ADC package.

Figure 19 shows the recommended system ground

connections. Establish a single-point analog ground

(star ground point) at AGND, separate from the logic

ground. Connect all other analog grounds and DGND

to the star ground. No other digital system ground

should be connected to this ground. For lowest-noise

operation, the ground return to the star ground’s power

supply should be low impedance and as short as

possible.

High-frequency noise in the VDD power supply may

affect the high-speed comparator in the ADC. Bypass

the supply to the star ground with 0.1µF and 1µF

capacitors close to pin 20 of the MAX148/MAX149.

Minimize capacitor lead lengths for best supply-noise

rejection. If the power supply is very noisy, a 10Ωresis-

tor can be connected as a lowpass filter (Figure 19).

MAX148

MAX149 MC683XX

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

SHDN

VDD

SCLK

DIN

SSTRB

DOUT

DGND

AGND

REFADJ

VREF

(POWER SUPPLIES)

SCK

PCS0

MOSI

MISO

0.1µF1µF

(GND)

0.1µF

ANALOG

INPUTS

+3V

+2.5V

Figure 20. MAX148/MAX149 QSPI Connections, External Reference

CLKX

CLKR

FSR

SCLK

DIN

DOUT

SSTRB

TMS320LC3x MAX148

MAX149

Figure 21. MAX148/MAX149-to-TMS320 Serial Interface

High-Speed Digital Interfacing with QSPI

The MAX148/MAX149 can interface with QSPI using

the circuit in Figure 20 (fSCLK = 2.0MHz, CPOL = 0,

CPHA = 0). This QSPI circuit can be programmed to do a

conversion on each of the eight channels. The result is

stored in memory without taxing the CPU, since QSPI

incorporates its own microsequencer.

The MAX148/MAX149 are QSPI compatible up to the

maximum external clock frequency of 2MHz.

TMS320LC3x Interface

Figure 21 shows an application circuit to interface the

MAX148/MAX149 to the TMS320 in external clock mode.

The timing diagram for this interface circuit is shown in

Figure 22.

Use the following steps to initiate a conversion in the

MAX148/MAX149 and to read the results:

1) The TMS320 should be configured with CLKX

(transmit clock) as an active-high output clock and

CLKR (TMS320 receive clock) as an active-high

input clock. CLKX and CLKR on the TMS320 are

tied together with the MAX148/MAX149’s SCLK

input.

2) The MAX148/MAX149’s CS pin is driven low by the

TMS320’s XF_ I/O port to enable data to be clocked

into the MAX148/MAX149’s DIN.

3) An 8-bit word (1XXXXX11) should be written to the

MAX148/MAX149 to initiate a conversion and place

the device into external clock mode. Refer to Table

1 to select the proper XXXXX bit values for your

specific application.

4) The MAX148/MAX149’s SSTRB output is monitored

via the TMS320’s FSR input. A falling edge on the

SSTRB output indicates that the conversion is in

progress and data is ready to be received from the

MAX148/MAX149.

5) The TMS320 reads in one data bit on each of the

next 16 rising edges of SCLK. These data bits rep-

resent the 10 + 2-bit conversion result followed by

4 trailing bits, which should be ignored.

6) Pull CS high to disable the MAX148/MAX149 until

the next conversion is initiated.

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

______________________________________________________________________________________ 21

SCLK

DIN

SSTRB

DOUT

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

MSB B8 S1 S0 HIGH

IMPEDANCE

HIGH

IMPEDANCE

Figure 22. TMS320 Serial-Interface Timing Diagram

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

22 ______________________________________________________________________________________

TOP VIEW

DIP/SSOP

VDD

SCLK

DIN

SSTRB

DOUT

DGND

AGND

REFADJ

VREFSHDN

COM

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

MAX148

MAX149

__________________Pin Configuration

___________________Chip Information

TRANSISTOR COUNT: 2554

†

Contact factory for availability of alternate surface-mount

packages.

Contact factory for availability of CERDIP package, and for

processing to MIL-STD-883B.

Ordering Information (continued)

±1

±1/2

20 CERDIP*-55°C to +125°CMAX149BMJP

±1

20 CERDIP*-55°C to +125°C

±1/2

20 SSOP-40°C to +85°C

MAX149AMJP

MAX149BEAP 20 SSOP-40°C to +85°CMAX149AEAP ±1

±1/2

20 Plastic DIP-40°C to +85°CMAX149BEPP

±1

20 Plastic DIP-40°C to +85°C

±1/2

20 SSOP0°C to +70°C

±1

±1/2

MAX149AEPP

MAX149BCAP 20 SSOP

20 Plastic DIP

20 Plastic DIP0°C to +70°C

0°C to +70°C

0°C to +70°CMAX149ACAP

MAX149BCPP

MAX149ACPP ±1

±1/2

20 CERDIP*-55°C to +125°CMAX148BMJP 20 CERDIP*-55°C to +125°CMAX148AMJP ±1

±1/2

20 SSOP-40°C to +85°C

±1

±1/2

INL

(LSB)

MAX148BEAP 20 SSOP

20 Plastic DIP

PIN-PACKAGETEMP. RANGE

-40°C to +85°C

-40°C to +85°CMAX148AEAP

MAX148BEPP

MAX148AEPP

PART†

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

______________________________________________________________________________________ 23

________________________________________________________Package Information

SSOP.EPS

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

MAX148/MAX149

+2.7V to +5.25V, Low-Power, 8-Channel,

Serial 10-Bit ADCs

PDIPN.EPS

___________________________________________Package Information (continued)