applications requiring very high speed operations. The RapidS serial interface is SPI compatible for frequencies up to 66MHz.

page in the main memory is being reprogrammed, as well as the writing of a continuous data stream. EEPROM (electrically

erasable and programmable read-only memory) emulation (bit or byte alterability) is easily handled with a self-contained, 

three-step read-modify-write operation. Unlike conventional flash memories, which are accessed randomly with multiple

simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability,

Figure 1-1. Pin configurations and pinouts.

are contained in Table 13-1 on page 24 through Table 13-7 on page 27. A valid instruction starts with the falling edge of CS,

toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI

terminology BFA8 - BFA0 to denote the nine address bits required to designate a byte address within a buffer. Main memory

addressing is referenced using the terminology A21 - A0, where A21 - A9 denotes the 13 address bits required to designate a

page address and A8 - A0 denotes the nine address bits required to designate a byte address within a page.

By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers.

Waveform – RapidS Serial Interface Mode 0/Mode 3 diagrams in this datasheet for details on the clock cycle sequences for

each mode.

By supplying an initial starting address for the main memory array, the continuous array read command can be utilized to

to read, and the last 10 bits (BA9 - BA0) of the 23-bit address sequence specify the starting byte address within the page. To

perform a continuous read from the binary page size (512-bytes), the opcode (E8H) must be clocked into the device followed by

three address bytes and four don’t care bytes. The first 13 bits (A21 - A9) of the 22-bit sequence specify which page of the main

memory array to read, and the last 9 bits (A8 - A0) of the 22-bit address sequence specify the starting byte address within the

page. The don’t care bytes that follow the address bytes are needed to initialize the read operation. Following the don’t care

When the end of a page in main memory is reached during a continuous array read, the device will continue reading at the

beginning of the next page, with no delays incurred during the page boundary crossover (the crossover from the end of one

page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue

This command can be used with the serial interface to read the main memory array sequentially in high-speed mode for any

clock frequency up to the maximum specified by fCAR1. To perform a continuous read array with the page size set to 528 bytes,

CS must first be asserted, and then a 0BH opcode must be clocked into the device, followed by three address bytes and a

dummy byte. The first 13 bits (PA12 - PA0) of the 23-bit address sequence specify which page of the main memory array to

perform a continuous read with the page size set to 512 bytes, the 0BH opcode must be clocked into the device, followed by

three address bytes (A21 - A0) and a dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result

in data being output on the SO (serial output) pin.

beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at

first be asserted, and then a 03H opcode must be clocked into the device, followed by three address bytes (which comprise the

address within the page. To perform a continuous read with the page size set to 512 bytes, the 03H opcode must be clocked

into the device, followed by three address bytes (A21 - A0). Following the address bytes, additional clock pulses on the SCK pin

will result in data being output on the SO (serial output) pin.

next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning

both of the data buffers and leaving the contents of the buffers unchanged. To start a page read from the standard DataFlash

page size (528 bytes), an opcode of D2H must be clocked into the device, followed by three address bytes (which comprise the

the starting byte address within that page. To start a page read from the binary page size (512 bytes), the D2H opcode must be

clocked into the device, followed by three address bytes and four don’t care bytes. The first 13 bits (A21 - A9) of the 22-bit

sequence specify which page of the main memory array to read, and the last 9 bits (A8 - A0) of the 22-bit address sequence

specify the starting byte address within the page. The don’t care bytes that follow the address bytes are sent to initialize the

read operation. Following the don’t care bytes, additional pulses on SCK result in data being output on the SO (serial output)

The SRAM data buffers can be accessed independently of the main memory array, and utilizing the buffer read command

allows data to be sequentially read directly from the buffers. Four opcodes, D4H or D1H for buffer 1 and D6H or D3H for buffer

used to read data from the buffer. The D4H and D6H opcodes can be used at any SCK frequency, up to the maximum specified

To perform a buffer read from the standard DataFlash buffer (528 bytes), the opcode must be clocked into the device, followed

by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0). To perform a buffer read from

the binary buffer (512 bytes), the opcode must be clocked into the device, followed by three address bytes comprised of 15

don’t care bits and 9 buffer address bits (BFA8 - BFA0). Following the address bytes, one don’t care byte must be clocked in to

address bits (BFA8 - BFA0). The nine buffer address bits specify the first byte in the buffer to be written. After the last address

byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If the end of the data buffer is

reached, the device will wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer until a

low-to-high transition is detected on the CS pin.

Data written into either buffer 1 or buffer 2 can be programmed into the main memory. A 1-byte opcode, 83H for buffer 1 or 86H

for buffer 2, must be clocked into the device. For the standard DataFlash page size (528 bytes), the opcode must be followed by

three address bytes consist of 1 don’t care bit, 13 page address bits (PA12 - PA0) that specify the page in the main memory to

be written, and 10 don’t care bits. To perform a buffer to main memory page program with built-in erase for the binary page size

A previously-erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. A one-byte

opcode, 88H for buffer 1 or 89H for buffer 2, must be clocked into the device. For the standard DataFlash page size (528 bytes),

specify the page in the main memory to be written, and 10 don’t care bits. To perform a buffer to main memory page program

without built-in erase for the binary page size (512 bytes), the 88H opcode for buffer 1 or 89H opcode for buffer 2 must be

clocked into the device, followed by three address bytes consisting of 2 don’t care bits, 13 page address bits (A21 - A9) that

specify the page in the main memory to be written, and 9 don’t care bits. When a low-to-high transition occurs on the CS pin, the

part will program the data stored in the buffer into the specified page in the main memory. It is necessary that the page in main

memory being programmed has been previously erased using one of the erase commands (page erase or block erase). The

Deasserting the CS pin will terminate the read sector lockdown register operation and put the SO pin into a high-impedance

that the device is busy. If the device is powered down during the program cycle, then the contents of the 64-byte user

programmable portion of the security register cannot be guaranteed.

cannot be guaranteed. For example, if only the first two bytes are clocked in instead of the complete 64 bytes, then the

64 bytes of data are clocked into the device, then the data will wrap back around to the beginning of the register. For instance, if

The user programmable portion of the security register can be programmed only once. Therefore, it is not possible to program

The security register can be read by first asserting the CS pin and then clocking in an opcode of 77H, followed by three dummy

size (512 bytes), the 53H opcode for buffer 1 or 55H opcode for buffer 2 must be clocked into the device, followed by three

bytes from the input pin (SI). The transfer of page of data from the main memory to the buffer will begin when the CS pin

transitions from a low to a high state. During the transfer of a page of data (tXFR), the status register can be read or the

DataFlash page size (528 bytes), a one-byte opcode, 60H for buffer 1 or 61H for buffer 2, must be clocked into the device,

followed by three address bytes consisting of 1 don’t care bit, 13 page address bits (PA12 - PA0) that specify the page in the

main memory that is to be compared to the buffer, and 10 don’t care bits. To start a main memory page to buffer compare for a

binary page size (512 bytes), the 60H opcode for buffer 1 or 61H opcode for buffer 2 must be clocked into the device, followed

by three address bytes consisting of 2 don’t care bits, 13 page address bits (A21 - A9) that specify the page in the main memory

that is to be compared to the buffer, and 9 don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode

A page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer

2) are programmed back into their original page of main memory. To start the rewrite operation for the standard DataFlash page

size (528 bytes), a one-byte opcode, 58H for buffer 1 or 59H for buffer 2, must be clocked into the device, followed by three

address bytes comprised of 1 don’t care bit, 13 page address bits (PA12-PA0) that specify the page in main memory to be

rewritten, and 10 don’t care bits. To initiate an auto page rewrite for a binary page size (512 bytes), the 58H opcode for buffer 1

or 59H opcode for buffer 2 must be clocked into the device, followed by three address bytes consisting of 2 don’t care bits, 13

page address bits (A21 - A9) that specify the page in the main memory that is to be written, and 9 don’t care bits. When a low-

program the data from the buffer back into same page of main memory. The operation is internally self-timed, and should take

pin (SO), starting with the next clock cycle. The data in the status register, starting with the msb (bit 7), will be clocked out on the

SO pin during the next eight clock cycles. After the one byte of the status register has been clocked out, the sequence will

Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a one, then the device is not busy and is ready to

updated, the user must toggle the SCK pin to check the ready/busy status.

There are several operations that can cause the device to be in a busy state:

either by the software-controlled or hardware-controlled method. A logic one indicates that sector protection has been enabled,

and logic zero indicates that sector protection has been disabled.

bit 0 is a zero, then the page size is set to 528 bytes.

The device density is indicated using bits 5, 4, 3, and 2 of the status register. For the AT45DB321D, the four bits are 1101. The

Table 9-1. Status Register Format

into the lowest power-consumption mode. To enter the deep power-down mode, the CS pin must first be asserted. Once the CS

The resume from deep power-down command takes the device out of the deep power-down mode and returns it to the normal

standby mode. To resume from deep power-down mode, the CS pin must first be asserted, and an opcode of ABH must be

clocked in via the input pin (SI). After the last bit of the command has been clocked in, the CS pin must be deasserted to

terminate the deep power-down mode. After the CS pin is deasserted, the device will return to the normal standby mode within

After resuming from deep power-down, the device will return to the normal standby mode.

the main memory to be configured for binary page size (512 bytes) or standard DataFlash page size (528 bytes). The power of

two page size is a one-time programmable configuration register, and once the device is configured for power of two page size,

it cannot be reconfigured again. The devices are initially shipped with the page size set to 528 bytes. The user has the option of

ordering binary page size (512-byte) devices from the factory. For details, please refer to Section 24., “Ordering Information” on

If the above steps to set the page size prior to page programming are not followed, incorrect data during a read operation may

be encountered.

any other command. Once the CS pin has been asserted, the appropriate four-byte opcode sequence must be clocked into the

device in the correct order. The four-byte opcode sequence must start with 3DH, followed by 2AH, 80H, and A6H. After the last

bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program

cycle. The programming of the configuration register should take place in a maximum time of tP, during which time the status

register will indicate that the device is busy. The device must be power cycled after the completion of the program cycle to set

in the system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and

from the device includes the JEDEC-defined manufacturer ID, the vendor-specific device ID, and the vendor-specific extended

device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the

subsequent clock cycles. The first byte to be output will be the manufacturer ID, followed by two bytes of device ID information.

The fourth byte output will be the extended device information string length, which will be 00H to indicate that no extended

Note: 1. These legacy commands are not recommended for new designs.