AS8ERLC128K32SQ-250/883C - Micross Components, Inc.

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

GENERAL DESCRIPTION

The Austin Semiconductor , Inc. AS8ERLC128K32 is a 4 Mega-

bit Radiation Tolerant EEPROM Module organized as 128K x 32 bit.

User configurable to 256K x16 or 512Kx 8. The module achieves high

speed access, low power consumption and high reliability by

employing advanced CMOS memory technology.

The military grade product is manufactured in compliance to

MIL-STD 883, making the AS8ERLC128K32 ideally suited for mili-

tary or space applications.

The module is offered as a 68 lead 0.880 inch square ceramic

quad flat pack. It has a max. height of 0.200 inch (non-shielded). This

package design is targeted for those applications which require low

profile SMT Packaging.

* contact factory for test reports. ASI does not guarantee or warrant

these performance levels, but references these third party reports.

FEATURES

•Access time of 250ns , 300ns

• Operation with single 3.3V (+ .3V) supply

• LOW Power Dissipation:

Active(Worst case): 300mW (MAX), Max Speed Operation

Standby(Worst case): 7.2mW(MAX), Battery Back-up Mode

• Automatic Byte Write: 15 ms (MAX)

• Automatic Page Write (128 bytes): 15 ms (MAX)

• Data protection circuit on power -on/off

• Low power CMOS MONOS cell Technology

•10

4 Erase/Write cycles (in Page Mode)

• Software data protection

• TTL Compatible Inputs and Outputs

• Data Retention: 10 years

• Ready/Busy\ and Data Polling Signals

• Write protection by RES\ pin

• Radiation Tolerant: Proven total dose 40K to 100K RADS*

• Shielded Package for Best Radiation Immunity

• Operating T emperature Ranges:

Military: -55oC to +125oC

Industrial: -40oC to +85oC

OPTIONS MARKINGS

• Timing

150 ns -150

200 ns -200

250 ns -250

• Package

Ceramic Quad Flat pack w/ formed leads Q No. 703Q

Ceramic Quad Flat pack w/ tie bar QB No. 703QB

Shielded Ceramic Quad Flat pack SQ No. 703SF

Shielded Ceramic Quad Flat pack SQB No. 703SQB

AVAILABLE AS MILIT AR Y SPECIFICATIONS

•MIL-STD-883, para 1.2.1 compliant

• SPACE Level Process Flow

PIN ASSIGNMENT

(Top View)

68 Lead CQFP

128K x 32 Radiation T olerant EEPROM

For more products and information

please visit our web site at

www.austinsemiconductor.com

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

GND

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

RES\

CS3\

GND

CS4\

WE1\

A10

Vcc

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Vcc

A11

A12

A13

*A15

*A14

A16

CS1\

OE\

CS2\

WE2\

WE3\

WE4\

RDY

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

GND

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

PIN NAME

FUNCTION

A0 to A16 Address Input

I/O0 to I/O31 Data Input/Output

OE\ Output Enable

CE\ Chip Enable

WE\ Write Enable

VCC Power Supply

VSS Ground

RDY/BUSY\ Ready Busy

RES\ Reset

FUNCTIONAL BLOCK DIAGRAM

*Pin #'s 31 and 32, A15 and A14 respectively, are reversed from the AS8E128K32. Correct

use of these address lines is required for operation of the SDP mode to work properly.

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

NOTES: 1. RDY/Busy\ output has only active LOW VOL and high impedance state. It can not go to HIGH (VOH) state.

2. VCC - 0.5V < VH < VCC+0.5V

3. X : DON'T CARE

TRUTH TABLE

MODE CE\ OE\ WE\ RES\ RDY/BUSY\

I/O

Read V

High-Z Dout

Standby V

X X High-Z High-Z

Write V

High-Z to V

Din

Deselect V

High-Z High-Z

X --- ---

X X --- ---

Data\ Polling V

Dout (I/O7)

Program Reset X X X V

High-Z High-Z

Wirte Inhibit

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

*Stresses greater than those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the

operation section of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods

may affect reliability .

**Junction temperature depends upon package type, cycle time,

loading, ambient temperature and airflow, and humidity

(plastics).

ABSOLUTE MAXIMUM RATINGS*

Voltage on Vcc Supply Relative to Vss

Vcc ....................................................................-0.6V to +5.0V

Operating Temperature Range(1) ..................-55°C to +125°C

Storage Temperature Range .........................-65°C to +150°C

Voltage on any Pin Relative to Vss..............-0.5V to +5.0V (2)

Max Junction Temperature**.......................................+150°C

Thermal Resistance junction to case (θJC):

Package T ype Q...........................................11.3° C/W

Package Type P & PN..................................2.8° C/W

NOTES:

1) Including electrical characteristics and data retention.

2) VIN MIN = -1.0V for pulse width < 20ns.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(-55oC<TA<125oC or -40oC to +85oC; Vcc = 3.3V +/-.3V)

NOTE: 1) VIL (MIN): -1.0V for pulse width < 20ns.

2) All other Signal pins except RES\

PARAMETE

CONDITIONS SYMBOL MIN MA

UNITS

Input High Voltage V

2.2 V

+0.3 V

Input High Voltage (RES\) V

-0.5 V

+.5 V

Input Low Voltage V

-0.3

0.8 V

LOW INPUT Leakage(RES\ Signal) RES\=0V, VCC=3.6V I

(RES) -500 P$

HIGH INPUT Leakage(RES\ Signal) RES\=3.6V, VCC=3.6V I

(RES) 10 P$

INPUT LEAKAGE CURRENT

OV < V

< V

-10 10 P$

OUTPUT LEAKAGE CURRENT

Outputs(s) Disabled,

OV < V

OUT

< V

-10 10 P$

Output High Voltage I

= -0.4mA V

VCCx.8 -- V

Output High Voltage I

= -0.1mA V

VCC-.0.3 -- V

Output Low Voltage I

= 2.1mA V

-- 0.4 V

Output Low Voltage I

= 0.1mA V

-- 0.2 V

Supply Voltage V

3 3.6 V

CONDITIONS SYM -250 -300 UNITS

Iout = 0mA, V

= 3.6V

Cycle = 1µS, Duty = 100% 30 30

Iout = 0mA, V

= 3.6V

Cycle = MIN, Duty = 100% 80 70

CE\ = V

CC,

= 3.6V I

CC1

0.2 0.2 mA

CE\ = V

IH,

= 3.6V I

CC2

44mA

Power Supply Current:

Standby

Icc3 mA

PARAMETE

Power Supply Current:

Operating

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

NOTE: 1. This parameter is guaranteed but not tested.

CAP ACIT ANCE T ABLE1 (VIN = 0V, f = 1 MHz, TA = 25oC , VCC=3.3V)

SYMBOL PARAMETER MAX

UNITS

CADD A0 - A16 Capacitance 40 pF

COE OE\, RES\, RDY Capacitance 40 pF

CWE, CCE WE\ and CE\ Capacitance 12 pF

CIO I/O 0- I/O 31 Capacitance 20 pF

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +.3V)

AC TEST CHARACTERISTICS

TEST SPECIFICA TIONS

Input pulse levels...........................................VSS to 3V

Input rise and fall times...........................................5ns

Input timing reference levels.................................1.5V

Output reference levels.........................................1.5V

Output load................................................See Figure 1

Current Source

Vz = 1.5V

(Bipolar

Supply)

Device

Under

Test

Ceff = 50pf

NOTES:

Vz is programmable from -2V to + 5V.

IOL and IOH programmable from 0 to 16 mA.

Vz is typically the midpoint of VOH and VOL.

IOL and IOH are adjusted to simulate a typical resistive load

circuit. Figure 1

MIN MA

Address to Output Delay CE\ = OE\ = VIL, WE\ = VIH t

ACC

250 300 ns

CE\ to Output Delay OE\ = VIL, WE\ = VIH t

250 300 ns

OE\ to Output Delay OE\ = VIL, WE\ = VIH t

10 120 10 130 ns

Address to Output Hold CE\ = OE\ = VIL, WE\ = VIH t

00ns

CE\ or OE\ high to Output Float (1) OE\ = VIL, WE\ = VIH t

0 50 0 50 ns

RES\ low to Output Float (1) CE\ = OE\ = VIL, WE\ = VIH t

DFR

0 350 0 350 ns

RES\ to Output Delay CE\ = OE\ = VIL, WE\ = VIH t

0 600 0 600 ns

-300

DESCRIPTION -250

SYMBOL UNITS

TEST CONDITIONS

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC WRITE CHARACTERISTICS

(-55oC < TA < +125oC; Vcc = 3.3V +.3V)

READ TIMING W A VEFORM

tACC

tCE

tOE

tOH

tDF

tDFR

tRR

HIGH-Z

ADDRESS

CE\

OE\

WE\

Data Out

RES\

DAT A OUT VALID

VIH

SYMBOL PARAMETER MIN

(2)

MAX UNITS

tAS Address Setup Time 0 ms

tAH Address Hold Time 150 ns

tCS CE\ to Write Setup Time (WE\ controlled) 0 ns

tCH CE\ Hold Time (WE\ controlled) 0 ns

tWS WE\ to Write Setup Time (CE\ controlled) 0 ns

tWH WE\ to Hold Time (CE\ controlled) 0 ns

tOES OE\ to Write Setup Time 0 ns

tOEH OE\ to Hold Time 0 ns

tDS Data Setup Time 100 ns

tDH Data Hold Time 10 ns

tWP WE\ Pulse Width (WE\ controlled) 250 ns

tCW CE\ Pulse Width (CE\ controlled) 250 ns

tDL Data Latch Time 750 ns

tBLC Byte Load Cycle 1 30 µs

tBL Byte Load Window 100 µs

tWC Write Cycle Time 15 (3) ms

tDB Time to Device Busy 150 ns

tDW Write Start Time 250 (4) ns

tRP Reset Protect Time 100 µs

tRES Reset High Time (5) 2µs

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

BYTE WRITE TIMING WAVEFORM (WE\ CONTROLLED)

BYTE WRITE TIMING WAVEFORM (CE\ CONTROLLED)

tRES

tRP

HIGH-Z

tOES

tAS

tCS tAH

tWC

tCH

tBL

tOEH

tWP

tDS tDH

tDB tDW

HIGH-Z

VCC

RES\

RDY/Busy\

Din

OE\

WE\

CE\

Address

VOL

tRES

tRP

HIGH-Z

tOES

tAS

tWS tAH tWC

tWH

tBL

tOEH

tCW

tDS tDH

tDB tDW

HIGH-Z

VCC

RES\

RDY/Busy\

Din

OE\

WE\

CE\

Address

VOL

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

PAGE WRITE TIMING WAVEFORM (WE\ CONTROLLED)

PA GE WRITE TIMING W AVEFORM (CE\ CONTROLLED)

HIGH-Z HIGH-Z

VCC

RES\

RDY/Busy\

Din

OE\

CE\

WE\

Address(6)

A0 to A16

tRES

tRP

tDB

tDS

tDH

tOES

tCS tCH tBLC

tDL

tWP

tAS tAH tBL

tWC

tOEH

tDW

HIGH-Z HIGH-Z

VCC

RES\

RDY/Busy\

Din

OE\

WE\

CE\

Address(6)

A0 to A16

tRES

tRP

tDB

tDS

tDH

tOES

tWS tWH tBLC

tDL

tCW

tAS tAH tBL

tWC

tOEH

tDW

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

DATA POLLING TIMING WAVEFORM

Din X Dout X Dout X

tOE(7)

tWC

tOEH

tCE(7)

tOES

tDW

Address

CE\

WE\

OE\

I\O7

NOTES:

1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven.

2. Use this device in longer cycle than this value.

3. tWC must be longer than this value unless polling techniques or RDY/Busy\ are used. This device automatically com-

pletes the internal write operation within this value.

4. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy\ are used.

5. This parameter is sampled and not 100% tested.

6. A7 to A16 are page addresses and must be same(i.e. Not Change) during the page write operation.

7. See AC read characteristics.

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

TOGGLE BIT

This device provides another function to determine the internal programming cycle. If the EEPROM is set to read mode

during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for each read. When the internal pro-

gramming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program.

TOGGLE BIT WAVEFORM

NOTES:

1) I/O6 beginning state is "1".

2) I/O6 ending state will vary.

3) See AC read characteristics.

4) Any locations can be used, but the address must be fixed.

Dout2

Dout

Dout1

Din

tCE3

tOE3

tOEH

tWC

tDW

4Next Mode

tOES

Address

CE\

WE\

OE\

I/O6

SOFTW ARE D ATA PROTECTION TIMING WAVEFORM (In protection mode)

tWC

tBLC

{

Address

Data (each byte)

5555

AAAA or

2AAA

5555

Write Address*

Write Data

VCC

CE\

WE\ tBLC

tBLC

* During this write cycle, data is physically written to the address provided.

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

SOFTWARE DATA PROTECTION TIMING WAVEFORM (In non-protection mode)

FUNCTIONAL DESCRIPTION

Automatic Page Write

Page-mode write feature allows 1 to 128 bytes of data to be

written into the EEPROM in a single write cycle. Following

the initial byte cycle, an additional 1 to 128 bytes can be writ-

ten in the same manner. Each additional byte load cycle must

be started within 30µs from the preceding falling edge of WE\

or CE\. When CE\ or WE\ is kept high for 100µs after data input,

the EEPROM enters write mode automatically and the input

data are written into the EEPROM.

D ATA\ P olling

DATA\ polling allows the status of the EEPROM to be deter-

mined. If EEPROM is set to read mode during the write cycle,

an inversion of the last byte of data to be loaded outputs from

I/O's 7, 15, 23, and 31 to indicate that the EEPROM is per-

forming a write operation.

RDY/Busy\ Signal

RDY/Busy\ signal also allows status of the EEPROM to be

determined. The RDY/Busy\ signal has high impedance ex-

cept in write cycle and is lowered to VOL after the first write

signal. At the end of write cycle, the RDY/Busy\ signal changes

state to high impedance.

RES\ Signal

When RES\ is low, the EEPROM cannot be read or pro-

grammed. Therefore, data can be protected by keeping RES\

low when VCC is switched. RES\ should be high during read

and programming because it doesn't provide a latch function.

See timing diagram below.

Program inhibit Program inhibit

Read inhibit

VCC

RES\

RES\ Signal Diagram

tWC

Address

Data (each byte)

5555

AAAA

2AAA

5555

AAAA

2AAA

VCC

CE\

WE\

5555

Normal

active mode

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

WE\, CE\ Pin Operation

During a write cycle, address are latched by the falling edge

of WE\ or CE\, and data is latched by the rising edge of WE\

or CE\.

Write/Erase Endurance and Data Retention Time

The endurance is 104 cycles in case of the page programming

and 103 cycles in case of the byte programming (1% cumula-

tive failure rate). The data retention time is more than 10

years when a device is page-programmed less than 104 cycles.

RDY/Busy\ SIGNAL

RDY/Busy\ signal also allows status of the EEPROM to

be determined. The RDY/Busy\ signal has high impedance

except in write cycle and is lowered to VOL after the first write

signal. At the end of the write cycle, the RDY/Busy\ signal

changes state to high impedance. This allows many

AS8ERLC128K32 devices RDY/Busy\ signal lines to be wired-

OR together .

PROGRAMMING/ERASE

The AS8ERLC128K32 does NOT employ a BULK-erase

function. The memory cells can be programmed ‘0’ or ‘1’. A

write cycle performs the function of erase & write on every

cycle with the erase being transparent to the user . The internal

erase data state is considered to be ‘1’. T o program the memory

array with background of ALL 0’s or All 1’s, the user would

program this data using the page mode write operation to pro-

gram all 1024 128-byte pages.

Data Protection

1. Data Protection against Noise on Control Pins (CE\,

OE\, WE\) During Operation

During readout or standby, noise on the control pins

may act as a trigger and turn the EEPROM to programming

mode by mistake. To prevent this phenomenon, this device has

a noise cancellation function that cuts noise if its width is 20ns

or less in program mode.

Be careful not to allow noise of a width more than

20ns on the control pins. See Diagram 1 below.

2. Data Protection at VCC On/Off

When VCC is turned on or off, noise on the control

pins generated by external circuits (CPU, etc.) may act as a

trigger and turn the EEPROM to program mode by mistake.

T o prevent this unintentional programming, the EEPROM must

be kept in an unprogrammable state while the CPR is in an

unstable state.

NOTE: The EEPROM should be kept in

unprogrammable state during VCC on/off by using CPU RE-

SET signal. See the timing diagram below.

DIAGRAM 1

D ATA PROTECTION AT VCC ON/OFF

*Unprogrammable

VCC

CPU

RESET

*Unprogrammable

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

Data Protection Cont.

a. Protection by RES\

The unprogrammable state can be realized by the

CPU's reset signal inputs directly to the EEPROM's RES pin.

RES should be kept VSS level during VCC on/off.

The EEPROM brakes off programming operation

when RES becomes low, programming operation doesn't fin-

ish correctly in case that RES falls low during programming

operation. RES should be kept high for 10ms after the last

data inputs. See the timing diagram below.

3. Software data protection

To prevent unintentional programming, this device

has the software data protection (SDP) mode. The SDP is

enabled by inputting the 3 bytes code and write data in

Chart 1. SDP is not enabled if only the 3 bytes code is input.

To program data in the SDP enable mode, 3 bytes code must

be input before write data. This 4th cycle during write is

required to initiate the SDP and physically writes the address

and data. While in SDP the entire array is protected in which

writes can only occur if the exact SDP sequence is

re-executed or the unprotect sequence is executed.

The SDP is disabled by inputting the 6 bytes code in

Chart 2. Note that, if data is input in the SDP disable cycle,

data can not be written.

The software data protection is not enabled at the

shipment.

NOTE: These are some differences between ASI's

and other company's for enable/disable sequence of software

data protection. If these are any questions, please contact ASI.

PROTECTION BY RES\

Program inhibit

VCC

RES\ Program inhibit

WE\ or CE\

1µ min 100µ min 10 ms min

CHART 1

Address

5555

AAAA or 2AAA

5555

Write Address

Data

(each Byte)

Write Data} Normal data input

CHART 2

Address

5555

AAAA or 2AAA

5555

AAAA or 2AAA

5555

Data

(each Byte)

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

ASI Case #703 (Pac kage Designator Q)

MECHANICAL DEFINITIONS*

*All measurements are in inches.

4 x D2

4 x D1

4 x D

Pin 1

MIN MAX

A 0.123 0.200

A1 0.118 0.186

A2 0.000 0.020

b 0.013 0.017

D1 0.870 0.890

D2 0.980 1.000

D3 0.936 0.956

R 0.005

L1 0.035 0.045

SYMBOL

0.010 REF

0.050 BSC

ASI PACKAGE SPECIFICATIONS

0.800 BSC

DETAIL A

0o - 7o

SEE DETAIL A

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

MECHANICAL DEFINITIONS*

ASI Case #703SQ

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

MECHANICAL DEFINITIONS*

ASI Case #703SQB

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

ASI Case (Package Designator QB)

MECHANICAL DEFINITIONS*

*All measurements are in inches.

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

*AVAILABLE PROCESSES

IT = Industrial Temperature Range -40oC to +85oC

XT = Extended T emperature Range -55oC to +125oC

883C = Full Military Processing, 1.2.1 compliant -55oC to +125oC

SPACE = ASI Class 'S' Flow -55oC to +125oC

ORDERING INFORMA TION

EXAMPLE: AS8ERLC128K32Q-250/883

Device NumbERLV Package Type Speed ns Process

S8ERLC128K32 Q -250 /*

S8ERLC128K32 Q -300 /*

S8ERLC128K32 QB -250 /*

S8ERLC128K32 QB -300 /*

S8ERLC128K32 SQ -250 /*

S8ERLC128K32 SQ -300 /*

S8ERLC128K32 SQB -250 /*

S8ERLC128K32 SQB -300 /*

AS8ERLC128K32QB-300/SPAC

EEPROMEEPROM

EEPROM

AS8ERLC128K32

Rev. 1.5 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

PRELIMINARY

SPECIFICATION

ASI TO DSCC PART NUMBER

CROSS REFERENCE*

* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.

Package Designator Q

ASI Part # SMD Part

AS8ERLC128K32Q-250/883C to be determined

AS8ERLC128K32Q-300/883C to be determined

Package Designator QB

ASI Part # SMD Part

AS8ERLC128K32QB-250/883C to be determined

AS8ERLC128K32QB-300/883C to be determined