Evaluation Board Document NE5550779A-EV09-A Evaluation Board o Circuit Description o Typical Performance Data o Circuit Schematic and Assembly Drawing Circuit Description The NE5550779A-EV09-A is an evaluation circuit board for Renesas' LDMOS power FET, NE5550779A optimized for the performance at 915MHz. The circuit board is RoHS compliant. Matching and Bias Circuits Both input and output matching networks consist of shunt capacitors and sections of transmission lines (refer to the schematic and assembly drawing in the last page of this document for the component designation). The electrical lengths of the transmission lines labeled on the schematic are estimated and for reference only. Some bench tuning on the actual circuit board is usually required to achieve optimal performance. For applications where there is a constraint on the board space, serial inductors, instead of transmission lines, can be used for the matching circuits. The efficiency spec, PAE, usually will be slightly lower in that case. LDMOSFETs essentially draw no gate current under normal operation conditions. Therefore a large value resistor, in the order of k, can be used for the gate biasing. At the drain an inductor is used as the RF choke. The current rating for this inductor should be high enough to provide the required current at the operation conditions. Bias Conditions This evaluation board was optimized at a specific drain voltage, 7.5V. For different supply voltages, the matching circuits should be adjusted to fully utilize the device capability. The quiescent current is 100mA for the data shown below. The gain is higher at higher quiescent currents, particularly when the device is not completely saturated. For many communication systems, where the PA is never at idle state, a high quiescent current might be used. PCB Material: The PCB is Getek 28mil two layer board. The dielectric constant of Getek is 4.2. 2 Typical Performance Data Test Conditions: f=915MHz Vd=7.5V, Idsq=100mA Pout, Gain, PAE and Current vs Pin are shown in the following plot. 3