First Release
Copyright © IXYS CORPORATION 2005
Ordering Information
General Description
The IXDN430/IXDI430/IXDD430/IXDS430 are high speed high current
gate drivers specifically designed to drive MOSFETs and IGBTs to their
minimum switching time and maximum practical frequency limits. The
IXD_430 can source and sink 30A of peak current while producing
voltage rise and fall times of less than 30ns. The input of the drivers are
compatible with TTL or CMOS and are fully immune to latch up over the
entire operating range. Designed with small internal delays, cross
conduction/current shoot-through is virtually eliminated in all
configurations. Their features and wide safety margin in operating
voltage and power make the drivers unmatched in performance and
value.
The IXD_430 incorporates a unique ability to disable the output under
fault conditions. The standard undervoltage lockout voltages are 11.75V
for the IXD_430 parts and 8.5V for the IXD_430M parts. ULVO can be
set to either level in the IXDS430 with the UNSEL input line. When a
logical low is forced into the Enable inputs, both final output stage
MOSFETs (NMOS and PMOS) are turned off. As a result, the output
of the IXDD430 enters a tristate mode and enables a Soft Turn-Off of the
MOSFET when a short circuit is detected. This helps prevent damage
that could occur to the MOSFET if it were to be switched off abruptly due
to a dv/dt over-voltage transient.
The IXDN430 is configured as a noninverting gate driver, and the IXDI430
is an inverting gate driver. The IXDS430 can be configured either as a
noninverting or inverting driver. The IXD_430 are available in the standard
28-pin SIOC (SI-CT), 5-pin TO-220 (CI), and in the TO-263 (YI) surface
mount packages. CT or 'Cool Tab' for the 28-pin SOIC package refers
to the backside metal heatsink tab.
Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected
• High Peak Output Current: 30A Peak
• Wide Operating Range: 8.5V to 35V
• Under Voltage Lockout Protection
• Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 5600 pF in <25ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
Applications
• Driving MOSFETs and IGBTs
• Motor Controls
• Line Drivers
• Pulse Generators
• Local Power ON / OFF Switch
• Switch Mode Power Supplies (SMPS)
• DC to DC Converters
• Pulse Transformer Driver
• Limiting di/dt Under Short Circuit
• Class D Switching Amplifiers
Part Number Package
Type Tem p. Range Configuration Undervoltage
Lock-out
IXDD430YI
IXDD430MYI 5-pin TO -263 11.75 V
8.5 V
IXDD430CI
IXDD430MCI 5-pin TO -220 -55°C to +125° Non Inverting with
Enable 11.75 V
8.5 V
IXDI430YI
IXDI430MYI 5-pin TO -263 11.75 V
8.5 V
IXDI430CI
IXDI430MCI 5-pin TO -220
-55°C to +125°
In v e rtin g 11.75 V
8.5 V
IXDN430YI
IXDN430MYI 5-pin TO -263 11.75 V
8.5 V
IXDN430CI
IXDN430MCI 5-pin TO -220
-55°C to +125°
Non Inverting
11.75 V
8.5 V
IXDS430SI 28-pin SOIC
-55°C to +125°
Inverting / Non
In ve rtin g with
Enable
and UV SEL
11.75 V
or
8.5 V
30 Amp Low-Side Ultrafast MOSFET / IGBT Driver
IXDN430 / IXDI430 / IXDD430 / IXDS430
DS99045C(04/04)
2
IXDN430 / IXDI430 / IXDD430 / IXDS430
Figure 1C - IXDI430 (Inverting) Diagram
Figure 1A - IXDD430 (Non Inverting With Enable) Diagram
Figure 1B - IXDN430 (Non-Inverting) Diagram
Figure 1D - IXDS430 (Inverting and Non Inverting with Enable) Diagram
Notes: 1. Out P and Out N are connected together in the 5 lead TO-220 and TO-263 packages;
2. IXDS430: Undervoltage lock-out is set by UVSEL. UVSEL = Vcc, UVLO = 8.5V, UVSEL = OPEN, UVLO = 11.75V.
INV
400K
400K
1K
GNDGND
VccVcc
OUT N
OUT P
IN
EN
UVSEL UVCC
1K OUT
GNDGND
VccVcc
IN
EN
400k
UVCC
OUT
Vcc
1K
GNDGND
Vcc
IN
UVCC
OUT
Vcc
1K
GNDGND
Vcc
IN
UVCC
3
IXDN430 / IXDI430 / IXDD430 / IXDS430
Unless otherwise noted, TA = 25 oC, 8.5V ≤ VCC ≤ 35V .
All voltage measurements with respect to GND. IXDD430 configured as described in Test Conditions.
Electrical Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
VIH High in put voltage 0V≤VIN ≤VCC, 8.5V≤VIN ≤18V 3.5 V
VIL Low input voltage 0V≤VIN ≤VCC, 8.5V≤VIN ≤18V 0.8 V
VIN Input voltage range -5 VCC + 0.3 V
IIN Input current 0V ≤ VIN ≤ V CC
-10 10
µA
VOH High output voltage VCC - 0.025 V
VOL Low output voltage 0.025 V
ROH Output resistance
@ O utput high VCC = 18V
0.3 0.4
Ω
ROL Output resistance
@ Ou tp u t L o w VCC = 18V 0.2 0.3 Ω
IPEAK Peak output current VCC = 18V
30 A
IDC Continuous output
current Limited b y package power
dissipation 8 A
VEN Enable voltage range IX DD 430 O nly - 0.3 Vcc + 0.3 V
VENH High E n Input V oltage IXD D430 O nly 2/3 Vcc V
VENL Low En Input V oltage IXD D430 O nly 1/3 Vcc V
REN EN Input R esistance IXD S430 O nly 400 Kohm
VINV INV Voltage R ange IX DS 430 Only - 0.3 Vcc + 0.3 V
VINVH High IN V Input Voltage IX DS 430 Only 2/3 Vcc V
VINVL Low IN V Input V oltage IXD S430 O nly 1/3 V cc V
RINV INV Input R esistance IXD S430 O nly 400 Kohm
tR Rise time CL=5600pF Vcc=18V 18 20 ns
tF Fall time CL=5600pF Vcc=18V 16 18 ns
tONDLY On-time propagation
d e la y CL=5600pF V cc=18V 41 45 ns
tOFFDLY Off-time propagation
d e la y CL=5600pF V cc=18V 35 39 ns
tENOH Enable to output hig h
delay time IX DD 430 O nly, V cc=18 V 47 ns
tDOLD Disable to output low
delay time IX DD 430 O nly, V cc=18 V 120 ns
VCC Power supply voltage 8.5 18 35 V
ICC Power supply current VIN = 3 .5V
VIN = 0V
VIN = + VCC
1
0 3
10
10
mA
µA
µA
UVLO IXD_430M; IXDS430:
IX D_ 4 3 0 ; IX DS4 3 0 : UVSEL = VCC (MOS F E T )
UVSEL = O PEN (IGBT) 7.5
10.5 8.5
11.75 9.5
13.0 V
V
Absolute Maximum Ratings (Note 1)
Paramete
r
V
alue
Supply Voltage 40 V
All Other Pins -0.3 V to VCC + 0.3 V
Power Dissipation, TAMBIENT ≤25 oC
TO220 (CI), TO263 (YI) 2W
Derating Factors (to Ambient)
TO220 (CI), TO263 (YI) 0.016W/oC
Storage Temperature -65 oC to 150 oC
Lead Temperature (10 sec) 300 oC
Operating Ratings
P ara me ter
V
alue
M aximum Junction Temperature 150 oC
O pera ting Tem perature Range -55 oC to 125 oC
Therm al Impedance TO 220 (CI), TO 263 (YI)
θJC (Junction To Case) 0.95 o C/W
θJA (Junction To Am bient) 62.5 oC/W
Therm al Impedance 28 pin S OIC with H eat S lug (SI)
θJC (Junction To Case) 3 o C/W
Specifications Subject To Change Without Notice
Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
4
IXDN430 / IXDI430 / IXDD430 / IXDS430
Symbol Paramete
r
Test Conditions Min Typ Max Units
VIH High input voltage 8.5 ≤ Vcc ≤ 18V 3.5 V
VIL Low input vol tag e 8.5 ≤ Vcc ≤ 18V 1.1 V
VIN Input voltage range -5 VCC + 0.3 V
ROH Output resistance
@ Output high VCC = 18V
0.46
Ω
ROL Output resistance
@ Output Low VCC = 18V 0.4 Ω
tR Rise time CL=5600pF Vcc=18V 20 ns
tF Fall time CL=5600pF Vcc=18V 18 ns
tONDLY On-time propagation
delay CL=5600pF Vcc=18V 58 ns
tOFFDLY Off-time propagation
delay CL=5600pF Vcc=18V 51 ns
VCC Power supply voltage 8.5 18 35 V
Electrical Characteristics
Unless otherwise noted, temperature over -55 oC to +125 oC, 4.5 ≤ VCC ≤ 35V .
All voltage measurements with respect to GND. IXDD430 configured as described in Test Conditions.
NOTE: Mounting tabs, solder tabs, or heat sink metalization on all packages are connected to ground.
5-lead TO-220 Outline (IXD_430CI, IXD_430MCI)
28-pin SOIC Outline (IXD_430SI)
5-lead TO-263 Outline (IXD_430YI, IXD_430MYI)
5
IXDN430 / IXDI430 / IXDD430 / IXDS430
Pin Description
SYMBOL FUNCTION DESCRIPTION
VCC Supply Voltage
Positive power-supply voltage input. This pin provides power to the
entire chip. The range for this voltage is from 8.5V to 35V.
IN Input Input sign al-TT L or CM O S com patible.
EN * Enable The s ystem enable pin. T his pin, when driven low, disables the chip,
forcing high im pedance state to the output (IXDD 430 O nly).
INV Invert
Forcing INV low causes the IXDS430 to becom e non-inverted, while
forcing INV high causes the IXDS43 0 to become inverted.
OUT P
OUT N Output
Respective P and N driver outputs. For application purposes this pin
is connected, throu gh a resistor, to Gate of a MO SFET/IG BT. The P
and N output pins are c onnected together in the T O -263 and TO -220
packages.
GND Ground
The system ground pin. Internally connected to all circuitry, this pin
provides ground reference for the entire chip. This pin should be
connected to a low noise analog ground plane for optimum
perform ance.
UVSEL Select Under
Voltag e L evel With UVSEL connected to Vcc, IXDS430 outputs go low at Vcc <
8.5V; With UV S EL open, under voltag e level is set a t Vcc < 12.5V
Figure 2 - Characteristics Test Diagram
* This pin is used only on the IXDD430, and is N/C (not connected) on the IXDI430 and IXDN430.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when
handling and assembling this component.
TO220 (CI)
TO263 (YI)
Vcc
OUT
GND
IN
EN *
1
2
3
4
5
Pin Configurations
(SI-CT)
28 Pin SOIC
Vcc 4
Vcc 3
Vcc 2
Vcc 1
25 Vcc
26 Vcc
27 Vcc
28 Vcc
18 GNDGND 11
16 GND
17 GND
15 GND
GND 13
GND 12
22 OUT P
23 OUT P
24 OUT P
19 OUT N
20 OUT N
21 OUT N
GND 14
N/C 7
N/C 5
UVSEL 6
IN 8
EN 9
INV 10
+
Vin
-
Vcc
EN
IN
GND
OUT
Vcc
+
IXDD430
C
LOAD
-
C
BYPASS/
..
FILTER
6
IXDN430 / IXDI430 / IXDD430 / IXDS430
Rise and Fall Times vs. Temperature
CL = 5600 pF, Vcc = 18V
0
5
10
15
20
25
-60 -10 40 90 140 190
Tem p erature (C)
Time (ns)
tR
tF
Output Rise Times vs. Load Capacitance
5
10
15
20
25
30
1000 3000 5000 7000 9000 11000 13000 15000
Load Capacitance (pF)
Rise Time (ns)
13V
18V
35V
O u tp ut F a ll Time s v s . Loa d Ca p acita nce
0
5
10
15
20
25
30
1000 3000 5000 7000 9000 11000 13000 15000
Load Capacitance (pF)
Fall Time (ns)
13V
18V
35V
R ise Times vs. Supply Volta ge
0
5
10
15
20
25
30
35
10 15 20 25 30 35
Supply Voltage (V)
Rise Time (ns)
1000 pF
5600 pF
10000 pF
15000 pF
F a ll T ime s v s. Su p p ly V o lta g e
0
5
10
15
20
25
30
10 15 20 25 30 35
Supply Voltage (V)
Fall Time (ns)
1000 pF
5600 pF
10000 pF
15000 pF
Typical Performance Characteristics
Fig. 3 Fig. 4
Fig. 5 Fig. 6
Fig. 7 Fig. 8 Max / Min Input vs. Temperature
CL = 5600pF, Vcc = 18V
0
0.5
1
1.5
2
2.5
3
3.5
4
-60 -10 40 90 140 190
Tem perature (C)
Max / Min Input Voltage
Min Input High
Max Input Low
7
IXDN430 / IXDI430 / IXDD430 / IXDS430
Supply Current vs. Frequency
Vcc = 25V
0.1
1
10
100
1000
1 10 100 1000 10000
Frequency (kHz)
Supply Current (mA )
1000 pF
5600 pF
10000 pF
15000
p
F
Supply Current vs. Load Capacitance
Vcc = 25V
0
50
100
150
200
250
300
350
400
1000 10000 100000
Load C apacitance (pF)
Supply Current (m A)
10 kHz
50 kHz
100 kHz
500 kHz
1 MHz
2 MHz
Supply Current vs. Frequency
Vcc = 18V
0.1
1
10
100
1000
1 10 100 1000 10000
Frequency (kHz)
Supply Current (mA)
1000
p
F
5600
p
F
10000
p
F
15000
p
F
Supply Current vs. Load Capacitance
Vcc = 18V
0
50
100
150
200
250
300
1000 10000 100000
Load Capacitance (pF)
Supply Current (m A)
2 MHz 1 MHz
500 kHz
100 kHz
50 kHz
10 kHz
Supply Current vs. Load Capacitance
Vcc = 13V
0
50
100
150
200
250
300
1000 10000 100000
Load Capacitance (pF)
Supply Current (mA)
10 k H z
50 kHz
100 kHz
500 kHz
1 MHz
2 MHz
Supply Current vs. Frequency
Vcc = 13 V
0.1
1
10
100
1000
1 10 100 1000 10000
Frequency (kHz)
Supply Current (mA)
1000
p
F
5600
p
F
10000
p
F
15000
p
F
Fig. 10
Fig. 11 Fig. 12
Fig. 14
Fig. 9
Fig. 13
8
IXDN430 / IXDI430 / IXDD430 / IXDS430
Supply Current vs. Load Capacitance
Vcc = 35V
0
50
100
150
200
250
300
350
400
1000 10000 100000
Load Capacitance (pF)
Supply Current (mA)
10 kHz
50 kHz
100 kHz
500 kHz
1 MHz
Supp ly Current vs. Frequency
Vcc = 35V
1
10
100
1000
1 10 100 1000 10000
Frequency (kHz)
Supply Current (mA)
1000 pF
5600
F
10000
p
F
15000
p
F
Fig. 16
Fig. 17 Fig. 18
Fig. 19 Fig. 20
Fig. 15
Quiesc en t Supp ly C u rren t vs. Tem pe ra ture
Vcc = 18V, Vin = 15V@1kHz, CL = 5600pF
0
0.1
0.2
0.3
0.4
0.5
0.6
-60 -10 40 90 140 190
Temperature (C)
Quie scent Vcc Input Current (mA)
Propagation Delay Times vs. Temperature
CL = 560 0pF, Vcc = 18V
0
10
20
30
40
50
60
70
-60 -10 40 90 140 190
Temperature (C)
Time (ns)
tONDLY
tOFFDLY
Propagation Delay vs. Supply Voltage
CL = 5600 pF Vin = 15V@1kHz
0
5
10
15
20
25
30
35
40
45
50
10 15 20 25 30 35
Supply Voltage (V)
Propagation Delay (ns)
tONDLY
tOFFDLY
Propagation Delay vs. Input Voltage
CL = 5600 pF Vcc = 18V
0
5
10
15
20
25
30
35
40
45
50
5 10152025
Input Voltage (V)
Propagati on Delay (ns)
tONDLY
tOFFDLY
9
IXDN430 / IXDI430 / IXDD430 / IXDS430
N Channel Output Current vs. Temperature
Vcc = 1 8V
0
5
10
15
20
25
30
35
40
45
-60 -10 40 90 140 190
Temperature (C)
N Channel Output Current (A)
P Channel O utput Current vs. Vcc
-80
-70
-60
-50
-40
-30
-20
-10
0
10 15 20 25 30 35 40
Vcc (V)
P Channel Output Current (A )
High State Output Resistance vs. Supply Voltage
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
10 15 20 25 30 35 40
Supply Voltage (V)
High State Output Resistance (Ohms)
P Channel Output Current vs. Temperature
Vcc = 18 V
0
5
10
15
20
25
30
35
40
-60 -10 40 90 140 190
Temperature (C)
P Channel Output Current (A)
Fig. 21 Fig. 22
Fig. 23 Fig. 24 N C h a nnel O u tp ut C u rr e n t v s . V c c
0
10
20
30
40
50
60
70
10 15 20 25 30 35 40
Vcc (V)
N Channel O utput Current (A)
Fig. 25 Fig. 26
Low State Output Resistanc e v s. S u pp ly Voltage
0
0.05
0.1
0.15
0.2
0.25
10 15 20 25 30 35 40
Supply Voltage (V)
Low State Output Resist ance (Ohm s)
10
IXDN430 / IXDI430 / IXDD430 / IXDS430
Figure 28 - IXDD430 Application Test Diagram
Figure 27 - Typical circuit to decrease di/dt during turn-off
10uH
Ld
0.1ohm
Rd
Rs
20nH
Ls
1ohm
Rg
10kohm
R+
VMO580-02F
Hi
g
h
_
Power
5kohm
Rcomp
100pF
C+
+
-
V+
V-
Comp
LM339
1600ohm
Rsh
Ccomp
1pF
VCC
VCCA
IN
EN
GND
OUT
IXDD430
+
-
VIN
+
-
VCC
+
-
REF
+
-
VB
CD4001A
NOR2
1Mohm
Ros
NOT2
CD4049A
CD4011A
NAND
CD4049A
NOT1
CD4001A
NOR1
CD4049A
NOT3
Low
_
Power
2N7002/PLP
1pF
Cos
0
S
R
EN
Q
On e Sh o t C i rc u i t
SR Flip-Flop
GND
11
IXDN430 / IXDI430 / IXDD430 / IXDS430
Short Circuit di/dt Limit
A short circuit in a high-power MOSFET module such as the
VM0580-02F, (580A, 200V), as shown in Figure 27, can cause
the current through the module to flow in excess of 1500A for
10µs or more prior to self-destruction due to thermal runaway.
For this reason, some protection circuitry is needed to turn off
the MOSFET module. However, if the module is switched off
too fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche break-
down.
The IXDD430 has the unique capability to softly switch off the
high-power MOSFET module, significantly reducing these
Ldi/dt transients.
Thus, the IXDD430 helps to prevent device destruction from
both dangers; over-current, and avalanche breakdown due to
di/dt induced over-voltage transients.
The IXDD430 is designed to not only provide ±30A under
normal conditions, but also to allow it's output to go into a high
impedance state. This permits the IXDD430 output to control
a separate weak pull-down circuit during detected overcurrent
shutdown conditions to limit and separately control dVGS/dt gate
turnoff. This circuit is shown in Figure 28.
Referring to Figure 28, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the VM0580-02. A low pass filter should be added to the input
of the comparator to eliminate any glitches in voltage caused
by the inductance of the wire connecting the source resistor to
ground. (Those glitches might cause false triggering of the
comparator).
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS
4000-series devices operate with a VCC range from 3 to 15 VDC,
(with 18 VDC being the maximum allowable limit).
A low power MOSFET, such as the 2N7000, in series with a
resistor, will enable the VMO580-02F gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the VMO580-02F.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD430 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD430 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD430 input, and this
pulse will reset the SRFF outputs to normal operation.
When a short circuit occurs, the voltage drop across the low-
value, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a
low input into the Enable pin disabling the IXDD430 output. The
SRFF also turns on the low power MOSFET, (2N7000).
In this way, the high-power MOSFET module is softly turned off
by the IXDD430, preventing its destruction.
APPLICATIONS INFORMATION
Supply Bypassing and Grounding Practices,
Output Lead inductance
When designing a circuit to drive a high speed MOSFET
utilizing the IXDD430/IXDI430/IXDN430, it is very important to
keep certain design criteria in mind, in order to optimize
performance of the driver. Particular attention needs to be paid
to Supply Bypassing, Grounding, and minimizing the Output
Lead Inductance.
Say, for example, we are using the IXDD430 to charge a 15nF
capacitive load from 0 to 25 volts in 25ns.
Using the formula: I= C ∆V / ∆t, where ∆V=25V C=15nF &
∆t=25ns we can determine that to charge 15nF to 25 volts in
25ns will take a constant current of 15A. (In reality, the charging
current won’t be constant, and will peak somewhere around
30A).
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXDD430
must be able to draw this 5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is a magnitude
larger than the load capacitance. Usually, this would be
achieved by placing two different types of bypassing capacitors,
with complementary impedance curves, very close to the driver
itself. (These capacitors should be carefully selected, low
inductance, low resistance, high-pulse current-service
capacitors). Lead lengths may radiate at high frequency due
to inductance, so care should be taken to keep the lengths of
the leads between these bypass capacitors and the IXDD430
to an absolute minimum.
GROUNDING
In order for the design to turn the load off properly, the IXDD430
must be able to drain this 5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD430
and it’s load. Path #2 is between the IXDD430 and it’s power
supply. Path #3 is between the IXDD430 and whatever logic is
driving it. All three of these paths should be as low in resistance
and inductance as possible, and thus as short as practical. In
addition, every effort should be made to keep these three
ground paths distinctly separate. Otherwise, (for instance), the
returning ground current from the load may develop a voltage
that would have a detrimental effect on the logic line driving the
IXDD430.
12
IXDN430 / IXDI430 / IXDD430 / IXDS430
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: marcom@ixys.de
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
www.ixys.com
e-mail: sales@ixys.net
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the load. A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high,
V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in
Figure 29 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to VCC=15V, and provides a
high voltage CMOS logic high output. The high voltage CMOS
logical EN output applied to the IXDD430 EN input will enable
it, allowing the gate driver to fully function as an 30 Amp
output driver.
The total component cost of the circuit in Figure 29 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.
Figure 29 - TTL to High Voltage CMOS Level Translator
TTL to High Voltage CMOS Level Translation
(IXDD430 Only)
The enable (EN) input to the IXDD430 is a high voltage
CMOS logic level input where the EN input threshold is ½
VCC, and may not be compatible with 5V CMOS or TTL input
levels. The IXDD430 EN input was intentionally designed
for enhanced noise immunity with the high voltage CMOS
logic levels. In a typical gate driver application, VCC =15V
and the EN input threshold at 7.5V, a 5V CMOS logical high
input applied to this typical IXDD430 application’s EN input
will be misinterpreted as a logical low, and may cause
undesirable or unexpected results. The note below is for
optional adaptation of TTL or 5V CMOS levels.
A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied to the
Q1 emitter will drive it on. This causes the level translator
output, the Q1 collector output to settle to VCESATQ1 +
VTTLLOW=<~2V, which is sufficiently low to be correctly interpreted
as a high voltage CMOS logic low (<1/3VCC=5V for VCC =15V given
in the IXDD430 data sheet.)
The circuit in Figure 29 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic
input to high voltage CMOS logic levels needed by the
IXDD430 EN input. From the figure, VCC is the gate driver
power supply, typically set between 8V to 20V, and VDD is
the logic power supply, typically between 3.3V to 5.5V.
Resistors R1 and R2 form a voltage divider network so
that the Q1 base is positioned at the midpoint of the
expected TTL logic transition levels.
Q1
2N3904
R1
10K
R2
10K
R3
10K
Vdd
EN
Vcc
(From gate driver
power supply)
power supply)
5V CMOS or TTL input
(From logic
(To IXDD430 EN input)
CMOS EN output
High Voltage
DS99045A(8/03)