19-1255, Rev 0; 8/97 General Description The MAX5150/MAX5151 low-power, serial, voltage-out- put, dual 13-bit digital-to-analog converters (DACs) consume only S00uA from a single +5V (MAX5150) or +3V (MAX5151) supply. These devices feature Rail-to- Rail output swing and are available in a space-saving 16-pin QSOP package. To maximize the dynamic range, the DAC output amplifiers are configured with an internal gain of +2. The 3-wire serial interface is SPI/QSPI and Microwire compatible. Each DAC has a double- buffered input organized as an input register followed by a DAC register, which allows the input and DAC reg- isters to be updated independently or simultaneously with a 16-bit serial word. Additional features include programmable shutdown (2A), hardware-shutdown MA AXIMA Low-Power, Dual, 13-Bit Voltage-Output DACs with Serial Interface Features 13-Bit Dual DAC with internal Gain of +2 # Rail-to-Rail Output Swing + 168 Settling Time @ Single-Supply Operation: +5V (MAX5150) +3V (MAX5151) Low Quiescent Current: S500pA (normal operation) 2uA (shutdown mode) SPI/QSPi and Microwire Compatible Available in Space-Saving 16-Pin QSOP Package Power-On Reset Clears Registers and DACs to Zero @ Adjustable Output Offset -?- + lockout, a separate reference voltage input for each Orderi information DAC that accepts AC and DC signals, and an active- ng low clear input (CL) that resets ail registers and DACs INL to zero. These devices provide a programmable logic PART TEMP. RANGE PIN-PACKAGE {LSB} pin a aceon functionality, and a serial-data output pin MAXSIS0ACPE OCto+70C 16 Plastic DIP err OF dalsy-chaining. MAXSI50BCPE _OCto+70C 16Plastic DIP? A pplications MAX5150ACEE OC to +70C 16 QSOP +1/2 Industrial Process Control Remote Industrial Controls MAXS'SOBCEE OC to +70C 16 QS80P x Digital Offset and Gain Microprocessor MARS TEBE _OC to +70C _Dive = Adjustment Controlled Systems Ordering information continued at end of data sheet. " . Dice are tested at Ta = +25C, DC parameters only. Motion Control Automatic Test Equipment (ATE) Pin Configuration appears at end of data sheet. Functional Diagram pout OL POL DGND AGND Yoo REFA & oN SERIAL CONTROL SCLK uPo DAC A A OUTA MAXIM MAX5150 MAX5151 DAC DACB ion FEB REFB Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. PAAXLSA SPI and QSP! are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. For free samples & the latest literature: http:/;www.maxim-ic.com, or phone 1-800-998-8800 For small orders, phone 408-737-7600 ext. 3468. Maxim integrated Products 9-85 = : :MAX5150/MAX5151 Low-Power, Dual, 13-Bit Voltage-Output DACs with Serial Interface ABSOLUTE MAXIMUM RATINGS Von tO AGND A... ccc eececcseteceeetesaecaseenesreneensertnes -G.3V to +6V Vop te OGND ... -0.3V to +6V AGND to DGND... OSA, OSB to AGND. . _A(AGND - 4V/) to (Vop + 0.3V) REF_, OUT_ to AGND........ .D.3V to (Von + 0.3) Maximum Current into Any Pin ooo... cect cere crceees +20mA Continuous Power Dissipation (Ta = +70C) Plastic DIP (derate 10.5mW/PC above +70C) .......... 842mW QSOP (derate 8.30mMW/C above +70C)......... . CERDIP (derate 10.00mWPC above +70C) Digital Inputs (SCLK, DIN, GS, GL. PDL) | tO DGND ooo ccce ct ccec ces ectee reset entiteetiereeesa -O.9V to +6V Digital Outputs (DOUT, UPO) tO DGND oe eee ... -0.3V to (Vop + 0.3V) Operating Temperature Ranges MAX515__E_E .... MAXS15_ C_E oe MAXS15_ MJB. ee veaecenee cece OE tO +70C 40C to +85C vseee bere BES to + 125C Stresses beyond those listed under Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at !hese or any other conditions beyond these indicated in the operational sections of the specifications is not implied. Exposure to absolule maximum rating conditions lor extended periods may affect device reliability. ELECTRICAL CHARACTERISTICSMAX5150 (Vop = +5V 210%, VREEA = VREFe = 2.048V, Ry = 10kQ, Cy = 100pF, Ta = Tin to Tax, unless otherwise noted. Typical values are at Ta= 425C (OS_ tiecl to AGND for a gain of +2).) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS STATIC PERFORMANCEANALOG SECTION Resolution 13 Bits MAX5150A if2 Int | Nonlineari INL Note j egral earity (Note 1) MAX5150B ni LSB Differential Nontinearity DNL Guaranteed monotonic +1 LSB Offset Error Vos Code = 12 +6 5 mV Otiset Tempco TCVos_ | Normalized to 2.048V 4 ) ppmPC Gain Error 0.2 +3 mv Gain-Error Tempco Normalized to 2.048V 4 ppm?c Voo Power-Supply Rejection Ratio PSRAR | 45V< Vo $5.5V 20 260 uVIV REFERENCE INPUT Reference Input Range REF 0 Voo - 1.4 Vv Reference input Resistance RREF Minimum with code 1555 hex 14 20 kQ MULTIPLYING-MODE PERFORMANCE . Input code = {FFF hex, . Reference 3dB Bandwidth VReF. = 0.67Vp-p at 25Voc 300 kHz Input code = 0000 hex. Reference Feedthrough Veer. = (Vp - 1.4Vp-p) at 1kHz -B2 dB Signal-to-Noise plus Input code = 1FFF hex, - Distortion Ratio SINAD | Vper_ = 1Vpp at 1.25Vpe, f = 25kHz * dB DIGITAL INPUTS Input High Voltage Vin | CL. PBL, CS, DIN, SCLK 3.0 v input Low Voltage Vib CL. PDL. CS. DIN, SCLK 08 Vv Input Hysteresis VHYS 200 mV Input Leakage Current tin Vin = OV to Vop 0.001 1 yA input Capacitance Cin 8 pF PAAXIMALow-Power, Dual, 13-Bit Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICSMAX5150 (continued) = (Vpp = +5V +10%, VrRera = Vagpp = 2.048V, Ry = 10kQ, CL = 100pF, Ta = Twin to Tmax, unless otherwise noted. Typical values are at Tas +25C (OS_ tied to AGND for a gain of +2).} PARAMETER _[SyMmaoL | CONDITIONS [| MIN TYP MAX | UNITS DIGITAL OUTPUTS Qn Output High Voltage VOH ISOURCE = 2MA Vop -0.5 Vv wl, Output Low Voltage Vot IsINK = 2mA 0.13 0.4 v Q DYNAMIC PERFORMANCE Vaitage Output Slew Rate SR 0.75 Vips 2 Output Settling Time To 1/2LSB of full-scale, Vgrep = 4V 16 us Output Voltage Swing Rail-to-rail (Note 2) 0 te Voo v e OSA or OSB Input Resistance Ros 24 34 kQ a Time Required to Exit Shutdown 25 us Oi Digital Feedthrough GS = Vop. fpIn = 100kHz, Vecix = 5Vp-p 5 ave] Digital Crosstalk 5 nV-s POWER SUPPLIES Positive Supply Voltage Voo 45 5.5 v Power-Supply Current lop (Note 3) 0.5 0.65 mA, Power-Supply Current in Shutdown IDD (SHON}) (Note 3) 2 10 WA Reference Current in Shutdown 0 +1 LA TIMING CHARACTERISTICS SCLK Clock Period tcp 100 ns SCLK Pulse Width High tcH 40 ns SCLK Pulse Width Low ter 40 ns CS Fall to SCLK Rise Setup Time 'css 40 ns SCLK Rise to CS Rise Hold Time | tcsH 0 ns SD! Setup Time tos 40 ns SDI Hold Time 1DH 0 ns SCLK Rise to DOUT _ Valid Propagation Delay oot CLoap = 200pF 80 ns SCLK Fall to DOUT Valid Propagation Delay !oo02 CLoap = 200pF 80 ns SCLK Rise to CS Fall Delay tcso 10 ns CS Rise to SCLK Rise Hold test 40 ns CS Pulse Width High tcosw 100 ns Note 1: Accuracy is specified from code 12 to code 8191. Note 2: Accuracy is better than 1LSB for VouT_ greater than 6mvV and fess than Vpp - SOmV. Guaranteed by PSRR test at the end points. Note 3: Digital inputs are set to either Vop or DGND, code = 0000 hex, Ri = . FAAXIMA 9-87MAX5150/MAX5151 Low-Power, Dual, 13-Bit Voltage-Output DACs with Serial interface ELECTRICAL CHARACTERISTICS-MAX5151 (Vop = +2.7V to +3.6V, Vrera = Vrere = 1.25V, Ry = 10kQ, CL = 100pF, Ta = Tain to Tmax, unless otherwise noted, Typical values are at Ta = +25C (OS_ pins tied ta AGND for a gain of +2).} PARAMETER | SYMBOL | CONDITIONS MIN TYP = MAX | UNITS STATIC PERFORMANCEANALOG Resolution 413 Bits . . MAX5151A +1 integral Nonlinearity INL (Note 4) MAXS151B = LSB Differential Nontinearity DNL Guaranteed monotonic +1 LSB Offset Error Vas Code = 20 +6 mV Offset Tempco TCVgs_ | Normalized to 1.25V 65 ppmPc Gain Error 0.2 +5 mv Gain-Error Tempco Normalized to 1.25V 6.5 ppm ae Fower Suen PSRR | 2.7V <Vpp $3.6V 40 320 | pV REFERENCE INPUT (VREF) Reference Input Range REF 0 Von - 1.4 Vv Reference Input Resistance Raer Minimum with code 1555 hex 14 20 kQ MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth Veer 08/Vpp re 300 kHz Reference Feedthrough Veer opp. 1 4Veco at tkH2 82 0B Datertion Ratio pis SINAD Vier Sve att Ven f = 15kHz 73 dB DIGITAL INPUTS input High Voltage Vin | CC, POL, CS, DIN. SCLK 22 Vv Input Low Voltage vit | CL, POL, CS, DIN, SCLK 0.8 Vv Input Hysteresis VHYS 200 mV Input Leakage Current HN Vin = OV to Vop 0 +1 pA input Capacitance CIN 8 oF DIGITAL OUTPUTS Output High Voltage VOH ISOURCE = 2mA Vop - 0.5 Vv Output Low Voltage VOL IsInk = 2mA 0.13 0.4 Vv DYNAMIC PERFORMANCE Voltage Output Slew Rate SR ) 0.75 Vius Output Setiling Time To 1/2LSB of full-scale, Vstep = 2.5V 16 us Output Voltage Swing Rail-to-raii (Note 5) 0 to Voo v OSA or OSB Input Resistance Ros 24 34 kQ Time Required for Valid 25 us Operation after Shutdown , Digital Feedthrough CS = Vpp, foin = 100kHz, VsciK = 3Vp-p 5 nv-s Digital Crosstalk 5 AV-s 9-88 MAAXIMMLow-Power, Dual, 13-Bit Voltage-Output DACs with Serial interface ELECTRICAL CHARACTERISTICSMAX5151 (continued) (Vpp = +2.7V to +3.6V, Vaera = Vacee = 1.25V, RL = 10kQ, CL = 100pF, Ta = Tain to TMax, unless otherwise noted. Typical values = are at Ta = +25C (OS_ pins tied to AGND for a gain of +2).) PARAMETER | SYMBOL | CONDITIONS | MIN TYP = MAX | UNITS e POWER SUPPLIES Q Positive Supply Voltage Vpp 27 3.6 Vv mi, Power-Supply Current lop (Note 6) 0.45 0.6 mA i] in Shutsoor. Current IDD (SHDN) (Note 6) 1 8 yA > Referance Current in Shutdown 0 +1 pA TIMING CHARACTERISTICS > SCLK Clock Period tcp 100 ns SCLK Pulse Width High {CH 40 ns Qi SCLK Pulse Width Low {CL 40 ns an Se, ScLk Rise tess 40 hs wah, SCLK Rise to CS Rise Hold Time | tcsH 0 ns SDI Setup Time tos 50 ns SDI Hold Time toH# : 0 ns propesate "Seley Valid to01_| CLoap = 200pF 120 | ns seule pouTVaia | pca_| ccm = 209" 20 | SCLK Rise to CS Fall Delay tcso 10 ns CS Rise to SCLK Rise Hold tost 40 ns CS Pulse Width High tcsw 100 ns Note 4: Accuracy is specified from code 20 to code 8191. Note 5: Accuracy is better than 1LSB for Vout greater than 6mV and less than Vop - 8OmV. Guaranteed by PSRR test at the end points. Note 6: Digital inputs are set to either Vop or DGND, code = 0000 hex, R, = =. MAXUM 9-89MAX5150/MAX5151 Low-Power, Dual, 13-Bit Voltage-Output DACs with Serial Interface Typical Operating Characteristics (Vop = +5V, Ry = 10@, CL = 100pF, OS_ pins tied to AGND, unless otherwise noted.) REFERENCE VOLTAGE INPUT TOTAL HARMONIC DISTORTION FREQUENCY RESPONSE SUPPLY CURRENT vs. TEMPERATURE PLUS NOISE vs. FREQUENCY 700 30 t TOPrT Ered 8 Voge = iVp-p @ 2. 5Vpc | = 650 = {FFF CODE = FFF (HEX) j is -40 z g z | : = = 600 S = a wy 730 a = 550 8 = = + = z , 2 - a & 500 CODE = 0000 (HEX)| = = -70 Vaer = 0.67Vp-: @ 2.5Vpc 450 ~ A CODE = 1FFF (HEX) Vrer=2 oaBy | 400 -86 ml 1 3707401110 14801850 55-35-15 2% 45 65 85 105 125 1 16 400 FREQUENCY (kHz) TEMPERATURE (C) FREQUENCY (kHz) SHUTDOWN CURRENT FULL-SCALE ERROR vs. LOAD REFERENCE FEEDTHROUGH AT 1kHz vs. TEMPERATURE 10 8 Verge = 2.048 Var = 3Vp-p @ 1 5Vpe Vper = 'V 05 fe tke 5 : = CODE = 0000 (HE = go (HE) z = S = 4 & 05 2 NOTE: RELATIVE TO FULL-SCALE OUTPUT @ 40 3 B 4 2 g = @ 15 = e 3 z = ? = 29 a 1 25 30 -150 0 04 { 10 400 05 10 15 20 25 30 35 40 45 50 55 5-35-15 5 25 45 65 85 105 125 Ri (kQ) FREQUENCY (kHz) TEMPERATURE (C} OUTPUT FFT PLOT DYNAMIC RESPONSE RISE TIME DYNAMIC RESPONSE FALL TIME Vaer = 2.45Vp-p @ 1.225Vpe fe tkHz & & CODE = 1FFF (HEX) 5V/div SVidiv s 5 NOTE: RELATIVE TO FULL-SCALE 3 = out our. a Widiv Widiv x epsidiv i 05 16 27) 38 49 80 aes = 2048 Kt Veer 2.018 Qusidiv FREQUENCY (kHz) 9-80 MAXLMLow-Power, Dual, 13-Bit Voltage-Output DACs with Serial Interface Typical Operating Characteristics (continued) (Vop = +3V, RL = 10kQ, CL = 100pF, OS_pins tied to AGND, unless otherwise noted.) REFERENCE VOLTAGE INPUT A 5 TOTAL HARMONIC DISTORTION 2 FREQUENCY RESPONSE SUPPLY CURRENT vs. TEMPERATURE PLUS NOISE vs. FREQUENCY oO 560 30 ey , sale , Var = Vv Vece = Vp-p @ 1Vpc 3 tr 50 Ream CODE = 1FFF (HEX) 49 CODE = TFFF (HEN) a a = 52 2 3 2 eS E g 500 = 50 3 B 480 3 | 2 > 3 f 3 .* CODE = 0000 (HEX a r <= aA 40 = {HEX} / a -70 45 Veer = 0.67Vp-p @ 420 i mal, CODE = 1FFF WH 400 -80 jth] On 1 320-640 9501280 (1800 55-35-15 5 2 45 65 85 105 125 1 te 00s ally FREQUENCY (kHz} TEMPERATURE (C} FREQUENCY (kHz) SHUTDOWN CURRENT FULL-SCALE ERROR vs. LOAD REFERENCE FEEDTHROUGH AT tkitz vs. TEMPERATURE 05 -50 30 Vere = 1.25V 60 Vace = 2p-p @ Wn 28 0 f = 1kHz x 70 F- CODE 0000 (HEX) z 28 2 S -00 = 24 ge 05 ~ z 2 = 20 f- NOTE: RELATIVE T0 FULL-SCALE OUTPUT = 22 ad ~ aw 1.0 B -100 z 20 z 2 110 8 18 3 ZB 429 2 16 - 14 20 430 140 12 25 -150 10 a4 1 10 400 05 10 15 20 25 30 35 4.0 45 50 55 55-35-15 5 25 45 (65 85 105 125 Ry KG) FREQUENCY (kHz) TEMPERATURE (C) OUTPUT FFT PLOT OYNAMIC RESPONSE RISE TIME DYNAMIC RESPONSE FALL TIME na 9 won Var = 1.4Vp-p @ 0.75V; cs cs 10 eae oP ep Witiv 2vidiv -20 CODE = 1FFF (HEX) S 30 = 2 -40 = B 50 = 6 a 70 OUT_ OUT_ = Soomividiv S0Omvidiv -80 -90 -100 , " 05 16 27 38 49 60 ausidiv us/div FREQUENCY {kHz} Vaeg = 1.25V Vage = 1.25 MAAXIAA 9-91MAX5150/MAX5151 Low-Power, Dual, 13-Bit Voltage-Output DACs with Serial Interface Typical Operating Characteristics (continued) (Vop = +5V (MAX5 150), Vop = +3V (MAX5151), Ri = 10kQ, CL = 100pF, OS_ pins tied to AGND, unless otherwise noted.) MAX5150/MAX5151 SUPPLY CURRENT MAXS150 vs. SUPPLY VOLTAGE MAJOR-CARRY TRANSITION 0.65 7 sy 2 m= tTTITIE CODE = {FFF HEX ie - 8 _ 9.60 ? 2 g i ; |) - | 3 Z 055 oa an Ys MAXS150 : avidiv z 050 P+ MAX5151 : = A faereerttne oto our. r i Somvidiv 0.45 a 7 : AC COUPLED CODE = 0000 HEX Lo 0.40 i 20 25 30 35 40 45 50 55 60 SUPPLY VOLTAGE (V) Sus/div TRANSITION FROM 1000 HEX TO OFFF HEX MAXS150 DIGITAL FEEDTHROUGH 5 QUTA 3 SCLK 5V/div 5Vidiv OUTA OUTB SO0uV/div 200Vidiv AC COUPLED AC COUPLED 250ps/div 2.5ysidiv Vace = 2.048V. GAIN = +2, CODE 1FFF HEX 9-92 PRAKILAALow-Power, Dual, 13-Bit Voiltage-Output DACs Pin Description PIN NAME FUNCTION 1 AGND Analog Ground 2 OUTA DAC A Output Voltage 3 OSA DAC A Offset Adjustment 4 REFA Reference for DAC A 5 rol Conte a O and registers 6 cs Chip-Setect Input 7 DIN Serial-Data input 8 SCLK Serial-Register Clock input 9 DGND Digital Ground 10 DOUT Serial-Data Output 11 UPO User-Programmable Output 42 POC Power-Down Lockout. The device can- nat pe powered down when PBL is low. 13 REFB Reference for DAC B 14 OSsB DAC B Offset Adjustment 15 OUTB DAC B Output Voltage 16 Vop Pos.tive Power Supply Detailed Description The MAX5150/MAX5151 dual, 13-bit, voltage-output DACs are easily configured with a 3-wire serial inter- face. These devices include a 16-bit data-in/data-out shift register, and each DAC has a double-buffered input composed of an input register and a DAC register (see Functional Diagram). In addition, trimmed internal resistors produce an internal gain of +2 that maximizes output voltage swing. The amplifier's offset-adjust pin allows for a DC shift in the DACs output. Both DACs use an inverted R-2R ladder network that produces a weighted voltage proportional to the input voltage value. Each DAC has its own reference input to facilitate independent full-scale values. Figure 14 depicts a simplified circuit diagram of one of the two DACs. Reference Inputs The reference inputs accept both AC and DC values with a voltage range extending from OV to (Vop - 1.4V). Determine the output veltage using the following equa- tion (OS_ = AGND): PAAXILAA with Serial Interface aR aR De 9 6 REF CC + ye + AGND CC d) SHOWN FOR ALL 1s ON DAC Figure 1. Simplified DAC Circuit Diagram Vout = (VREF x NB / 8192) x2 where NB is the numeric value of the DACs binary input code (0 to 8191) and Vree is the reference volt- age. The reference input impedance ranges from 14kQ (1555 hex) to several giga ohms (with an input code of 0000 hex). The reference input capacitance is code dependent and typically ranges from 15pF with an input code of all zeros to SOpF with an input code of all ones. Output Amplifier The output amplifiers on the MAX5150/MAX5151 have internal resistors that provide for a gain of +2 when OS_ is connected to AGND. These resistors are trimmed to minimize gain error. The output amplifiers have a typi- cal slew rate of 0.75V/us and settle to 1/2LSB within 16us, with a load of 10kQ in parallel with 100pF. Loads less than 2kQ degrade performance. The OS_. pin can be used to produce an adjustable off- set voltage at the output. For instance, to achieve a 1V offset. apply -1V to the OS_ pin to produce an output range from 1V to (1V + VRE x 2). Note that the DACs output range is still limited by the maximum output volt- age specification. Power-Down Mode The MAX5150/MAX5151 feature a software-program- mable shutdown mode that reduces the typical supply current to 2uA. The two DACs can be shutdown inde- pendently, or simultaneously using the appropriate pro- gramming command. Enter shutdown mode by writing the appropriate input-contro! word {Table 1). in shut- down mode, the reference inputs and amplifier out- 9-93 . oO ~ S ; oO ~ oO m=Low-Power, Dual, 13-Bit Voltage-Output DACs with Serial interface Table 1. Seriat-Interface Programming Commands = i) 16-BIT SERIAL WORD ~ FUNCTION IN AO C1 CO | DT Reesssseeeesceeesseee DO (MSB) (LSB) 0 0 1 13-bit DAC data Load input register A; DAC registers are unchanged. = 1 0 1 13-bit DAC data Load input register B; DAC registers are unchanged. 8 Qo 4 0 13-bit DAC data Load input register A; all DAC registers are updated. 8 1 1 0 13-bit DAC data Load input register B; all DAC registers are updated. bi Load all DAC registers from the shift register ) 0 1 ' 1S-bILDAC data (start up both DACs with new data.). Update both DAC registers from their respective input registers 5 ' 0 0 POOOAHAAKINK (start up both DACs with data previously stored in the input registers). = 1 1 1 XXXXXAKXKAXKK Shut down both DACs (provided PDL = 1). Update DAC register A from input register A o 0 0 0 1 x 2000000 (start up DAC A with data previously stored in input register A). Update DAC register B from input register B 0 0 o 10 1 x xxE0o00K (start up DAC B with data previously stored in input register B). 0 0 0 11-0 X XXXxxxxXX Shut down DAC A (provided POL = 1). 0 Q 0 11 4 x x0OKKKXx Shut down DAC B (provided PDL = 1). 0 0 0 O 1 OX XXXXKXXxX UPO goes low (default), 0 0 0 O 1 1X XXXXXXKXX UPO goes high. 0 Go 0 10 0 1 xxxxxxxxx Mode 1, DOUT clocked out on SCLKs rising edge. 0 0 0 1.0 0 0 xxxxxxxxx Mode 0, DOUT clocked out on SCLKs falling edge (default). 0 0 0 0 0 O x XXXxxxxxxx No operation (NOP). x = Don care Note: When AO, C1, and CO = 0, then D12, D11, D10, and D9 become control bits. MAAXILIA MAX5150 MAX5151 SCLK DIN SK MICROWIRE PORT $0 a yo Figure 2. Connections for Microwire 9-94 puts become high impedance, and the serial inter- face remains active. Data in the input registers is saved, allowing the MAX5150/MAX5151 to recall the output state prior to entering shutdown when returning to normal mode. Exit shutdown by recalling the previ- ous condition or by updating the DAC with new infor- mation. When returning to normal operation (exiting shutdown), wait 20us for output stabilization. Serial interface The MAX5150/MAX5151 3-wire serial interface is com- patible with both Microwire (Figure 2) and SPI/QSPI (Figure 3) serial-interface standards. The 16-bit serial inout word consists of an address bit, two control bits, and 13 bits of data (MSB to LSB) as shown in Figure 4. MAAXLAALow-Power, Dual, 13-Bit Voltage-Output DACs 45V 8s DIN ft MOSI MA AXLAA SPYQSPI MAKS150 ci bag SCK PORT MAX5151 cS j 0 CPOL =0, CPHA= 0 Figure 3. Connections for SPI/QSPI Address Bits Contral Bits AO C1,C9 @ 1 Address/2 Control Bits > ~&_ 13 Data Bits t Figure 4. Serial-Data Format with Serial interface The address and control bits determine the MAX5150/ MAX5151's response, as outlined in Table 1. The MAX5150/MAX5151's digital inputs are double buffered, which allows any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC registers concurrently. The address and control bits allow the DACs to act independently. The 16-bit data can be sent as two 8-bit packets (SPI, Microwire), with CS low during this period. The address and control bits determine which register will be updat- ed, and the state of the registers when exiting shut- down. The 3-bit address/control determines the following: * registers to be updated * clock edge on which data is to be clocked out via the serial-data output (DOUT) * state of the user-programmabie logic output configuration of the device after shutdown. The general timing diagram of Figure 5 illustrates how data is acquired. Driving CS low enables the device to receive data. Otherwise, the interface control circuitry is disabled. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. As CS goes high, data is latched into the input and/or DAC registers depending on the address and control bits. The maxi- mum clock frequency guaranteed for proper operation is 10MHz. Figure 6 depicts a more detailed timing dia- gram of the serial interface. ws | 1 EXECUTED su LILI UU UU 8 on no XciX coXpreXoriXoroX os X08 X07 X06 X05 X de X08 Xb2X 01K oo XK a L_ COMMAND 9 16 Figure 5. Serial-Interface Timing Diagrarn 9-95 MAAXLAA = Oo mh, Q : 5 O mh Oo mhMAX5150/MAX5151 Low-Power, Dual, 13-Bit Voltage-Output DACs with Serial interface SCLK ~* tess _ icso ~ 7 beta = tlc a : ' t t y Ss ete iste ' ff \/ - ley i t : aa i fo tesw x : _ lep Oe tesy a! : Reon Figure 6. Detailed Seria!-interface Timing Diagram > SCLK SCLK SCLK PRAXIS SA MRAXISA MAXI MAX5150 MAX5150 MAX5150 MAXS151 MANX5151 MAX5151 > DIN DOUT DIN DOUT BIN oul Rh > cs cs cs TO OTHER SERIAL DEVICES Figure 7. Daisy Chaining MAXS150/MAX5 15 1s ON > eee SCLK ene cSt C32 TO OTHER acy SERIAL DEVICES CS3 > | t C8 4 65 cs MAAXLM MAAXISA PAAXLEM MAX5150 MAX5150 MAX5150 MAX5151 MAX5151 MAX5151 SCLK SCLK SCLK DIN DIN DIN Figure 8. Multiple MAX5 150/MAX5 151s Sharing a Common DIN Line 9-96 MAXLAALow-Power, Dual, 13-Bit Voltage-Output DACs Table 2. Unipolar Code Table (Gain = +2) DAC CONTENTS mse se ANALOG OUTPUT 4494100 -499704904 wer (S21) x 2 10000 0000 0001 eer (222) x2 10000 0000 0000 | +Vpee (se) x2 = Vper o1tdt otttt 44d weer (P| x 2 00000 0000 0001 +Vper (a x2 00000 0000 dda ov Serial-Data Output The serial-data output, DOUT, is the internal shift regis- ter's output. DOUT allows for daisy chaining of devices and data readback. The MAX5150/MAX5151 can be programmed to shift data out of DOUT on SCLKs falling edge (Mode 0) or on the rising edge (Mode 1). Mode 0 provides a lag of 16 clock cycles, which main- tains compatibility with SPI/QSPI and Microwire inter- faces. In Mode 1, the output data lags 15.5 clock cycles. On power-up, the device defaults to Mode 0. User-Programmable Logic Output (UPO) UPO allows an externa! device to be controlled through the serial interface (Table 1), thereby reducing the number of microcontraller |/O pins required: Power-Down Lockout Input (PDL) The power-down lockout pin (PDL) disables software shutdown when low. When in shutdown, transitioning PDL from high to low wakes up the part with the output set to the state prior to shutdown. PDL. can also be used to asynchronously wake up the device. Daisy Chaining Devices Any number of MAX5150/MAX5151s can be daisy chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain (Figure 7). Since the MAX5150/MAX5151's DOUT pin has an inter- nal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive load. Refer to the serial-data-out VOH and VoL specifications in the Electrical Characteristics. PAAXLAA with Serial Interface +5V/43V oS_ REF_ | maxim MAX5150 Re MAX 151 AGND GAIN = +2 Lb L Figure 9. Unipolar Output Circuit (Rail-to-Rail) +ON/43Y os_ REF_ [" MAMMA Nos MANS 150 R MAX5151 P OUT AGND vo Figure 10. Setting OS_ for Output Offset Figure 8 shows an alternate method of connecting sev- eral MAX5150/MAX5151s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy chain. More 1/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC. Applications Information Unipolar Output Figure 9 shows the MAX5150/MAX5151 configured for unipolar, rail-to-rail operation with a gain of +2. The MAX5150 can produce a OV to 4.096V output with 2.048V reference (Figure 9), while the MAX5151 can produce a range of OV to 2.5V with a 1.25V reference. Table 2 lists the unipolar output codes. An offset to the output can be achieved by connecting a voltage to OS_, as shown in Figure 10. By applying Vos_ = -1V, the output values will range between 1V and (1V + VREF X 2). 9-97 LSLSXVW/OSILSXVINNMAX5150/MAX5151 Low-Power, Dual, 13-Bit Voltage-Output DACs with Serial Interface Table 3. Bipolar Code Table DAC CONTENTS MSB LSB ANALOG OUTPUT ttad4 4444 1444 4035 : ee (2 1 40000 0000 00n1 Veer | ox rer (<abs] 10000 9000 0000 ov 1 OVlid 1414 1119 a sner (apg 4095 00000 0000 0cot - as \REF (=) 4096 00000 6000 0000 Vege | ee) = - per (See REF REF_ +8V/43V Yoo MAXIM a MAX5150 | MAXSI51 | INR DAC. > . ba DGND _AGND he oy TOLERANCES: 10k 20.1% Figure 11. Bipolar Output Circuit Bipolar Output The MAX5150/MAX5151 can be configured for a bipo- lar output, as shown in Figure 11, The output voltage is given by the equation (OS_ = AGND): Vout = Vrer [((2 x NB) / 8192) - 1] where NB represents the numeric value of the DACs binary input code. Table 3 shows digital codes and the corresponding output voltage for Figure 11's circuit. Using an AC Reference In applications where the reference has an AC signal component, the MAX5150/MAX5151 have multiplying capabilities within the reference input voltage range specifications. Figure 12 shows a technique for apply- ing a sinusoidal input to REF_, where the AC signal is offset before being applied to REF. 9-98 +5V/ Ww AC REFERENCE INPUT S00mVp-p REF Yoo R OS. t g| qt MAAXILMA MAX5150 AGND MAXSIST gn Vv a Figure 12. AC Reference Input Circuit PHOTODIODE REF Su Voo cI MAAXILAA RS MAX5150 < MAK5151 2 Yv = Rs Vout [uP } et pac. . DIN AGNO DGNO RPULLDOWN Figure 13. Digital Calibration Harmonic Distortion and Noise The total harmonic distortion plus noise (THD+N) is typ- ically less than -78dB at full scale with a 1Vp-p input swing at 5kHz. The typical -3dB frequency is 300kHz for both devices, as shown in the Typical Operating Characteristics. Digital Calibration and Threshold Selection Figure 13 shows the MAX5150/MAX5151 in a digital calibration application. With a bright light value applied to the photodiade (on), the DAC is digitally ramped until it trips the comparator. The microprocessor stores this high calibration value. Repeat the process with a dim light (off) to obtain the dark current calibration. PAAXLIALow-Power, Dual, 13-Bit Voltage-Output DACs with Serial interface MAAXLAA MAX5150 MAX5151 Vw we fFA & | _J input L_| pac SHIET REGA || REGA SCLK] | ReGisTER |_| input |_| pac DIN REGB] | REGB FI ace. mitt | L AGND DGND OSA OUTA Rt R2 R3 Vout ours AMY 4 R4 R Vour ={ cai} -Torrset oe ! i ] R4 2NB = [{Viy SNA} ( Re fy, RAE NB ) (4 ( NBig2 Yate) R3 [veer BS) NAIS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB Figure 14. Digital Contro! of Gain and Offset The microprocessor then programs the DAC to set an output voltage at the midpoint of the two calibrated val- ues, Applications include tachometers, motion sensing, automatic readers, and liquid clarity analysis. Digital Control of Gain and Offset The two DACs can be used to control the offset and gain for curve-fitting nonlinear functions, such as trans- ducer linearization or analog compression/expansion applications. The input signal is used as the reference for the gain-adjust DAC, whose output is summed with the output from the offset-adjust DAC. The relative weight of each DAC output is adjusted by R1, R2, R3, and R4 (Figure 14). Power-Supply Considerations On power-up, the input and DAC registers clear (set to zero code). For rated performance. VREF_ should be at least 1.4V below Vpop. Bypass the power supply wth a 4.7uF capacitor in parallel with a O.1pF capacitor to AGND. Minimize lead lengths to reduce lead induc- tance. Grounding and Layout Considerations Digital and AC transient signats on AGND can create noise at the output. Connect AGND to the highest quali- ty ground available. Use proper grounding techniques. such as a multilayer board with a low-inductance ground plane. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommend- ed. If noise becomes an issue, shielding may be required. 9-99 PRAAXLAA KS ESXVIW/OSLSXUWLow-Power, Dual, 13-Bit Voltage-Output DACs with Serial Interface MAX5150/MAX5151 Pin Configuration _Ordering Information (continued) PART TEMP.RANGE Pin-PackaGe_, 'NL TOP VIEW Ire (LSB) aco [1] 6] oo MAXS{S0AEPE -40C to +85C 16 Plastic DIP + 1/2 outa [2] 5] outs MAXSI50BEPE -40C to +85C 16 Plastic DIP +1 = MAXSISQAEEE -40C to +85C 16 QSOP 1/2 ole arr i - MAXS150BEEE -40C to +85C 16 QSOP + Masta a MAXS150BMJE _-55C to +125C 16 CERDIP af at [3 2] PL MAXSISIACPE OC to +70C 16 Plastic DIP xt as [6 1] wed MAXSI51BCPE _OC to +70C 16 PlasticDIP #2 ow [7 | [10] DouT MAXS51S1ACEE _OC to +70C__ 16 QSOP +1 seux [8] 9] GND MAXSIS1BCEE OPC 10 +70C 16 QSOP #2 MAXSIS1BC/ID OC to +70C__Dice* +1 DIP/QSOP MAXSIS1AEPE -40C to +85C 16 Plastic DIP +1 MAXS1SiBEPE -40C to +85C 16Plastic DIP #2 MAXSIS1AEEE -40C 10 +85C 16 QSOP +1 Chip Information MAXS151BEEE -40C to +85C 16 QSOP +2 MAXS1S1BMJE -55C to +125C 16 CERDIP** 2 TRANSISTOR COUNT: 3053 *Dice are tested at Ta = +25C, OC parameters only. SUBSTRATE CONNECTED TO AGND * Contact factory for availability. 9-100 MAAXLAA