The A8651 is an adjustable frequency, high output current,
PWM regulator that integrates a high-side, P-channel MOSFET
and a low-side, N-channel MOSFET. The A8651 incorporates
current-mode control to provide simple compensation, excellent
loop stability, and fast transient response. The A8651 uses
external compensation to accommodate a wide range of power
components to optimize transient response without sacrificing
stability. The A8651 regulates input voltages from 2.5 to 5.5 V,
down to output voltages as low as 0.8 V and is able to supply
up to 2 A of load current per regulator.
The A8651 features include an externally adjustable and
synchronizable switching frequency, an externally-set soft-
start time to minimize inrush currents, independent EN inputs,
and independent NPOR outputs with either 7.5 ms (A8651) or
120 µs (A8651-1) delay. The sleep mode current of the A8651
control circuitry is less than 5 μA. Protection features include
VIN undervoltage lockout (UVLO), pulse-by-pulse overcurrent
protection (OCP), hiccup mode short-circuit protection (HIC),
overvoltage protection (OVP), and thermal shutdown (TSD).
In addition, the A8651 provides open-circuit, adjacent pin
short-circuit, and short-to-ground protection at every pin to
satisfy the most demanding automotive applications.
A8651-DS, Rev. 8
• AEC-Q100 qualified
• Operating voltage range: 2.5 to 5.5 V
• UVLO stop threshold: 2.25 V (max)
• Dual outputs with up to 2 A output current per regulator
• Adjustable output voltage as low as 0.8 V
• Internal 80 mΩ high-side switching MOSFET
• Internal 55 mΩ low-side switching MOSFET
• Adjustable oscillator frequency ( fOSC
): 0.35 to 2.2 MHz
• Synchronizes to external clock: 1.2
× to 1.5
× fOSC
• 180° phase shift between switching regulators
• Sleep mode supply current less than 5 μA
• Soft-start time externally set via the SS pin
• Pre-biased startup capable
• Externally adjustable compensation
• Stable with ceramic output capacitors
• Independent enable inputs and NPOR output pins
• NPOR delay of 7.5 ms (A8651) or 120 µs (A8651-1)
• Adjustable current limiting (OCP) for each regulator
• Hiccup mode short-circuit protection (HIC)
• Overvoltage and overtemperature protection
• Open-circuit and adjacent pin short-circuit tolerant
• Short-to-ground tolerant at every pin
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
Typical Application Diagram
A8651
Package: 20-pin TSSOP with exposed
thermal pad (suffix LP)
Not to scale
Continued on the next page…
• GPS/infotainment
• Automotive audio
• Home audio
• Network and telecom
APPLICATIONS:
FB1
L
O1
PGND1
PGND2
V
IN
VIN1
GND
SW1
NPOR1
COMP1
ISET1
R
Z1
C
Z1
C
SS1
CP1
EN1
SS1
V
OUT1
V
OUT2
C
IN1
C
SYNC
EN1
20
16
17
19
2
3
4
1
18
15
A8651
C
O1
C
O2
R
SET1
5
FSET/SYNCSYNCin
VIN2
C
IN2
11
13
12
9
8
7
R
PU1
NPOR1
FB2
R
FB4
R
FB3
R
FB2
R
FB1
R
FSET
R
PU2
L
O2
SW2
NPOR2
NPOR2
10
14
6
COMP2
ISET2
R
Z2
C
Z2
C
SS2
C
P2
EN2
SS2
EN2
R
SET2
FEATURES AND BENEFITS DESCRIPTION
December 5, 2016
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The A8651 device is available in a 20-pin TSSOP package with
exposed thermal pad for enhanced thermal dissipation (suffix LP).
It is lead (Pb) free, with 100% matte-tin leadframe plating.
DESCRIPTION (CONTINUED)
Selection Guide
Part Number
Operating Ambient
Temperature Range
TA, (°C)
Package Packing [1] Leadframe Plating
A8651KLPTR-T [2]
–40 to 125
20-pin TSSOP with
exposed
thermal pad
4000 pieces per
13-in. reel 100% matte tin
A8651KLPTR-T-1
1 Contact Allegro™ for additional packing options.
2 Part variant discontinued. Date of status change: September 1, 2016. Suggested replacement: A8651KLPTR-T-1.
Table of Contents
Specifications 2
Absolute Maximum Ratings 3
Thermal Characteristics 3
Top-Level Functional Block Diagram 4
Detailed Functional Block Diagram 5
Pinout Diagram and Terminal List 6
Electrical Characteristics 7
Characteristic Performance 10
Timing Diagram 12
Functional Description 13
Overview 13
Reference Voltage 13
Oscillator/Switching Frequency (RFSET, fOSC) 13
Transconductance Error Amplifier 13
Slope Compensation 13
ENx, VINx, and Sleep Mode 14
Synchronization (FSET/SYNC) 14
Power MOSFETs 14
Pulse Width Modulation (PWM) 14
Current Sense Amplifier 14
Soft-Start (Startup) and Inrush Current Control 14
Pre-Biased Startup 15
Active Low Power-On Reset (NPORx) 16
Protection Features 16
Undervoltage Lockout (UVLO) 16
Thermal Shutdown (TSD) 16
Overvoltage Protection (OVP) 16
Pulse-by-Pulse Overcurrent Protection (OCP) 16
Output Short Circuit (Hiccup Mode) Protection 17
Design and Component Selection 20
Setting the Output Voltage (VOUT1
, RFBx ) 20
PWM Switching Frequency (RFSET) 20
Output Inductor (LO
) 21
Output Capacitors 22
Input Capacitors 22
Soft-Start and Hiccup Mode Timing (CSS1) 23
Compensation Components (RZ, CZ, CP) 24
A Generalized Tuning Procedure 26
Power Dissipation and Thermal Calculations 28
PCB Component Placement and Routing 30
Package Outline Diagram 33
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings1
Characteristic Symbol Notes Rating Unit
VIN1 and VIN2 to GND VIN –0.3 to 6.0 V
SW1 and SW2 to GND2VSW
Continuous –0.3 to VIN + 0.3 V
t < 50 ns –1.0 to VIN +2.0 V
All Other Pins – –0.3 to 6.0 V
Operating Ambient Temperature TAK temperature range –40 to 125 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
1 Operation at levels beyond the ratings listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute
Maximum-rated conditions for extended periods may affect device reliability.
2 SW1 and SW2 have internal clamp diodes to GND and VIN
. Applications that forward bias these diodes should take care not to exceed the A8651 package power
dissipation limits.
Thermal Characteristics: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions* Value Unit
Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 32 ºC/W
*Additional thermal information available on the Allegro website.
SPECIFICATIONS
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
SWITCHER #1
(SW1)
ADJUSTABLE
VOUT
SYNCHRONOUS
BUCK
FB1
SW1
VIN1
COMP1
CLK0°
SS1
80 mΩ
NPOR1
TSD
VIN1 UVLO
VREF &
POR
VIN1START
VIN1STOP
55 mΩ
EN1
ISET1
FSET/
SYNC
FB2
SW2
VIN2
COMP2
SS2
80 mΩ
NPOR2
VIN2
UVLO
SWITCHER #2
(SW2)
ADJUSTABLE
VOUT
SYNCHRONOUS
BUCK
55 mΩ
EN2
ISET2
CLK180°
POR &
VREF
Note: VIN1 supplies the bandgap (VREF), oscillator, TSD, and other critical circuits
fOSC or fSYNC
with
180° shift
ISENSE2
ISENSE1
PGND1
PGND2
GND
A8651
2
2
TSD
TSD
VIN2START
VIN2STOP
fSW1
fSW2
Top-Level Functional Block Diagram
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Detailed Functional Block Diagram
ISETx
GAIN
OFF
OFF
S
R
Q
Q
FAULT = 1 IF:
EN = 0 or
UVLO = 1
OVP
COMP
HICCUP = 1 IF:
VFB < 700 mV and
7 OCP EVENTS
VREF
CURRENT
ENx
SSx
FBx
UV / OV
125 ns
RESET
DOM
OV
MIN_T off
GNDx
FAULT
+
-
Falling
Delay
Slope
Comp
ADJ
Oscillator
CLKin
ADJ2 fSW
ADJ1
ADJ3
UVLOx
VSSoffs
200 mV
COMPx
PWMoffset
380 mV
UV
UV
COMP
+
-
+
ERROR AMP
NPORx
+
-
TSD
92% × VREF
88% × VREF
A8651
1 of 2 regulators shown
115% × VREF
VINx
10 ns
1.5 kΩ
POR
VIN
VIN
PWM
COMP
20 µA
10 µA
OFF
CLKx
Clamp
1.65 V (typ)
1.25 V (typ)
55 mΩ
PROTECTIONS
EN_OCP_COUNT
UVLO
EN / CLR
HICCUP
LATCHED
HIC RST
CURRENT OCP
FBx
+
-
80 mΩ
HICCUP
NON-OVERLAP
FBx
100 kΩ
SWx
PGNDx
150 nA
OCP
+
-
EN
OFF OFF
CLAMP ACTIVE
ENx
OCP
IF VFB > 400 mV, fSW = CLKx
IF VFB < 400 mV & CLAMP ACTIVE & OCP, fSW = CLKx/4
CLAMP ACTIVE
Pad
IF VFB < 400 mV, fSW = CLKx/2
2 kΩ
111% × VREF
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package LP, 20-Pin TSSOP with Exposed Thermal Pad Pinout Diagram
Terminal List Table
Number Name Function
1, 10 SW1, SW2
The drains of the internal high-side P-channel MOSFETs. The output inductors should be connected to these pins.
The output inductors should be placed as close as possible to these pins and be connected with relatively wide
traces.
2, 9 PGND1, PGND2 Power ground pins for switcher 1 and switcher 2.
3, 8 EN1, EN2 Inputs to enable switcher 1 and/or enable switcher 2.
4, 7 ISET1, ISET2 Pulse–by-pulse current limit setting pins.
5 FSET/SYNC A resistor, RFSET, from this pin to GND sets the base PWM switching frequency (fOSC). If an external clock is AC-
coupled to this pin by a 22 pF capacitor, the switching frequency of the regulator can be increased higher than fOSC.
6, 15 NPOR2, NPOR1 Active low, open-drain fault indication outputs, with fixed delay.
11, 20 VIN2, VIN1
Power inputs for the control circuits and the sources of the internal high-side P-channel MOSFETs. VIN1 is the
primary supply and must be present for the A8651 to operate. At least one high quality ceramic capacitor must be
placed very close to these pins.
12, 19 SS2, SS1 Soft-start pins. Connect a capacitor, from these pins to GND to set the soft-start time. These capacitors also
determine the hiccup period during an overcurrent condition.
13, 17 COMP2, COMP1
Outputs of the error amplifiers and compensation nodes for the current mode control loops. Connect a series RC
network from these pins to GND for loop compensation. See the Design and Component Selection section of this
datasheet for further details.
14, 18 FB2, FB1 Feedback (negative) inputs to the error amplifiers. Connect a resistor divider from the converter output nodes to
these pins to program the output voltages.
16 GND Ground.
–PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground
plane(s) of the PCB with at least 6 vias, directly in the pad.
PAD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SW1
PGND1
EN1
ISET1
FSET/SYNC
NPOR2
ISET2
EN2
PGND2
SW2
VIN1
SS1
FB1
COMP1
GND
NPOR1
FB2
COMP2
SS2
VIN2
Pinout Diagram and Thermal Characteristics
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Input Voltage Specications
Operating Input Voltage Range VIN 2.5 −5.5 V
Undervoltage Lockout (UVLO)
Start Threshold VINSTART VIN1 = VIN2, rising 2.00 2.22 2.45 V
Undervoltage Lockout (UVLO)
Stop Threshold VINSTOP VIN1 = VIN2, falling 1.80 2.02 2.25 V
Undervoltage Lockout (UVLO)
Hysteresis VUVLO(HYS) −200 −mV
Input Currents
Input Quiescent Current IQ
VEN1 = VEN2 = 5 V, VFB1 = VFB2 = 1 V, no PWM
switching −3 6 mA
Input Sleep Supply Current IQSLEEP VINx = VSWx = 5 V, VEN1 = VEN2 ≤ 0.4 V − 0.2 5 μA
Reference Voltage
Reference (Feedback) Voltage VREF 2.5 V < VIN1 = VIN2 < 5.5 V, VFBx = VCOMPx 792 800 808 mV
Error Amplier
Feedback Input Bias Current(1) IFB
VCOMPx = 1.5 V, VFBx regulated so that
ICOMPx = 0 A – –150 –300 nA
Open Loop Voltage Gain(2) AVOL −65 −dB
Transconductance gm
ICOMPx = 0 μA, VSSx > 500 mV 550 750 950 μA/V
0 V < VSSx < 500 mV – 250 – μA/V
Source Current IEA(SRC) VFBx < 0.8 V, VCOMPx = 1.5 V −–50 − μA
Sink Current IEA(SINK) VFBx > 0.8 V, VCOMPx = 1.5 V −+50 − μA
Maximum Output Voltage VEAVO(max) 1.00 1.25 1.50 V
COMP Pulldown Resistance RCOMP FAULT = 1, HICCUP = 1 or VEN1 = VEN2 ≤ 0.4 V − 1.5 − kΩ
Pulse-Width Modulation (PWM)
PWM Ramp Offset VPWMOFFSET VCOMPx for 0% duty cycle −380 −mV
High-Side MOSFET Minimum
Controllable On-Time tON(MIN) −65 105 ns
Low-Side MOSFET Minimum
On-Time tOFF(MIN)
Does not include total gate driver non-overlap
time, 2 × tOFF
−50 100 ns
Gate Driver Non-Overlap Time(2) tOFF −15 −ns
COMP to SW Current Gain gmPOWER −4.5 −A/V
Slope Compensation(2) SE
RSETx = 41.2 kΩ, fSW = 2.0 MHz 2.1 2.5 2.9 A/μs
RSETx = 41.2 kΩ, fSW = 0.35 MHz 0.36 0.44 0.51 A/μs
RSETx = 30.9 kΩ, fSW = 2.0 MHz 1.0 1.4 1.9 A/μs
RSETx = 30.9 kΩ, fSW = 0.35 MHz 0.17 0.25 0.35 A/μs
Continued on the next page…
ELECTRICAL CHARACTERISTICS: valid at VIN1 = VIN2 = 5 V, –40°C ≤ TA = TJ ≤ 125°C, unless otherwise specied
Note 1: For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as
going into the node or pin (sinking).
Note 2: Ensured by design and characterization, not production tested.
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
MOSFET Parameters
High-Side MOSFET On-Resistance RDS(on)HS IDSx = 100 mA −80 − mΩ
SW Node Rise Time(2) tr(SW) −12 −ns
High-Side MOSFET Leakage Current IDSS(HS)
VENx ≤ 0.4 V, VSWx = 0 V, VINx = 5 V,
–40°C < TA = TJ < 85°C(3) − − 4μA
VENx ≤ 0.4 V, VSWx = 0 V, VINx = 5 V,
TA = TJ = 125°C − − 25 μA
Low-Side MOSFET ON Resistance RDS(on)LS IDSx = 100 mA −55 − mΩ
Low-Side MOSFET Leakage Current IDSS(LS)
VENx ≤ 0.4 V, VSWx = 5 V,
–40°C < TA = TJ < 85°C (3) − − 1μA
VENx ≤ 0.4 V, VSWx = 5 V, TA = TJ = 125°C − − 10 μA
Oscillator Frequency
Oscillator Frequency fOSC
RFSET = 10.2 kΩ 1.98 2.20 2.45 MHz
RFSET = 24.9 kΩ 0.90 1.00 1.10 MHz
RFSET = 82.5 kΩ 325 375 425 kHz
SW1 to SW2 Phase Delay(2) Φ1,2 −180 −deg.
FSET/SYNC Input
FSET/SYNC High Threshold VFSETSYNC(H) − − 1.8 V
FSET/SYNC Low Threshold VFSETSYNC(L) 0.4 − − V
FSET/SYNC Pin Voltage VFSETSYNC Without external SYNCin signal −0.8 −V
FSET/SYNC Pin Current IFSETSYNC Without external SYNCin signal 9 −90 µA
Maximum SYNC Frequency fSYNCM − − 2.5 MHz
SYNC Frequency Range(2) fSYNC
1.2 ×
fOSC
−1.5 ×
fOSC
–
SYNC Duty Cycle (2) DSYNC 50 60 70 %
Synchronization Minimum On-Time tONSYNC 150 − − ns
Synchronization Minimum Off-Time tOFFSYNC 150 − − ns
Enable Inputs
EN High Threshold VENIH VENx rising − − 1.8 V
EN Low Threshold VENIL VENx falling 0.8 − − V
EN Hysteresis VENHYS VENIH – VENIL −200 −mV
EN Input Resistance REN 50 100 − kΩ
EN Shutdown Delay(2) tdEN(SD)
From ENX transitioning low to SWx switching
stops 0 5 10 µs
Continued on the next page…
ELECTRICAL CHARACTERISTICS (continued): valid at VIN1 = VIN2 = 5 V, –40°C ≤ TA = TJ ≤ 125°C, unless otherwise speci-
ed
Note 2: Ensured by design and characterization, not production tested.
Note 3: Specifications at 25°C or 85°C are ensured by design and characterization, not production tested at these temperatures.
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Overcurrent Protection (OCP) and Hiccup Mode
Pulse-by-Pulse Current Limit ILIM
RSET = 41.2 kΩ, duty cycle = 5% 3.5 4.1 4.7 A
RSET = 41.2 kΩ, duty cycle = 90%(2) 2.2 3.0 3.8 A
RSET = 30.9 kΩ, duty cycle = 5% 1.9 2.4 2.9 A
RSET = 30.9 kΩ, duty cycle = 90%(2) 1.1 1.8 2.3 A
Hiccup Disable Threshold VHICDIS VFBx rising −740 −mV
Hiccup Enable Threshold VHICEN VFBx falling −700 −mV
OCP / HICCUP Count Limit2OCPLIMIT
HICCUP enabled (see Functional Block
diagram), OCP pulses −7−counts
Soft-Start (SS pin)
Soft-Start Offset Voltage VSSOFFS VSSx rising due to ISSSU 100 200 270 mV
Soft-Start Fault/Hiccup Reset Voltage VSSRESET VSSx falling due to ISSHIC −120 185 mV
Soft-Start Startup (Source) Current ISSSU
VSSx = 1 V, HICCUP = FAULT = 0 (see
Functional Block diagram) −10 –20 −30 μA
Soft-Start Hiccup (Sink) Current ISSHIC
VSSx = 0.5V, HICCUP = 1 (see Functional Block
diagram) 5 10 20 μA
Soft-Start Input Resistance RSS
FAULT (see Functional Block diagram) = 1 or
ENx = 0 −2− kΩ
Soft-Start to VOUT Delay Time tSS(DELAY) CSSx = 10 nF −85 − μs
VOUT Soft-Start Ramp Time tSS CSSx = 10 nF −400 − μs
Soft-Start Switching Frequency fSW(SS)
0 V < VFBx < 400 mV, VCOMPx = VEAVO(max)
,
IDSx > ILIMx (2) −fOSC / 4 − −
0 V < VFBx < 400 mV −fOSC / 2 − −
VFBx > 400 mV −fOSC − −
NPOR Outputs
NPOR Undervoltage Threshold VNPORUV Percentage of VREF
, VFBx rising 89 92 95 %
NPOR Undervoltage Hysteresis VNPORUVhys Percentage of VREF
, VFBx falling 2 4 6 %
NPOR Overvoltage Threshold VNPOROV Percentage of VREF
, VFBx rising 112 115 118 %
NPOR Overvoltage Hysteresis VNPOROVhys Percentage of VREF
, VFBx falling 2 4 6 %
NPOR Rising Delay (A8651) tNPOR
4.0 7.5 11 ms
NPOR Rising Delay (A8651-1) 65 120 175 µs
NPOR Low Output Voltage VNPOR(L)
2.5 V < VIN1 = VIN2 < 5 V, INPOR = 4 mA — — 400 mV
VIN1 = VIN2 =1.2 V, INPOR = 2 mA — — 800 mV
NPOR Leakage Current(1) INPOR(LEAK) VNPORx = 3.3 V — — 1 µA
Thermal Protection (TSD)
Thermal Shutdown Threshold(2) TSD(th) Temperature rising 155 170 185 ºC
Thermal Shutdown Hysteresis(2) TSD(HYS) Temperature falling −20 −ºC
Note 1: For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined
as going into the node or pin (sinking).
Note 2: Ensured by design and characterization, not production tested.
ELECTRICAL CHARACTERISTICS (continued): valid at VIN1 = VIN2 = 5 V, –40°C ≤ TA = TJ ≤ 125°C, unless otherwise speci-
ed
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Performance
Oscillator Frequency versus Temperature
VIN UVLO Start and Stop Thresholds
versus Temperature
NPOR Overvoltage and Undervoltage Thresholds
versus Temperature
Pulse-by-Pulse Current Limit at tON(MIN)
versus Temperature
Error Amplifier Transconductance
versus Temperature
792
794
796
798
800
802
804
806
808
-50 -25 0 25 50 75 100 125 150
Reference Voltage, VREF (mV)
Temperature (°C)
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
-50 -25 0 25 50 75 100 125150
Oscillator Frequency, f
OSC
(MHz)
Temperature (°C)
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
-50 -25 0 25 50 75 100 125 150
Input Voltage, VIN (V)
Temperature (°C)
UVLO Start Threshold, V
INSTART
UVLO Stop Threshold, V
INSTOP
80
85
90
95
100
105
110
115
120
-50 -25 0 25 50 75 100125150
Threshold (% of VFB)
Temperature (°C)
V
NPOROV
, V
FB
rising
V
NPOROV
, V
FB
falling
V
NPORUV
, V
FB
rising
V
NPORUV
, V
FB
falling
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
-50 -25 0 25 50 75 100125 150
Current Limit , ILIM (A)
Temperature (°C)
550
600
650
700
750
800
850
900
950
-50 -25 0 25 50 75 100 125 150
Transconductance, gm (µA/V)
Temperature (°C)
Reference Voltage versus Temperature
f
OSC
= 2.2 MHz
f
OSC
= 1 MHz
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
11
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Enable High and Low Thresholds
versus Temperature
Soft Start Startup and Hiccup Currents
versus Temperature
NPOR Low Output Voltage
versus Temperature
Hiccup Enable and Disable Thresholds
versus Temperature
Input Sleep Supply Current
versus Temperature
High- and Low-Side MOSFETs Leakage Current
versus Temperature
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
-50 -25 0 25 50 75 100125150
EN Pin Threshold (V)
Temperature (°C)
EN High Threshold, V
ENIH
EN Low Threshold, V
ENIL
5
7
9
11
13
15
17
19
21
23
25
-50 -25 0 25 50 75 100125150
SS Pin Current (µA)
Temperature (°C)
SS Startup Current, I
SSSU
SS Hiccup Current, I
SSHIC
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
-50 -25 0 25 50 75 100 125 150
NPOR Low Output Voltage,
V
NPOR(L)
(mV)
Temperature (°C)
I
NPOR
= 4 mA
I
NPOR
= 2 mA
550
575
600
625
650
675
700
725
750
775
800
825
850
-50 -25 0 25 50 75 100 125 150
Hiccup Threshold (mV)
Hiccup Enable Threshold,V
HICEN
Hiccup Disable Threshold, V
HICDIS
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-50 -25 0 25 50 75 100 125 150
Input Sleep Supply Current,
I
QSLEEP
(µA)
Temperature (°C)
0
5
10
15
20
25
30
35
40
-50 -25 0 25 50 75 100 125 150
Leakage Current (µA)
Temperature (°C)
High-Side MOSFET Leakage Curent, I
DSS(HS)
Low-Side MOSFET Leakage Curent, I
DSS(LS)
Temperature (°C)
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
12
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x
7
x
7
Vout shorted to GND
MODE
ENx
TSD
HIC
_
ENx
HICCUPx
VINx
VOUTx
SSx
COMPx
SWx
/
SS
PWM
O
C
HICCUP
O
C
SS
PWM
PWM
PWM
S
S
/
SS
SS
OFF
/
TSD
OCx
Fsw
SS
PWM
OFF
/
UVLO
OFF
/
DISABLED
OFF
/
UVLO
OFF
/
DISABLED
HICCUP
EN glitches low for
more than td
EN
,
SD
VIN dropout
/
Fsw
/
Fsw
/
Fsw
/
Fsw
/
TSD
V
SS
,
RESET
V
SS
,
OFFS
PWM
OFFSET
HIC
DIS
HIC
VIN
STOP
EN
VIN
START
NPORx
t
NPOR
NPOR set
below VIN
STOP
EA
VO
(
max
)
td
EN
,
SD
Timing Diagram (one of two regulators shown)
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
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FUNCTIONAL DESCRIPTION
Overview
The A8651 is a dual synchronous PWM regulator that incorpo-
rates all the control and protection circuitry necessary to satisfy
a wide range of applications. The A8651 employs current mode
control to provide fast transient response, simple compensa-
tion, and excellent stability. The features of the A8651 include,
for each of the two regulators: a precision reference, an adjust-
able switching frequency, a transconductance error amplifier, an
enable/synchronization input, integrated high-side and low-side
MOSFETs, adjustable Soft-Start, pre-bias startup, low-current
sleep mode, and a Power-On Reset output (NPOR). The protec-
tion features of the A8651 include undervoltage lockout (UVLO),
pulse-by-pulse overcurrent protection (OCP), hiccup mode
short-circuit protection (HIC), overvoltage protection (OVP), and
thermal shutdown (TSD). In addition, the A8651 provides open-
circuit, adjacent pin short-circuit, and pin-to-ground short-circuit
protection.
Reference Voltage
The A8651 incorporates an internal reference that allows output
voltages as low as 0.8 V. The accuracy of the internal reference is
±1% across the operating temperature range. The output voltage
for each of the regulators is adjusted by connecting a resistor
divider (RFB1-RFB2 and RFB3-RFB4 in the Typical Application
diagram) from VOUTx to the corresponding FBx pin of the A8651.
Oscillator/Switching Frequency (RFSET, fOSC)
The PWM switching frequency of the A8651 is adjustable from
350 kHz to 2.2 MHz and has an accuracy of about ±10% across
the operating temperature range. Connecting a resistor ( RFSET
)
from the FSET/SYNC pin to GND, as shown in the Typical
Application diagram, sets the base switching frequency, fOSC
.
An FSET/SYNC resistor with ±1% tolerance is recommended.
A graph of switching frequency versus RFSET resistor value is
shown in the Design and Component Selection section of this
datasheet.
Transconductance Error Amplifier
The transconductance error amplifier’s primary function is to
regulate the converter’s output voltage. The error amplifier for
one of the regulators is shown in Figure 1. It is shown as a three-
terminal input device with two positive and one negative input.
The negative input is simply connected to the FBx pin and is used
to sense the feedback voltage for regulation. The two positive
inputs are used for soft-start and regulation. The error ampli-
fier performs an “analog OR” selection between its two positive
inputs. The error amplifier regulates to either the soft-start pin
voltage minus 200 mV or the A8651’s internal reference, which-
ever is lower.
To stabilize the regulator, a series RC compensation network
(RZ and CZ
) must be connected from the error amplifier output
(COMPx pin) to GND as shown in the Typical Applications
diagram. In some applications, an additional, low-value capacitor
(CP
) may be connected in parallel with the RZ-CZ compensation
network to reduce the loop gain at higher frequencies. However
if the CP capacitor is too large, the phase margin of the converter
may be reduced.
If the regulator is disabled or a fault occurs, the correspond-
ing COMPx pin is immediately pulled to GND via approxi-
mately 1.5 kΩ and PWM switching is inhibited. During startup
(VSSx < 500 mV), the transconductance of the error amplifier is
reduced to approximately one-third of the normal operating level
to minimize transients when the system is requesting on-times
less than or equal to the minimum controllable on-time.
Slope Compensation
The A8651 incorporates internal slope compensation to allow
PWM duty cycles above 50% for a wide range of input/output
voltages, switching frequencies, and inductor values. As shown in
the Detailed Functional Block diagram, the slope compensation
signal is added to the sum of the current sense and PWM Ramp
Offset (VPWMOFFSET
). The amount of slope compensation is
scaled directly with the switching frequency.
Figure 1: The A8651 Error Amplier (for one regulator)
+
-
+
Error Amplifier
COMPx
SSx
FBx
V
REF
800 mV
200 mV
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
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A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
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ENx, VINx, and Sleep Mode
The A8651 provides two independent inputs, VIN1 and VIN2,
to sequence the output voltages after the A8651 is powered
up. However, VIN1 is the primary supply input. VIN1 must be
greater than VINSTART or the A8651 will not come out of sleep
mode. VIN2 can start or stop regulator 2 but cannot wake up the
A8651.
If the voltage at EN1 or EN2 is driven below VENIL (800 mV)
for more than tdEN(SD) (approximately 5 µs), the regulator stops
switching.
In sleep mode (EN1< VENVIL ), for more than tdEN(SD), the control
circuits are de-biased and draw less than 5 μA from VIN. How-
ever, the total current drawn by the VIN pin will be the sum of
the current drawn by the control circuitry ( IQSLEEP
) plus any
leakage due to the high-side MOSFETs ( IDSS(HS)
).
Synchronization (FSET/SYNC)
By using a 22 pF capacitor (CSYNC ) to AC-couple an external
clock to the FSET/SYNC pin, as shown in Figure 2, the switch-
ing frequency of the A8651 can by increased from 1.2 × fOSC
to 1.5 × fOSC. In these equations, fOSC is the typical frequency
determined by the RFSET resistor. The applied SYNC waveform
must satisfy the conditions shown in the Electrical Characteristics
table. The SYNC waveform must simultaneously satisfy three
conditions for all operating frequencies: duty cycle (DSYNC),
minimum on-time (tONSYNC), and minimum off-time (tOFFSYNC).
At relatively low frequencies (<1 MHz), the duty cycle will be
the primary specification to satisfy; however, at higher frequen-
cies (>2 MHz), the minimum on-time and minimum off-time will
be the primary specifications to satisfy.
Power MOSFETs
The A8651 regulators each include an 80 mΩ, high-side P-chan-
nel MOSFET capable of delivering up to 4.1 A at a 5% duty
cycle. The A8651 regulators also each include a 55 mΩ, low-side
N-channel MOSFET to provide synchronous rectification.
The low-side MOSFET continues to conduct when the induc-
tor current crosses zero to maintain constant conduction mode
(CCM). This helps minimize EMI/EMC for noise sensitive appli-
cations by eliminating the SW high-frequency ringing associated
with discontinuous conduction mode (DCM).
When the A8651 is disabled, via the ENx input or a fault condi-
tion, the A8651 output stage is tri-stated by turning off both the
high-side and low-side MOSFETs.
Pulse-Width Modulation (PWM)
A high-speed PWM comparator, capable of pulse widths less than
105 ns, is included in each A8651 regulator. The inverting input
of the comparator is connected to the output of the error ampli-
fier. The non-inverting input is connected to the sum of the cur-
rent sense signal, the slope compensation, and the PWM Ramp
Offset (VPWMOFFSET ).
At the beginning of each PWM cycle, the CLK signal sets the
PWM flip-flop and the upper MOSFET is turned on. When the
summation of the DC offset, the current sense signal, and the
slope compensation rises above the error amplifier voltage, the
comparator resets the PWM flip-flop and the high-side MOSFET
is turned off. If the output voltage of the error amplifier drops
below the PWM Ramp Offset (VPWMOFFSET
) then a zero percent
PWM duty cycle (pulse skipping) operation is achieved.
Current Sense Amplifier
A high-bandwidth current sense amplifier monitors the current
in the high-side MOSFETs. The PWM comparator, the pulse-
by-pulse current limiter, and the hiccup mode up/down counter
require the current signal.
Soft-Start (Startup) and Inrush Current Con-
trol
Inrush currents to the converter are controlled by the soft-start
function of the A8651. When the A8651 is enabled and all faults
are cleared, the soft-start (SSx) pins source approximately 20 μA
(ISSSU
) and the voltage on the soft-start capacitors (CSSx ) ramp
Figure 2: FSET/SYNC AC-Coupling
22 pF
C
SYNC
R
FSET
FSET/SYNC
SYNCin
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
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upward from 0 V. When the voltage on a soft-start pin exceeds
the Soft-Start Offset Voltage (VSSOFFS
, typically 200 mV mea-
sured at the SSx pin), the output of the error amplifier is released
and shortly thereafter the high-side and low-side MOSFETs
begin switching. As shown in Figure 3, there is a short delay
(tSS(DELAY)
) between when the enable (ENx) pin transitions high
and when the soft-start voltage reaches 200 mV to initiate PWM
switching.
When the A8651 begins PWM switching, the error amplifier
regulates the voltage at the FBx pin to the soft-start (SSx) pin
voltage minus the soft-start offset voltage (VSSOFFS
). When
PWM switching starts, the voltage at the SSx pin rises from
200 to 1000 mV, a difference of 800 mV, the voltage at the FBx
pin rises from 0 to 800 mV, and the regulator output voltage rises
from 0 V to the target setpoint determined by the feedback resis-
tor divider (RFB1-RFB2 or RFB3-RFB4).
When the voltage at the soft-start pin reaches approximately
1000 mV, the error amplifier begin regulating using the A8651
internal reference, 800 mV. The voltage at the soft-start pin con-
tinues to rise to approximately VIN
. The soft-start functionality is
shown in Figure 3.
If the A8651 is disabled or a fault occurs, the internal fault latch is
set and the soft-start (SSx) pin is pulled to ground via approximately
2 kΩ. The A8651 clears the internal fault latch when the voltage at
the SSx pin decays to approximately 120 mV (VSSRESET).
If the A8651 enters hiccup mode, the capacitor (CSSx
) on the soft-
start pin is discharged by a 10 μA current sink (ISSHIC
). There-
fore, the soft-start pin capacitor value (CSSx
) controls the time
between soft-start attempts. Hiccup mode operation is discussed
in more detail in the Output Short Circuit (Hiccup Mode) Protec-
tion section of this datasheet.
When VFBx > 400 mV, the PWM switching frequency is fOSC .
If VFBx < 400 mV, the PWM switching frequency is reduced
to fOSC / 2 to provide the low duty cycles and accurate, stable
control required during initial startup (when VOUT ≈ 0 V). Also,
if VFBx < 400 mV and COMPx = VEAVO(max) , it can be assumed
the regulator output is shorted to ground. In this case, the PWM
switching frequency is further reduced to only fOSC
/ 4 to allow
more off-time between PWM pulses. This is done to prevent
staircasing of the output inductor current, which could result in
damage to the inductor or the A8651. This is especially important
when the input voltage is relatively high and the output of the
regulator is either shorted or soft starting a relatively high output
capacitance.
Pre-Biased Startup
If the output capacitors are pre-biased to some voltage, the A8651
modifies the normal startup routine to prevent discharging the
output capacitors. Normally, the COMPx pin becomes active and
PWM switching starts when the voltage at the soft-start (SSx) pin
reaches 200 mV. With pre-bias at the output, the pre-bias volt-
age is sensed at the FBx pin. The A8651 does not start switching
until the voltage at the soft-start pin increases to approximately
VFBx + 200 mV. At this soft-start pin voltage, the error amplifier
output is released, the voltage at the COMPx pin rises, PWM
Figure 3: Startup to VOUTx = 1.2 V, 2.0 A, with CSS =
22 nF
Figure 4: Startup to VOUTx = 1.2 V, 2.0 A, with VOUT pre-
biased to 0.6 V
1.2 V
1000 mV
Switching starts when
VCOMP > 350 mV
COMP pin released at
VSS = VFB+200 mV
VOUT rises from 0.6 V
200 mV
VOUT
VCOMP
VEN
VSS
1.2 V
1000 mV
Switching starts when
VCOMP > 350 mV
200 mV
VOUT
tSS(DELAY)
tSS
VCOMP
VSS
VEN
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
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switching starts, and VOUT ramps upward, starting from the
pre-bias level. Figure 4 shows startup when the output voltage is
pre-biased to 0.9 V.
Active-Low Power-On Reset (NPORx)
The NPORx pins are open-drain outputs, so an external pull-
up resistor must be connected to each. An internal comparator
monitors the voltage at the FBx pin and controls the open-drain
device at the NPORx pins. NPORx is pulled high by the external
resistor approximately 7.5 ms after VOUTx is within regulation.
The NPORx output is pulled low if:
• VFBx(RISING) < 92% of the reference voltage, or
• VFBx(RISING) > 115% of the reference voltage, or
• EN is low, or
• VIN UVLO occurs, or
• Thermal shutdown (TSD) occurs.
If the A8651 is running and VINx transitions low, then NPORx
transitions low and remains low only as long as the internal cir-
cuitry is able to enhance the open-drain output device. When VIN
fully collapses, the NPORx pin returns to the high-impedance
state. The NPOR comparator incorporates hysteresis to prevent
chattering due to voltage ripple at the FBx pin.
Protection Features
UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout (UVLO) comparator monitors the volt-
age at the VIN pin and keeps the regulator disabled if the voltage
is below the lockout threshold (VINSTART
). The UVLO com-
parator incorporates enough hysteresis (VUVLO(HYS)
) to prevent
on-off cycling of the regulator due to IR drops in the VIN path
during heavy loading or during startup.
THERMAL SHUTDOWN (TSD)
The A8651 protects itself from overheating with an internal ther-
mal monitoring circuit. If the junction temperature exceeds the
upper thermal shutdown threshold (TSD(th)
, nominally 170°C),
the voltages at the soft-start (SSx) and COMPx pins is pulled to
GND and both the high-side and low-side MOSFETs are turned
off. The A8651 stops PWM switching, but it does not enter the
shutdown or sleep mode supply current levels. The A8651 auto-
matically restarts when the junction temperature decreases more
than the thermal shutdown hysteresis (TSD(HYS)
, 20°C (typ) ).
OVERVOLTAGE PROTECTION (OVP)
The A8651 uses the FBx pins to provide a basic level of overvolt-
age protection. An overvoltage condition could occur if the load
decreases very quickly or the COMPx pin or the regulator output
are pulled high by some external voltage. When an overvoltage
condition is detected, (1) NPORx is pulled low, and (2) PWM
switching stops (the SWx node becomes high impedance). The
COMPx and SSx pin voltages are not affected by OVP. If the
regulator output decreases back to the normal operating range,
NPORx transitions high and PWM switching resumes.
PULSE-BY-PULSE OVERCURRENT PROTECTION
(OCP)
The A8651 monitors the current in the high-side P-channel
MOSFET and if the current exceeds the pulse-by-pulse current
overcurrent threshold (ILIM), then the high-side MOSFET is
turned off. Normal PWM operation resumes on the next clock
pulse from the oscillator. The A8651 includes leading edge blank-
ing to prevent false triggering of the pulse-by-pulse current limit
when the high-side MOSFET is turned on. Pulse-by-pulse current
limiting is always active.
A key feature of the A8651 is the ability to adjust the peak switch
current limit. This can be useful when the full current capability
of the regulator is not required for a given application. A smaller
current limit may allow the use of power components with lower
current ratings, thus saving space and reducing cost. A single
resistor between the ISET pin and ground controls the current
limit. Resistor values should be set in the range between 30.9 kΩ
(for the lowest current limit setting) and 41.2 kΩ (for the highest
current limit setting).
The maximum switch current is affected by slope compensation
via the duty cycle. The A8651 is conservatively rated to deliver
2.0 ADC for most applications. However, the exact current the
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
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Figure 5b: Current Limit versus Duty Cycle, with RSET =
30.9 kΩ
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
I
LIM
(A)
Duty Cycle (%)
Min., f
SW
= 2.00 MHz
Typ., f
SW
= 2.00 MHz
Max., f
SW
= 2.00 MHz
Min., f
SW
= 350 kHz
Typ., f
SW
= 350 kHz
Max., f
SW
= 350 kHz
A8651 supports is heavily dependent on duty cycle, ambient
temperature, thermal resistance of the PCB, airflow, component
selection, and nearby heat sources.
The A8651 is designed to deliver more current at lower duty
cycles and slightly less current at higher duty cycles. For exam-
ple, the pulse-by-pulse current limit at 20% duty cycle is typically
3.85 A, but at 80% duty cycle the pulse limit is typically 3.10 A.
Use Table 1a and Figure 5a, and Table 1b and Figure 5b to deter-
mine the real current limit given the duty cycle required for each
application. Take care to do a careful thermal solution or thermal
shutdown can occur.
OUTPUT SHORT-CIRCUIT (HICCUP MODE) PROTEC-
TION
Hiccup mode protects the A8651 when the load is either too high
or when the output of the converter is shorted to ground. When
the voltage at the FBx pin is below the Hiccup Enable Threshold
(VHICEN
, 700 mV (typ)), hiccup mode protection is enabled.
When the voltage at the FBx pin is above the Hiccup Disable
Threshold (VHICDIS, 740 mV (typ)) hiccup mode protection is
disabled.
Hiccup mode overcurrent protection monitors the number of
overcurrent events using an up/down counter. An overcurrent
pulse increments the counter by 1 and a PWM cycle without an
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
ILIM (A)
Duty Cycle (%)
Min., f
SW
= 2.00 MHz
Typ., f
SW
= 2.00 MHz
Max., f
SW
= 2.00 MHz
Min., f
SW
= 350 kHz
Typ., f
SW
= 350 kHz
Max., f
SW
= 350 kHz
Table 1a. Pulse-by-Pulse Current Limit versus
Duty Cycle
RSET = 41.2 kΩ, fSW = 2 MHz
Duty Cycle
(%)
Pulse-by-Pulse Current Limit
(A)
Min. Typ. Max.
5 3.42 4.04 4.65
20 3.17 3.86 4.51
40 2.83 3.61 4.31
60 – 3.37 4.12
80 – 3.12 3.92
90 – 3.00 3.83
Table 1b. Pulse-by-Pulse Current Limit versus
Duty Cycle
RSET = 30.9 kΩ, fSW = 2 MHz
Duty Cycle
(%)
Pulse-by-Pulse Current Limit
(A)
Min. Typ. Max.
5 1.85 2.37 2.87
20 1.69 2.27 2.77
40 1.49 2.13 2.64
60 1.28 2.00 2.52
80 – 1.86 2.39
90 – 1.80 2.32
Figure 5a: Current Limit versus Duty Cycle, with RSET =
41.2 kΩ
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
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A8651
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overcurrent pulse decrements the counter by 1. If more than 7
consecutive overcurrents are detected, then the Hiccup latch is
set and PWM switching is stopped. The Hiccup signal causes
the COMPx pin to be pulled low with a relatively low resistance
(1.5 kΩ). Hiccup mode also enables a current sink connected to
the soft-start (SSx) pin (ISSHIC,10 µA), so when hiccup initially
occurs, the voltage at the soft-start pin ramps downward. Hiccup
mode operation is shown in Figure 6.
When the voltage at the soft-start pin decays to a low level
(VSSRESET
, 120 mV (typ) ), the hiccup latch is cleared and the
10 µA soft-start pin current sink is turned off. The soft-start pin
resumes charging the soft-start capacitor with 20 µA, and the
voltage at the soft-start pin ramps upward.
When the voltage at the soft-start pin exceeds the soft-start offset
voltage (VSSOFFS
, 200 mV (typ)), the low-resistance pull-down
at the COMPx pin is turned off. The error amplifier forces the
voltage at the COMPx pin to ramp up quickly, and PWM switch-
ing begins. If the short-circuit at the converter output remains,
another hiccup cycle occurs. Hiccup cycles repeat until the short-
circuit is removed or the converter is disabled. If the short-circuit
is removed, the A8651 soft-starts normally and the output voltage
ramps to the operating level, as shown in Figure 6.
Short removed
≈ 4.1 A
200 mV
120 mV
VOUT
VCOMP
VSS
IL
Figure 6: Hiccup Mode Operation and Recovery
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
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Table 2: Summary of A8651 Fault Modes and Operation
Fault Mode VSS VCOMP High-Side Switch Low-Side Switch NPOR Reset Condition
Output hard short-
to-ground (VOUT
and VFB = 0 V)
Hiccup after VCOMP
≈ 1.25 V and
7 OC faults
Clamped to
≈1.25 V for ILIM
,
then pulled low
during hiccup
Controlled by
VCOMP
, fOSC
/ 2 if
0 < VFB < 400 mV,
fOSC / 4 if COMP
≈1.25 V and ILIM
Active during tOFF
,
off during hiccup Depends on VOUT
Automatic, remove
the short
Output overcurrent
and VFB < VHICDIS
Hiccup after VCOMP
≈ 1.25 V and
7 OC faults
Clamped to
≈1.25 V for ILIM
,
then pulled low
during hiccup
Controlled by
VCOMP
, fOSC
/ 2 if
0 < VFB
< 400 mV, fOSC / 4
if VCOMP ≈1.25 V
and ILIM
Active during tOFF,
off during hiccup Depends on VOUT
Automatic,
decrease the load
current
SW hard short to
ground
Ramps to VIN
,
hiccup may occur
when the short is
removed
Clamped to
≈1.25 V, pulled low
if hiccup occurs
Controlled by
VCOMP
, turn off
if VSW ≈ 0 V and
blanking time
expires, fOSC / 4
Active during tOFF
,
off if hiccup occurs
when the short is
removed
Depends on VOUT
Automatic, remove
the short
SW soft short to
ground
Hiccup after VCOMP
≈1.25 V and
7 OC faults
Clamped to
≈1.25 V for ILIM,
then pulled low
during hiccup
Controlled by
VCOMP
, fOSC / 2 if 0
< VFB < 400 mV,
fOSC / 4 if VCOMP
≈1.25 V and ILIM
Active during tOFF
,
off during hiccup Depends on VOUT
Automatic, remove
the short
FB pin open (VFB
floats high due
to negative bias
current)
Not affected
Transitions low via
loop response as
VFB floats high
Off, fOSC / 2 if 0 <
VFB < 400 mV, fOSC
if 400 mV < VFB
Off, disabled if
VCOMP < 200 mV
Pulled low
whenVFB > 115%
× VREF
Automatic, connect
the FB pin
Output overvoltage
(VFB > 115% ×
VREF)
Not affected
Transitions low
via loop response
because VFB >
VREF
Off, fOSC
/ 2 if 0 <
VFB < 400 mV, fOSC
if 400 mV < VFB
Off, disabled if
VCOMP< 200 mV
Pulled low when
VFB > 115% × VREF
Automatic, VFB
returns to the
normal range
Output
undervoltage Not affected Transitions high via
loop response
Controlled by
VCOMP
, fOSC / 2 if
0 < VFB < 400 mV,
fOSC if 400 mV
< VFB
Active during tOFF
Pulled low when
VFB < 92% × VREF
Automatic, VFB
returns to the
normal range
Thermal shutdown
(TSD)
Pulled low and
latched until
VSS < VSSRESET
Pulled low and
latched until VSS >
VSS(RELEASE)
Off Off Pulled low
Automatic, after
the junction cools
down
Low Input Voltage, Adjustable Frequency Dual Synchronous
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This section shows how to design and select external component
values. For simplicity, the naming convention used here refers
only to regulator 1, but the same design methods can be used for
regulator 2.
Setting the Output Voltage (VOUT1
, RFBx )
The output voltage of the A8651 is determined by connecting a
resistor divider from the output node (VOUT1) to the FB1 pin as
shown in Figure 7. There are trade-offs when choosing the value
of the feedback resistors. If the series combination (RFB1+RFB2 )
is relatively low, then the light load efficiency of the regulator is
reduced. So, to maximize the efficiency it is best to choose high
values of resistors. On the other hand, if the parallel combination
(RFB1 // RFB2 ) is too high, then the regulator may be susceptible
to noise coupling into the FB1 pin.
In general, the feedback resistors must satisfy the ratio shown in
equation 1 to produce an output voltage, VOUT1:
=– 1
0.8 (V)
VOUT1
RFB2
RFB1 (1)
Table 3 shows the most common output voltages and recom-
mended feedback resistors, assuming less than 0.2% efficiency
loss at a light load of 100 mA and a parallel combination of 4 kΩ
presented to the FB1 pin. For optimal system accuracy, it is rec-
ommended that the feedback resistors have ≤1% tolerances.
PWM Switching Frequency (RFSET)
The PWM switching frequency is set by connecting a resistor
from the FSET/SYNC pin to ground. Figure 8 is a graph showing
the relationship between the typical switching frequency (y-axis)
and the FSET resistor (x-axis).
DESIGN AND COMPONENT SELECTION
Figure 7: Connection for the Feedback Divider
RFB1
RFB2
V
OUT1
FB1 PIN
Table 3. Recommended Feedback Resistors
VOUT1
(V)
RFB1
(VOUT1 to FB1 pin)
(kΩ)
RFB2
(FB1 pin to GND)
(kΩ)
1.2 6.04 12.1
1.5 7.50 8.45
1.8 9.09 7.15
2.5 12.4 5.76
3.3 16.5 5.23
Figure 8. PWM Switching Frequency versus RFSET
2250
2000
1750
1500
1250
1000
750
500
250
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
R(kΩ)
FSET
Oscillator Frequency (kHz)
Low Input Voltage, Adjustable Frequency Dual Synchronous
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To set a specific oscillator frequency (fosc
), the RFSET resistor can
be calculated as follows:
fOSC
15456
R=
FSET
–1.186
()
(2)
where fosc is in kHz and RFSET is in kΩ.
When the PWM switching frequency is chosen, the designer
should be aware of the minimum controllable on-time (tON(MIN)
)
of the A8651. If the application system required on-time is less
than the A8651 minimum controllable on-time, then switch node
jitter occurs and the output voltage has increased ripple or oscil-
lations.
The PWM switching frequency should be calculated as follows:
=tON(MIN)×VIN1(MAX)
VOUT1
fSWMAX (3)
where VOUT1 is the output voltage, tON(MIN) is the minimum
controllable on-time of the A8651 (worst case is 105 ns), and
VIN1(MAX) is the maximum required operational input voltage to
the A8651 (not the peak surge voltage).
If the A8651 synchronization function is employed, then the base
switching frequency should be chosen such that jitter does not
result at the maximum synchronized switching frequency accord-
ing to equation 3: 1.5 × fSW < fSWMAX calculated by equation 3.
Output Inductor (LO
)
For a peak current mode regulator it is common knowledge
that, without adequate slope compensation, the system becomes
unstable when the duty cycle is near or above 50%. However, the
slope compensation in the A8651 is a fixed value (SE
). Therefore,
it is important to calculate an inductor value such that the falling
slope of the inductor current (SF) works well with the A8651
slope compensation.
Equations 4a and 4b can be used to calculate a range of values for
the output inductor based on the well known approach of provid-
ing slope compensation that matches 50% to 100% of the down
slope of the inductor current.
≤≤ LO1
2 × SE
VOUT1 VOUT1
SE
(4a)
where LO is in µH and the slope compensation (SE ) is a function
of switching frequency, as follows:
SE = (0.054 × RSET – 0.96) × fSW (4b)
where RSET is in kΩ, fSW is in MHz, and the calculated SE is in
A/µs.
Another limitation is shown in equation 5. This is based on a
formula to calculate the amount of slope compensation required
to critically damp the double poles at half the PWM switching
frequency (this approach includes the duty cycle (D), which
should be calculated at the minimum input voltage to insure
optimal stability):
≥
LO1 1 – VIN1(MIN)
VOUT1
VOUT1
SE
0.18 ×
(5)
To avoid dropout (saturation of the buck regulator), VIN1(MIN)
must be approximately 0.75 to 1.0 V above VOUT1 when calculat-
ing the inductor value with equation 5.
If equations 4a or 5 yield an inductor value that is not a standard
value then the next closest available value should be used. The
final inductor value should allow for 10% to 20% of initial toler-
ance and 10% to 20% of inductor saturation.
The saturation current of the inductor should be higher than the
peak current capability of the A8651. Ideally, for output short
circuit conditions, the inductor should not saturate given the high-
est pulse-by-pulse current limit at minimum duty cycle (ILIM(5%) );
4.7 A. This may be too costly. At the very least, the inductor
should not saturate given the peak operating current according to
the following equation:
=
IPEAK 4.1 – SE × VOUT1
1.15 × fSW × VIN1(MAX)
(6)
where VIN1(MAX) is the maximum continuous input voltage, such
as 5.5 V.
Starting with equation 6 and subtracting half of the inductor
ripple current provides us with an interesting equation to predict
the typical DC load capability of the regulator at a given duty
cycle (D = VOUT1 / VIN1):
≤
IOUT1(DC) 4.1 – –
SE × D VOUT1 × (1 – D
)
2 × fSW × LO1
fSW
(7)
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After an inductor is chosen it should be tested during output
short-circuit conditions. The inductor current should be moni-
tored using a current probe. A good design should ensure the
inductor or the regulator are not damaged when the output is
shorted to ground at maximum input voltage and the highest
expected ambient temperature.
Output Capacitors
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage and they store energy to help
maintain voltage regulation during a load transient. The voltage
rating of the output capacitors must support the output voltage
with sufficient design margin.
The output voltage ripple (ΔVOUT1 ) is a function of the output
capacitors parameters: COUT1, ESRCOUT1
, and ESLCOUT1
:
=
∆VOUT1 ∆IL1 × ESRCOUT1
∆IL1
× ESLCOUT1
VIN1 – VOUT1
LO1
8 fSWCOUT1
+
+
(8)
The type of output capacitors determines which terms of equa-
tion 8 are dominant. For ceramic output capacitors the ESRCOUT1
and ESLCOUT1 are virtually zero, so the output voltage ripple will
be dominated by the third term of equation 8:
≤
∆VOUT1
∆IL1
8 fSWCOUT1
(9)
To reduce the voltage ripple of a design using ceramic output
capacitors simply: increase the total capacitance, reduce the
inductor current ripple (that is, increase the inductor value), or
increase the switching frequency.
For electrolytic output capacitors the value of capacitance will be
relatively high, so the third term in equation 8 will be very small
and the output voltage ripple will be determined primarily by the
first two terms of equation 8:
=
∆VOUT1 ∆IL1 × ESRCOUT1 × ESLCOUT1
VIN1
LO1
+
(10)
To reduce the voltage ripple of a design using electrolytic out-
put capacitors simply: decrease the equivalent ESRCOUT1 and
ESLCOUT1 by using a high(er) quality capacitor, or add more
capacitors in parallel, or reduce the inductor current ripple (that
is, increase the inductor value).
The ESR of some electrolytic capacitors can be quite high so
Allegro recommends choosing a quality capacitor for which the
ESR or the total impedance is clearly documented in the capaci-
tor datasheet. Also, the ESR of electrolytic capacitors usually
increases significantly at cold ambients, as much as 10 ×, which
increases the output voltage ripple and, in most cases, reduces the
stability of the system.
The transient response of the regulator depends on the quantity
and type of output capacitors. In general, minimizing the ESR of
the output capacitance will result in a better transient response.
The ESR can be minimized by simply adding more capacitors
in parallel or by using higher quality capacitors. At the instant
of a fast load transient (di/dt), the output voltage changes by the
amount:
=
∆VOUT1 ∆IL1 × ESRCOUT1 × ESLCOUT1
di
dt
+
(11)
After the load transient occurs, the output voltage will deviate
from its nominal value for a short time. The length of this time
depends on the system bandwidth, the output inductor value, and
output capacitance. Eventually, the error amplifier brings the
output voltage back to its nominal value.
The speed at which the error amplifier brings the output voltage
back to the setpoint depends mainly on the closed-loop band-
width of the system. A higher bandwidth usually results in a
shorter time to return to the nominal voltage. However, a higher
bandwidth system may be more difficult to obtain acceptable gain
and phase margins. Selection of the compensation components
(RZ
, CZ , and CP
) are discussed in more detail in the Compensa-
tion Components section of this datasheet.
Input Capacitors
Three factors should be considered when choosing the input
capacitors. First, the capacitors must be chosen to support the
maximum expected input surge voltage with adequate design
margin. Second, the capacitor rms current rating must be higher
than the expected rms input current to the regulator. Third, the
capacitors must have enough capacitance and a low enough ESR
to limit the input voltage dV/dt to something much less than the
hysteresis of the UVLO circuitry (nominally 200 mV for the
A8651) at maximum loading and minimum input voltage.
Low Input Voltage, Adjustable Frequency Dual Synchronous
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The input capacitor(s) must limit the voltage deviations at the
VIN1 pin to something significantly less than the device UVLO
hysteresis during maximum load and minimum input voltage.
The following equation allows us to calculate the minimum input
capacitance:
≥
CIN1
IOUT1
∆VIN1(MIN)
fSW
0.85
D×
× ×
× (1– D)(12)
where ΔVIN1(MIN) is chosen to be much less than the hysteresis
of the VIN1 UVLO comparator (ΔVIN1(MIN) ≤ 100 mV is recom-
mended), and fSW is the nominal PWM frequency.
The D × (1–D) term in equation 12 has an absolute maximum
value of 0.25 at 50% duty cycle. So, for example, a very con-
servative design based on IOUT1 = 2.0 A, fSW = 85% of 2 MHz,
D × (1–D) = 0.25, and ΔVIN1 = 100 mV yields:
≥=
×
×
CIN 1.7 (MHz) 100 (mV) 2.9 µF
2.0 (A) 0.25
The input capacitors must deliver an rms current (IRMS) accord-
ing to the following formula:
=
IRMS IOUT1 D × (
1 – D)
(13)
where the duty cycle (D) is defined as:
D = VOUT1 / VIN1 (14)
Figure 9 shows the normalized input capacitor rms current versus
duty cycle. To use this graph, simply find the operational duty
cycle (D) on the x-axis and determine the input/output current
multiplier on the y-axis. For example, at a 20% duty cycle, the
input/output current multiplier is 0.40. Therefore, if the regula-
tor is delivering 2.0 A of steady-state load current, the input
capacitor(s) must support 0.40 × 2.0 A or 0.8 Arms.
A good design should consider the DC-bias effect on a ceramic
capacitor: as the applied voltage approaches the rated value, the
capacitance value decreases. This effect is very pronounced with
the Y5V and Z5U temperature characteristic devices (as much as
90% reduction), so these types should be avoided. The X5R and
X7R type capacitors should be the primary choices due to their
stability versus both DC bias and temperature.
For all ceramic capacitors, the DC-bias effect is even more pro-
nounced on smaller sizes of device case, so a good design uses
the largest affordable case size (such as 1206 or 1210). Also, it is
advisable to select input capacitors with plenty of design margin
in the voltage rating to accommodate the worst case transient
input voltage.
Soft-Start and Hiccup Mode Timing (CSS1)
The soft-start time of the A8651 is determined by the value of the
capacitance at the soft start pin, CSS1. When the A8651 is enabled
the voltage at the soft start pin (SS1) starts from 0 V and is
charged by the soft-start current, ISSSU1
. However, PWM switch-
ing does not begin instantly because the voltage at the soft-start
pin must rise above 200 mV. The soft-start delay (tSS(DELAY)) can
be calculated using the following equation:
=×
tSS(DELAY) CSS1 ISSSU
200 (mV) (15)
If the A8651 is starting into a very heavy load, a very fast soft-
start time may cause the regulator to exceed the cycle-by-cycle
overcurrent threshold. This occurs because the total of the full
load current, the inductor ripple current, and the additional cur-
rent required to charge the output capacitors:
Figure 9: Normalized Input Capacitor Ripple versus
Duty Cycle
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0 10 20 30 40 50 60 70 80 90 100
Duty Cycle, D (%)
I
RMS
/ I
OUT1
Low Input Voltage, Adjustable Frequency Dual Synchronous
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ICOUT1 = COUT1 × VOUT1 / tSS (16)
is higher than the cycle-by-cycle current threshold, as shown in
Figure 10. This phenomena is more pronounced when using high
value electrolytic type output capacitors. To avoid prematurely
triggering hiccup mode, the soft-start capacitor, CSS1 , should be
calculated according to:
≥× ×
CSS1
COUT1
VOUT1
ISSSU
×
0.8 (V) ICOUT1
(17)
where VOUT1 is the output voltage, COUT1 is the output capaci-
tance, ICOUT1 is the amount of current allowed to charge the
output capacitance during soft-start (recommend 0.1 A < ICOUT1
< 0.3 A). Higher values of ICOUT1 result in faster soft-start times.
However, lower values of ICOUT1 ensure that hiccup mode is not
inappropriately triggered. Allegro recommends starting the design
with an ICOUT1 of 0.1 A and increasing it only if the soft-start
time is too slow. If a non-standard capacitor value for CSS1 is
calculated, the next larger value should be used.
The output voltage ramp time, tSS
, can be calculated by using
either of the following methods:
=
=
×
tSS
tSS
COUT1
CSS1
ISSSU
VOUT1
×
0.8 (V)
or ICOUT1
(18)
(19)
When the A8651 is in hiccup mode, the soft-start capacitor
is used as a timing capacitor and sets the hiccup period. The
soft-start pin charges the soft-start capacitor with ISSSU during
a startup attempt, and discharges the same capacitor with ISSHIC
between startup attempts. Because the ratio ISSSU / ISSHIC is
approximately 2:1, the time between hiccups is about two times
as long as the startup time. Therefore, the effective duty-cycle of
the A8651 is very low and the junction temperature is kept low.
Compensation Components (RZ, CZ, CP)
To compensate the system, it is important to understand where
the buck power stage, load resistance, and output capacitance
form their poles and zeros in frequency. Also, it is important
to understand that the (Type II) compensated error amplifier
introduces a zero and two more poles, and where these should be
placed to maximize system stability, provide a high bandwidth,
and optimize the transient response.
First, consider the power stage of the A8651, the output capaci-
tors, and the load resistance. This circuitry is commonly referred
as the control-to-output transfer function. The low frequency gain
of this circuitry depends on the COMP1 to SW1 current gain
( gmPOWER
), and the value of the load resistor (RL1
). The DC gain
(GCO(0HZ)
) of the control-to-output is:
GCO(0Hz) = gmPOWER × RL1 (20)
The control-to-output transfer function has a pole (fP1), formed
by the output capacitance (COUT1) and load resistance (RL1
),
located at:
=
fP1 COUT1
RL1
× ×
2�
1(21)
The control-to-output transfer function also has a zero (fZ1)
formed by the output capacitance (COUT1) and its associated
ESR:
=
fZ1 COUT1
ESRCOUT1
× ×
2�
1
(22)
For a design with very low-ESR type output capacitors (such as
ceramic capacitors), the ESR zero, fZ1, is usually at a very high
frequency so it can be ignored. On the other hand, if the ESR zero
falls below or near the 0 dB crossover frequency of the system
(as happens with electrolytic output capacitors), then it should
be cancelled by the pole formed by the CP capacitor and the RZ
resistor (discussed and identified later as fP3
).
A Bode plot of the control-to-output transfer function for the
schematic shown in figure 15, with VOUT1 = 1.2 V, IOUT1 = 1.5 A,
Figure 10. Output Current (ICOUT1) During Startup
Output
capacitor
current, I
COUT1
}
I
LIM
I
LOAD1
t
SS
Low Input Voltage, Adjustable Frequency Dual Synchronous
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and RL1 = 0.8 Ω, is shown in Figure 11. The pole at fP1 can easily
be seen at 8.8 kHz, while the ESR zero, fZ1
, occurs at a very high
frequency, 4 MHz (this is typical for a design using ceramic out-
put capacitors). Note, there is more than 90° of total phase shift
because of the double-pole at half the switching frequency.
Next, consider the feedback resistor divider, (RFB1 and RFB2), the
error amplifier (gm), and its compensation network RZ-CZ-CP
.
It greatly simplifies the transfer function derivation if RO >> RZ,
and CZ >> CP . In most cases, RO > 2 MΩ, 1 kΩ < RZ <100 kΩ,
220 pF < CZ < 47 nF, and CP < 50 pF, so the following equations
are very accurate.
The low frequency gain of the control section (GC(0Hz)
) is formed
by the feedback resistor divider and the error amplifier. It can be
calculated as:
=× ×
GC(0Hz)
RFB2 RO
RFB1+RFB2
gm
=× ×
VFB1 RO
VOUT1
gm
=×
VFB1
VOUT1
AVOL (23)
where
VOUT is the output voltage,
VFB is the reference voltage (0.8 V),
gm is the error amplifier transconductance (750 µA/V ), and
RO is the error amplifier output impedance (A
VOL/gm
).
The transfer function of the Type-II compensated error amplifier
has a (very) low frequency pole (fP2
) dominated by the output
error amplifier output impedance (RO) and the CZ compensation
capacitor:
=
fP2 CZ
RO
× ×
2�
1(24)
The transfer function of the Type-II compensated error amplifier
also has frequency zero (fZ2) dominated by the RZ resistor and
the CZ capacitor:
=
fZ2 CZ
RZ
× ×
2�
1(25)
Lastly, the transfer function of the Type-II compensated error
amplifier has a (very) high frequency pole (fP3) dominated by the
RZ resistor and the CP capacitor:
=
fP3 CP
RZ
× ×
2�
1(26)
A Bode plot of the error amplifier and its compensation network
is shown in Figure 12, where fP2, fP3, and fZ2 are indicated on the
Gain plot. Notice that the zero (fZ2 at 16 kHz) has been placed so
that it is just above the pole at fP1 previously shown at 8.8 kHz
in the control-to-output Bode plot (Figure 11). Placing fZ2 just
above fP1 results in excellent phase margin, but relatively slow
transient recovery time, as we will see later.
Finally, consider the combined Bode plot of both the control-to-
output and the compensated error amplifier (Figure 13). Careful
examination of this plot shows that the magnitude and phase
of the entire system (red curve) are simply the sum of the error
Figure 11: Control-to-Output Bode Plot
GCO(0Hz) = 12 dB fP1 = 8.8 kHz
fz1 = 4 MHz
0
-180
-90
180
90
-80
0
-40
40
Gain (dB)Phase (°)
Frequency (Hz)
10 100 10310×103100×103106
1.06
Double Pole at
1 MHz
Figure 12: Type-II Compensated Error Amplier Bode
Plot
GCO(0Hz) = 58 dB
fP2 = 45 Hz
fP2 ≈ 1.1 MHz
fz2 = 16 kHz
90
0
-45
180
135
-40
40
0
80
Gain (dB)Phase (°)
Frequency (Hz)
10 100 10310×103100×103106
1.06
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amplifier response (blue curve) and the control to output response
(green curve). As shown in Figure 13, the bandwidth of this sys-
tem (fc
) is 72 kHz, the phase margin is 73 degrees, and the gain
margin is 27 dB.
A Generalized Tuning Procedure
This section presents a methodology to systematically apply
design considerations provided above.
1. Choose the system bandwidth (fC
). This is the frequency at
which the magnitude of the gain crosses 0 dB. Recommended
values for fC, based on the PWM switching frequency, are
in the range fSW
/ 20 < fC < fSW / 7.5. A higher value of fC
generally provides a better transient response, while a lower
value of fC generally makes it easier to obtain higher gain and
phase margins.
2. Calculate the RZ resistor value. This sets the system band-
width (fC):
=
RZfCg
mPOWER
g
m
COUT1
VOUT1
VFB1
× ×
×
×
2�(27)
3. Determine the frequency of the pole (fP1). This pole is formed
by COUT and RL. Use equation 21 (repeated here):
=
fP1 COUT1
RL1
× ×
2�
1
4. Calculate a range of values for the CZ capacitor. Use the fol-
lowing:
< <
CZ
fC
RZ
× ×
2�
4
fP1
RZ
× × ×
2�1.5
1
(28)
To maximize system stability (that is, to have the greatest gain
margin), use a higher value of CZ . To optimize transient recovery
time, although at the expense of some phase margin, use a lower
value of CZ .
5. Calculate the frequency of the ESR zero (fZ1
) formed by the
output capacitor(s) by using equation 22 (repeated here):
=
fZ1 COUT1
ESRCOUT1
× ×
2�
1
If fZ1 is at least 1 decade higher than the target crossover fre-
quency (fC
), then fZ1 can be ignored. This is usually the case for
a design using ceramic output capacitors. Use equation 26 to
calculate the value of CP by setting fP3 to either 5 × fC or fSW
/ 2,
whichever is higher.
Alternatively, if fZ1 is near or below the target crossover fre-
quency (fC
), then use equation 26 to calculate the value of CP by
setting fP3 equal to fZ1. This is usually the case for a design using
high ESR electrolytic output capacitors.
Figure 13: Bode Plot of the Complete System
(red curve)
Figure 14: Transient Recovery Comparison for fZ2 at
16 kHz/69° and 50 kHz/51°
fC= 72 kHz GM = 27 dB
PM = 73 deg
0
-180
-90
180
90
-100
0
100
Gain (dB)Phase (°)
Frequency (Hz)
10 100 10310×103100×103106
1.06
(V)
(µs)
240 250 260 270 280 290 300 310 320 330
1.840
1.820
1.800
1.780
1.760
1.740
1.725
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
27
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 15: Typical Application Circuit for VIN = 5 V at TA = 125°C: VOUT 3.3 V / 1.5 A and 1.2 V / 1.5 A at 2 MHz
CSYNC are only required if synchronizing to an external clock
CIN2
0.1uF
0805
CIN3
10nF
0603
U1
A8651
SS1
19
EN1
3
FSET/SYNC
5
VIN1
20
GND
16
NPOR1 15
FB1 18
COMP1
17
PGND1
2
SW1 1
VIN2
11
PGND2
9
EN2
8
SS2
12 COMP2
13
SW2 10
FB2 14
NPOR2 6
ISET1
4
ISET2
7
CO2
0.1uF
0805
CO3
10nF
0603
Vin
Csync22pF
3.3V / 1.5A
RFB2
5.23K
RFB1
16.5K
CSS1
22nF
CIN1
3.3uF
1206
RSET1
34.8K
EN1
NPOR1
RZ1
4.99K
CP1
68pF
CZ1
1.8nF
LO1
3.3uH
1 2
RPU1
10K
CO1
10uF
1206
3.3V
SYNCin
CO9
10nF
0603
CIN5
0.1uF
0805
CIN6
10nF
0603
CSS2
22nF
CIN4
3.3uF
1206
RSET2
34.8K
EN2
RZ2
5.62K
CP2
68pF
CZ2
1.8nF
RFSET
11.3K
CO6
10uF
1206
CO7
10uF
1206
CO8
0.1uF
0805
1.2V / 1.5A
RFB4
12.1K
RFB3
6.04K
NPOR2
LO2
1.5uH
1 2
RPU2
10K
3.3V
CO5
10uF
1206
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
28
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
POWER DISSIPATION AND THERMAL CALCULATIONS
The power dissipated in the A8651 is the sum of the power dis-
sipated from the VIN supply current (PIN
) and the power dis-
sipated by the two regulators. The regulator power dissipation
is composed of: the power dissipated due to the switching of the
high-side power MOSFET (PSW(HS)
), the power dissipated due
to the rms current being conducted by the high-side and low-side
MOSFETs (PCOND(HS) and PCOND(LS)
), and the power dissipated
by the low-side body diode (PNO ) during the non-overlap time.
The power dissipated from the VIN supply current can be calcu-
lated using the following equation:
PIN = VIN1 × IQ + (VIN1 + VIN2 ) × (QG(HS) + QG(LS) ) × fSW
(29)
where
VINx are the input voltages,
IQ is the input quiescent current drawn by the device (nominally
2 mA),
QG(HS) and QG(LS) are the internal high- and low-side
MOSFET gate charges (approximately 3.3 nC and 1.4 nC, respec-
tively), and
fSW is the PWM switching frequency.
Note: The calculation after this point refers only to regulator 1.
The power dissipated by the internal high-side MOSFET during
PWM switching can be calculated using the following equation:
=
PSW1
VIN IOUT fSW
(tr + tf )
× × ×
2
(30)
where
VIN is the input voltage,
IOUT is the output current,
fSW is the PWM switching frequency, and
tr and tf are the rise and fall times measured at the SW node.
The exact rise and fall times at the SW node depend on the
external components and PCB layout so each design should be
measured at full load. Approximate values for both tr and tf range
from 10 to 15 ns. The fall time is usually about 50% faster than
the rise time.
The conduction losses dissipated by the high-side MOSFET
while it is conducting can be calculated using the following equa-
tion:
=
PCOND(HS) Irms(FET) RDS(on)HS
VOUT
VIN
×
×+12
2
∆IL
2
IOUT
2
=RDS(on)HS
×(31)
where
IOUT is the regulator output current,
ΔIL is the peak-to-peak inductor ripple current, and
RDS(on)1 is the on-resistance of the high-side MOSFET.
The conduction losses dissipated by the low-side MOSFET can
be calculated as:
=
PCOND2 Irms(FET) RDS(on)2
VOUT
VIN
×
×+12
2
∆IL
2
IOUT
2
=RDS(on)2
1 – ×(32)
where
IOUT is the regulator output current,
ΔIL is the peak-to-peak inductor ripple current, and
RDS(on)1 is the on-resistance of the high-side MOSFET.
The RDS(on)of the MOSFETs has some initial tolerance plus an
increase from self-heating and elevated ambient temperatures.
A conservative design should accommodate an RDS(on) with
at least a 15% initial tolerance plus 0.39%/°C increase due to
temperature.
The power dissipated by the low-side MOSFETs body diode dur-
ing the non-overlap time can be calculated as:
PNO = VSD × IOUT × 2 × tNO × fSW (33)
where
The deadtime is the same for the rising and falling edges of SW,
VSD is the source-to-drain voltage of the low-side MOSFET (typ-
ically 0.60 V), and tNO is the non-overlap time (typically 15 ns),
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
29
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Finally, the total power dissipated by the device (PTOTAL) is the
sum of the previous equations:
PTOTAL = PIN + PREGULATOR1 + PREGULATOR2 (35)
where
PREGULATOR1 = PSW + PCOND(HS) + PCOND(LS) + PNO (36)
The average junction temperature can be calculated with the fol-
lowing equation:
TJ = PTOTAL × RθJA + TA (37)
where
PTOTAL is the total power dissipated as described in equation 35,
RθJA is the junction-to-ambient thermal resistance (48°C/W on a
4-layer PCB), and
TA is the ambient temperature.
The maximum junction temperature is dependent on how effi-
ciently heat can be transferred from the PCB to ambient air. It is
critical that the thermal pad on the bottom of the IC should be
connected to a at least one ground plane using multiple vias.
As with any regulator, there are limits to the amount of heat that
can be dissipated before risking thermal shutdown. There are
trade-offs among: ambient operating temperature, input voltage,
output voltage, output current, switching frequency, PCB
thermal resistance, airflow, and other nearby heat sources.
Even a small amount of airflow will reduce the junction tempera-
ture considerably.
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
30
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
PCB COMPONENT PLACEMENT AND ROUTING
A good PCB layout is critical if the A8651 is to provide clean,
stable output voltages. Follow these guidelines to ensure a good
PCB layout. Figure 16 shows a typical buck converter schematic
with the critical power paths/loops. Figure 17 shows an example
PCB component placement and routing with the same critical
power paths/loops from the schematic.
1. Place the ceramic input capacitors as close as possible to the
VINx pins and ground the capacitors at the PGNDx pins. The
ceramic input capacitors and the A8651 must be on the same
layer. Connect the input capacitors, the VINx pins, and the
PGNDx pins with a wide trace. This critical loop is shown as
a red trace in Figures 16 and 17.
2. Place the output inductor (LOx
) as close as possible to the
SWx pins. The output inductor and the A8651 must be on the
same layer. Connect the SWx pins to the output inductor with
a relatively wide trace or polygon. For EMI/EMC reasons, it
is best to minimize the area of this trace/polygon. This critical
trace is shown as a green trace in Figure 16. Also, keep low-
level analog signals (like FB and COMP) away from the SW
metal.
3. Place the output capacitors relatively close to the output
inductor and the A8651. Ideally, the output capacitors, output
inductor and the A8651 should be on the same layer. Connect
the output inductor and the output capacitors with a fairly
wide trace. The output capacitors must use a ground plane to
make a very low inductance connection back to the PGND
pin. These critical connections are shown in blue in Figures
16 and 17.
4. Place the feedback resistor dividers (RFB1-RFB2
) very close
to the FB pin. Orient RFB2 such that its ground is as close as
possible to the A8651.
5. Place the compensation components (RZ, CZ, and CP) as
close as possible to the COMP pin. Orient CZ and CP such
that their ground connections are as close as possible to the
A8651.
6. Place and ground the FSET resistor as close as possible to the
FSET pin.
7. The output voltage sense trace (from VOUT to RFB1) should
be connected as close as possible to the load to obtain the
best load regulation.
8. The thermal pad under the IC should be connected a ground
plane (preferably on the bottom layer) with as many vias as
possible. Allegro recommends vias with approximately a 10-
15 mil hole and a 5-7 mil ring.
9. Place the soft-start capacitor (CSS) as close as possible to the
SS pin. Place a via to the GND plane as close as possible to
this component.
10. When connecting the input and output ceramic capacitors to
a power or ground plane, use multiple vias and place the vias
as close as possible to the component’s pads. Do not use ther-
mal reliefs (spokes) around the pads for the input and output
ceramic capacitors.
11. EMI/EMC issues are always a concern. Allegro recommends
having locations for an RC snubber from SW to ground. The
snubber components can be placed on the back of the PCB
and populated only if necessary. The resister should be 0805
or 1206 size.
12. Allegro strongly recommends the use of current steering (a
cut in the ground plane) to prevent current from SW1 from
disturbing SW2 and vice versa. Notice the horizontal cut in
the ground plane as shown in Figure 17.
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
31
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 16: Typical Synchronous Buck Converter with Critical Paths/Loops Shown
Figure 17: Example PCB Component Placement and Routing
SS
FSET
COMP
SW
VIN
PGND
FB
Lo
CIN
Cout
LOAD
SINGLE POINT GROUND
Could be the therm al/ground pad under the IC
A8651 SW1
GND
Css RFSET RZ
CP
CZ
RFB2
RFB1
Notice the cut in the
GND plane
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
32
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 16: Current Derating Curve versus Output Voltages, Switching Frequency, and Ambient Temperature
0
0.5
1
1.5
2
2.5
75 80 85 90 95 100105110115120125
Current Rang (A)
Ambient Temperature (°C)
3.3Vo
1.5Vo
0
0.5
1
1.5
2
2.5
75 80 85 90 95 100105110115120125
Current Rang (A)
Ambient Temperature (°C)
3.3Vo
1.5Vo
0
0.5
1
1.5
2
2.5
75 80 85 90 95 100105110115120125
Current Rang (A)
Ambient Temperature (°C)
3.3Vo
1.5Vo
0
0.5
1
1.5
2
2.5
75 80 85 90 95 100105110115120125
Current Rang (A)
Ambient Temperature (°C)
3.3Vo
1.5Vo
VIN
= 5 V, fSW V zHk004 = IN
= 5 V, f SW = 2 MHz
VIN = 5 V, fSW V zHk004 = IN = 5 V, fSW
= 2 MHz
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
33
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 17: Package LP, 20-Pin TSSOP with Exposed Thermal Pad
B
1
A
B
CExposed thermal pad (bottom surface)
For Reference Only – Not for Tooling Use
(Reference MO-153 ACT)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
1.20 MAX
0.15
0.00
0.30
0.19
0.20
0.09
8º
0º
0.60 ±0.15 1.00 REF
C
SEATING
PLANE
C0.10
20X
0.65 BSC
0.25 BSC
21
20
6.50 ±0.10
4.40 ±0.103.00 3.00
4.20
4.20
6.40 ±0.20
GAUGE PLANE
SEATING PLANE
0.45
1.70
20
21
B
6.10
0.65
C
PCB Layout Reference View
Terminal #1 mark area
Reference land pattern layout (reference IPC7351 SOP65P640X110-21M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
YYWW
NNNNNNN
LLLLLLL
Standard Branding Reference View
= Device part number
= Supplier emblem
= Last two digits of year of manufacture
= Week of manufacture
= Lot number
N
Y
W
L
PACKAGE OUTLINE DIAGRAM
Low Input Voltage, Adjustable Frequency Dual Synchronous
2
A / 2
A Buck Regulator with Synchronization, 2× EN, and 2× NPOR
A8651
34
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Revision History
Revision Revision Date Description of Revision
1 July 2, 2014 Removed references to DSYNC
2 September 25, 2014 Revised equation 2
3 September 29, 2014 Revised Switching Frequency values
4 February 20, 2015 Revised equation 4b
5 April 17, 2015 Added -1 option
6 June 10, 2015 Revised soft-start fault/hiccup reset voltage values
7 January 28, 2016 Updated functional block diagrams, last paragraph of Soft-Start (startup) and Inrush Current Control
section, and Table 2: Summary of A8651 Fault Modes and Operation.
8 December 5, 2016 Updated status of A8651KLPTR-T part variant to Discontinued
For the latest version of this document, visit our website:
www.allegromicro.com
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.