AD1934YSTZ - Analog Devices - Datasheet.Directory

8-Channel DAC with PLL and

Single-Ended Outputs, 192 kHz, 24 Bits

AD1934

Rev. C

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

PLL generated or direct master clock

Low EMI design

108 dB DAC dynamic range and SNR

−94 dB THD + N

Single 3.3 V supply

Tolerance for 5 V logic inputs

Supports 24 bits and 8 kHz to 192 kHz sample rates

Single-ended DAC output

Log volume control with autoramp function

SPI® controllable for flexibility

Software-controllable clickless mute

Software power-down

Right-justified, left-justified, I2S, and TDM modes

Master and slave modes up to 16-channel in/out

48-lead LQFP

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Home theater systems

Set-top boxes

Digital audio effects processors

GENERAL DESCRIPTION

The AD1934 is a high performance, single chip that provides

eight digital-to-analog converters (DACs) with single-ended

output using the Analog Devices, Inc., patented multibit sigma-

delta (Σ-Δ) architecture. An SPI port is included, allowing a

microcontroller to adjust volume and many other parameters.

The AD1934 operates from 3.3 V digital and analog supplies.

The AD1934 is available in a 48-lead (single-ended output)

LQFP. Other members of this family include a differential DAC

output version.

The AD1934 is designed for low EMI. This consideration is

apparent in both the system and circuit design architectures.

By using the on-board PLL to derive the master clock from the

LR clock or from an external crystal, the AD1934 eliminates the

need for a separate high frequency master clock and can also be

used with a suppressed bit clock. The DACs are designed using

the latest Analog Devices continuous time architectures to further

minimize EMI. By using 3.3 V supplies, power consumption is

minimized, further reducing emissions.

FUNCTIONAL BLOCK DIAGRAM

6106-001

SERIAL

DATA

PORT

PRECISION

VOLTAGE

REFERENCE

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL)

CONTROL PORT

SPI

CONTROL DATA

INPUT/OUTPUT

AD1934

DIGITAL AUDIO

INPUT/OUTPUT SDATAIN

CLOCKS

ANALOG

AUDIO

OUTPUTS

6.144MHz

DAC

DIGITAL

FILTER

AND

VOLUME

CONTROL

Figure 1.

AD1934

Rev. C | Page 2 of 28

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Test Conditions............................................................................. 3

Analog Performance Specifications........................................... 3

Crystal Oscillator Specifications................................................. 4

Digital Input/Output Specifications........................................... 4

Power Supply Specifications........................................................ 5

Digital Filters................................................................................. 6

Timing Specifications .................................................................. 6

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Theory of Operation ...................................................................... 12

Digital-to-Analog Converters (DACs) .................................... 12

Clock Signals............................................................................... 12

Reset and Power-Down ............................................................. 12

Serial Control Port ..................................................................... 13

Power Supply and Voltage Reference....................................... 14

Serial Data Ports—Data Format............................................... 14

Time-Division Multiplexed (TDM) Modes............................ 14

Daisy-Chain Mode..................................................................... 16

Control Registers............................................................................ 20

Definitions................................................................................... 20

PLL and Clock Control Registers............................................. 20

DAC Control Registers.............................................................. 21

Auxiliary TDM Port Control Registers................................... 23

Additional Modes....................................................................... 23

Application Circuits ....................................................................... 25

Outline Dimensions ....................................................................... 26

Ordering Guide .......................................................................... 26

Automotive Products................................................................. 26

REVISION HISTORY

7/11—Rev. B to Rev. C

Deleted References to I2C ............................................. Throughout

Changes to Figure 2 and Table 10, DSDATAx/AUXDATA1 Pin

Descriptions ...................................................................................... 9

1/11—Rev. A to Rev. B

Added Automotive Information.................................. Throughout

Change to Table 2, Introductory Text ............................................ 4

Change to Table 4, Introductory Text ............................................ 4

Change to Table 7, Introductory Text ............................................ 6

Changes to Ordering Guide.......................................................... 26

9/09—Rev. 0 to Rev. A

Change to Title...................................................................................1

Change to Table 11 ......................................................................... 13

Change to Power Supply and Voltage Reference Section.......... 14

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide.......................................................... 26

8/07—Revision 0: Initial Version

AD1934

Rev. C | Page 3 of 28

SPECIFICATIONS

TEST CONDITIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.

Supply Voltages (AVDD, DVDD) 3.3 V

Temperature Range1 As specified in Table 1 and Table 2

Master Clock 12.288 MHz (48 kHz fS, 256 × fS mode)

Input Sample Rate 48 kHz

Measurement Bandwidth 20 Hz to 20 kHz

Word Width 24 bits

Load Capacitance (Digital Output) 20 pF

Load Current (Digital Output) ±1 mA or 1.5 kΩ to ½ DVDD supply

Input Voltage HI 2.0 V

Input Voltage LO 0.8 V

1 Functionally guaranteed at −40°C to +125°C case temperature.

ANALOG PERFORMANCE SPECIFICATIONS

Specifications guaranteed at 25°C (ambient).

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 98 104 dB

With A-Weighted Filter (RMS) 100 106 dB

With A-Weighted Filter (Average) 108 dB

Total Harmonic Distortion + Noise 0 dBFS

Single-Ended Version Two channels running −92 dB

Eight channels running −86 −75 dB

Full-Scale Output Voltage 0.88 (2.48) V rms (V p-p)

Gain Error −10 +10 %

Interchannel Gain Mismatch −0.2 +0.2 dB

Offset Error −16 −4 +16 mV

Gain Drift −30 +30 ppm/°C

Interchannel Isolation 100 dB

Interchannel Phase Deviation 0 Degrees

Volume Control Step 0.375 dB

Volume Control Range 95 dB

De-emphasis Gain Error ±0.6 dB

Output Resistance at Each Pin 100 Ω

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V

External Reference Voltage FILTR pin 1.32 1.50 1.68 V

Common-Mode Reference Output CM pin 1.50 V

AD1934

Rev. C | Page 4 of 28

Specifications measured at 125°C (case).

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range 20 Hz to 20 kHz, −60 dB input

No Filter (RMS) 98 104 dB

With A-Weighted Filter (RMS) 100 106 dB

With A-Weighted Filter (Average) 108 dB

Total Harmonic Distortion + Noise 0 dBFS

Single-Ended Version Two channels running −92 dB

Eight channels running −86 −70 dB

Full-Scale Output Voltage 0.8775 (2.482) V rms (V p-p)

Gain Error −10 +10 %

Interchannel Gain Mismatch −0.2 +0.2 dB

Offset Error −16 −4 +16 mV

Gain Drift −30 +30 ppm/°C

REFERENCE

Internal Reference Voltage FILTR pin 1.50 V

External Reference Voltage FILTR pin 1.32 1.50 1.68 V

Common-Mode Reference Output CM pin 1.50 V

CRYSTAL OSCILLATOR SPECIFICATIONS

Table 3.

Parameter Min Typ Max Unit

Transconductance 3.5 mmhos

DIGITAL INPUT/OUTPUT SPECIFICATIONS

−40°C < TC < 125°C, DVDD = 3.3 V ± 10%.

Table 4.

Parameter Test Conditions/Comments Min Typ Max Unit

Input Voltage HI (VIH) 2.0 V

Input Voltage HI (VIH) MCLKI pin 2.2 V

Input Voltage LO (VIL) 0.8 V

Input Leakage IIH @ VIH = 2.4 V 10 μA

IL @ VIL = 0.8 V 10 μA

High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V

Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V

Input Capacitance 5 pF

AD1934

Rev. C | Page 5 of 28

POWER SUPPLY SPECIFICATIONS

Table 5.

Parameter Test Conditions/Comments Min Typ Max Unit

SUPPLIES

Voltage

DVDD 3.0 3.3 3.6 V

AVDD 3.0 3.3 3.6 V

Digital Current MCLK = 256 fS

Normal Operation fS = 48 kHz 56 mA

S = 96 kHz 65 mA

S = 192 kHz 95 mA

Power-Down fS = 48 kHz to 192 kHz 2.0 mA

Analog Current

Normal Operation 74 mA

Power-Down 23 mA

DISSIPATION

Operation MCLK = 256 fS, 48 kHz

All Supplies 429 mW

Digital Supply 185 mW

Analog Supply 244 mW

Power-Down, All Supplies 83 mW

POWER SUPPLY REJECTION RATIO

Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB

20 kHz, 200 mV p-p 50 dB

AD1934

Rev. C | Page 6 of 28

DIGITAL FILTERS

Table 6.

Parameter Mode Factor Min Typ Max Unit

DAC INTERPOLATION FILTER

Pass Band 48 kHz mode, typ @ 48 kHz 0.4535 fS 22 kHz

96 kHz mode, typ @ 96 kHz 0.3646 fS 35 kHz

192 kHz mode, typ @ 192 kHz 0.3646 fS 70 kHz

Pass-Band Ripple 48 kHz mode, typ @ 48 kHz ±0.01 dB

96 kHz mode, typ @ 96 kHz ±0.05 dB

192 kHz mode, typ @ 192 kHz ±0.1 dB

Transition Band 48 kHz mode, typ @ 48 kHz 0.5 fS 24 kHz

96 kHz mode, typ @ 96 kHz 0.5 fS 48 kHz

192 kHz mode, typ @ 192 kHz 0.5 fS 96 kHz

Stop Band 48 kHz mode, typ @ 48 kHz 0.5465 fS 26 kHz

96 kHz mode, typ @ 96 kHz 0.6354 fS 61 kHz

192 kHz mode, typ @ 192 kHz 0.6354 fS 122 kHz

Stop-Band Attenuation 48 kHz mode, typ @ 48 kHz 70 dB

96 kHz mode, typ @ 96 kHz 70 dB

192 kHz mode, typ @ 192 kHz 70 dB

Group Delay 48 kHz mode, typ @ 48 kHz 25/fS 521 μs

96 kHz mode, typ @ 96 kHz 11/fS 115 μs

192 kHz mode, typ @ 192 kHz 8/fS 42 μs

TIMING SPECIFICATIONS

−40°C < TC < 125°C, DVDD = 3.3 V ± 10%.

Table 7.

Parameter Condition Comments Min Max Unit

INPUT MASTER CLOCK (MCLK) AND RESET

tMH MCLK duty cycle DAC clock source = PLL clock @ 256 fS,

384 fS, 512 fS, 768 fS

40 60 %

tMH

DAC clock source = direct MCLK @ 512 fS

(bypass on-chip PLL)

40 60 %

fMCLK MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz

fMCLK Direct 512 fS mode 27.6 MHz

tPDR RST low 15 ns

tPDRR RST recovery Reset to active output 4096 tMCLK

PLL

Lock Time MCLK and LRCLK input 10 ms

256 fS VCO Clock, Output Duty Cycle

MCLKO Pin

40 60 %

SPI PORT See Figure 9

tCCH CCLK high 35 ns

tCCL CCLK low 35 ns

fCCLK CCLK frequency fCCLK = 1/tCCP, only tCCP shown in Figure 9 10 MHz

tCDS CDATA setup To CCLK rising 10 ns

tCDH CDATA hold From CCLK rising 10 ns

tCLS CLATCH setup To CCLK rising 10 ns

tCLH CLATCH hold From CCLK falling 10 ns

tCLHIGH CLATCH high Not shown in Figure 9 10 ns

tCOE COUT enable From CCLK falling 30 ns

tCOD COUT delay From CCLK falling 30 ns

tCOH COUT hold From CCLK falling, not shown in Figure 9 30 ns

tCOTS COUT tri-state From CCLK falling 30 ns

AD1934

Rev. C | Page 7 of 28

Parameter Condition Comments Min Max Unit

DAC SERIAL PORT See Figure 16

tDBH DBCLK high Slave mode 10 ns

tDBL DBCLK low Slave mode 10 ns

tDLS DLRCLK setup To DBCLK rising, slave mode 10 ns

tDLH DLRCLK hold From DBCLK rising, slave mode 5 ns

tDLS DLRCLK skew From DBCLK falling, master mode −8 +8 ns

tDDS DSDATA setup To DBCLK rising 10 ns

tDDH DSDATA hold From DBCLK rising 5 ns

AUXTDM SERIAL PORT See Figure 17

tABH AUXTDMBCLK high Slave mode 10 ns

tABL AUXTDMBCLK low Slave mode 10 ns

tALS AUXTDMLRCLK setup To AUXTDMBCLK rising, slave mode 10 ns

tALH AUXTDMLRCLK hold From AUXTDMBCLK rising, slave mode 5 ns

tALS AUXTDMLRCLK skew From AUXTDMBCLK falling, master mode −8 +8 ns

tDDS DSDATA setup To AUXTDMBCLK, not shown in Figure 17 10 ns

tDDH DSDATA hold

From AUXTDMBCLK rising, not shown in

Figure 17

5 ns

AUXILIARY INTERFACE

tDXDD AUXDATA delay From AUXBCLK falling 18 ns

tXBH AUXBCLK high 10 ns

tXBL AUXBCLK low 10 ns

tDLS AUXLRCLK setup To AUXBCLK rising 10 ns

tDLH AUXLRCLK hold From AUXBCLK rising 5 ns

AD1934

Rev. C | Page 8 of 28

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating

Analog (AVDD) −0.3 V to +3.6 V

Digital (DVDD) −0.3 V to +3.6 V

Input Current (Except Supply Pins) ±20 mA

Analog Input Voltage (Signal Pins) −0.3 V to AVDD + 0.3 V

Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V

Operating Temperature Range (Case) −40°C to +125°C

Storage Temperature Range −65°C to +150°C

THERMAL RESISTANCE

θJA represents thermal resistance, junction-to-ambient;

θJC represents the thermal resistance, junction-to-case.

All characteristics are for a 4-layer board.

Table 9. Thermal Resistance

Package Type θJA θ

JC Unit

48-Lead LQFP 50.1 17 °C/W

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

AD1934

Rev. C | Page 9 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

06106-020

AVDD

DVDD

DSDATA3

DSDATA2

DSDATA1

DBCLK

DLRCLK

AUXDATA1

AUXTDMBCLK

AUXTDMLRCLK

CIN

COUT

AGND

MCLKI/XI

MCLKO/XO

AGND

AVDD

OL3

OR3

OL4

OR4

PD/RST

DSDATA4

DGND

AGND

FILTR

AGND

AVDD

AGND

OR2

OL2

OR1

OL1

CLATCH

CCLK

DGND

AD1934

TOP VIEW

(Not to Scale)

SINGLE-ENDED

OUTPUT

NC = NO CONNECT

Figure 2. Pin Configuration

Table 10. Pin Function Description

Pin No. Input/Output Mnemonic Description

1 I AGND Analog Ground.

2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input.

3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output.

4 I AGND Analog Ground.

5 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.

6 O OL3 DAC 3 Left Output.

7 O OR3 DAC 3 Right Output.

8 O OL4 DAC 4 Left Output.

9 O OR4 DAC 4 Right Output.

10 I PD/RST Power-Down Reset (Active Low).

11 I/O DSDATA4 DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line

mode)/AUX DAC2 data out (to external DAC2).

12 I DGND Digital Ground.

13 I DVDD Digital Power Supply. Connect to digital 3.3 V supply.

14 I/O DSDATA3 DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line

mode)/AUX not used.

15 I/O DSDATA2 DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC2 data out/AUX not used.

16 I DSDATA1 DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/AUX TDM data in.

17 I/O DBCLK Bit Clock for DACs (Regular Stereo, TDM, or Daisy-Chain TDM Mode).

18 I/O DLRCLK LR Clock for DACs (Regular Stereo, TDM, or Daisy-Chain TDM Mode).

19 O AUXDATA1 AUX DAC1 data out (to external DAC1).

20 NC No Connect.

21 I/O AUXTDMBCLK Auxiliary Mode Only DAC TDM Bit Clock.

22 I/O AUXTDMLRCLK Auxiliary Mode Only DAC LR TDM Clock.

23 I CIN/ADR0 Control Data Input (SPI).

24 I/O COUT/SDA Control Data Output (SPI).

25 I DGND Digital Ground.

AD1934

Rev. C | Page 10 of 28

Pin No. Input/Output Mnemonic Description

26 I CCLK/SCL Control Clock Input (SPI).

27 I CLATCH/ADR1 Latch Input for Control Data (SPI).

28 O OL1 DAC 1 Left Output.

29 O OR1 DAC 1 Right Output.

30 O OL2 DAC 2 Left Output.

31 O OR2 DAC 2 Right Output.

32 I AGND Analog Ground.

33 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.

34 I AGND Analog Ground.

35 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.

36 I AGND Analog Ground.

37 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.

38 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND.

39 to 46 NC Must Be Tied to Common Mode, Pin 38. Alternately, ac-coupled to ground.

47 O LF PLL Loop Filter. Return to AVDD.

48 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.

AD1934

Rev. C | Page 11 of 28

TYPICAL PERFORMANCE CHARACTERISTICS

0.06

0.04

0.02

–0.06

–0.04

–0.02

02168

MAGNITUDE (dB)

FREQUENCY (kHz)

06106-004

–150

–100

–50

0924 48 72

MAGNITUDE (dB)

FREQUENCY (kHz)

06106-007

Figure 6. DAC Stop-Band Filter Response, 96 kHz

Figure 3. DAC Pass-Band Filter Response, 48 kHz

–150

–100

–50

0412 24 36

MAGNITUDE (dB)

FREQUENCY (kHz)

06106-005

0.5

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0681632

MAGNITUDE (dB)

FREQUENCY (kHz)

06106-008

Figure 4. DAC Stop-Band Filter Response, 48 kHz Figure 7. DAC Pass-Band Filter Response, 192 kHz

0.10

–0.10

–0.05

0.05

09724824

MAGNITUDE (dB)

FREQUENCY (kHz)

–10

–8

–6

–4

–2

48 9664 80

MAGNITUDE (dB)

FREQUENCY (kHz)

06106-009

06106-006

Figure 8. DAC Stop-Band Filter Response, 192 kHz

Figure 5. DAC Pass-Band Filter Response, 96 kHz

AD1934

Rev. C | Page 12 of 28

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTERS (DACs)

The AD1934 DAC channels are arranged as single-ended, four

stereo pairs giving eight analog outputs for minimum external

components. The DACs include on-board digital reconstruction

filters with 70 dB stop-band attenuation and linear phase response,

operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes)

or 2 (192 kHz mode). Each channel has its own independently

programmable attenuator, adjustable in 255 steps in increments

of 0.375 dB. Digital inputs are supplied through four serial data

input pins (one for each stereo pair) and a common frame

(DLRCLK) and bit (DBCLK) clock. Alternatively, one of the

TDM modes can be used to access up to 16 channels on a single

TDM data line.

Each output pin has a nominal common-mode dc level of 1.5 V

and swings ±1.27 V for a 0 dBFS digital input signal. A single op

amp, third-order, external, low-pass filter is recommended to

remove high frequency noise present on the output pins. The

use of op amps with low slew rate or low bandwidth can cause

high frequency noise and tones to fold down into the audio

band; therefore, exercise care in selecting these components.

The voltage at CM, the common-mode reference pin, can be

used to bias the external op amps that buffer the output signals

(see the Power Supply and Voltage Reference section).

CLOCK SIGNALS

The on-chip phase locked loop (PLL) can be selected to

reference the input sample rate from either of the LRCLK pins

or 256, 384, 512, or 768 times the sample rate, referenced to the

48 kHz mode from the MCLKI pin. The default at power-up is

256 × fS from MCLKI pin. In 96 kHz mode, the master clock

frequency stays at the same absolute frequency; therefore, the

actual multiplication rate is divided by 2. In 192 kHz mode,

the actual multiplication rate is divided by 4. For example, if a

device in the AD1934 family is programmed in 256 × fS mode, the

frequency of the master clock input is 256 × 48 kHz = 12.288 MHz.

If the AD1934 is then switched to 96 kHz operation (by writing

to the SPI port), the frequency of the master clock should

remain at 12.288 MHz, which is now 128 × fS. In 192 kHz mode,

this becomes 64 × fS.

The internal clock for the DACs varies by mode: 512 × fS (48 kHz

mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By

default, the on-board PLL generates this internal master clock

from an external clock. A direct 512 × fS (referenced to 48 kHz

mode) master clock can be used for DACs if selected in PLL

and Clock Control 1 Register.

The PLL can be powered down in PLL and Clock Control 0

or if the reference clock is unstable at power-on, power down

the PLL and then power it back up when the reference clock

has stabilized.

The internal MCLK can be disabled in PLL and Clock Control 0

The clock should be stable before it is enabled. Unless a stand-

alone mode is selected (see the Serial Control Port section), the

clock is disabled by reset and must be enabled by writing to the

SPI port for normal operation.

To maintain the highest performance possible, it is recommended

that the clock jitter of the internal master clock signal be limited

to less than 300 ps rms time interval error (TIE). Even at these

levels, extra noise or tones can appear in the DAC outputs if the

jitter spectrum contains large spectral peaks. If the internal PLL

is not being used, it is highly recommended that an independent

crystal oscillator generate the master clock. In addition, it is

especially important that the clock signal not be passed through

an FPGA, CPLD, or other large digital chip (such as a DSP)

before being applied to the AD1934. In most cases, this induces

clock jitter due to the sharing of common power and ground

connections with other unrelated digital output signals. When

the PLL is used, jitter in the reference clock is attenuated above

a certain frequency depending on the loop filter.

RESET AND POWER-DOWN

Reset sets all the control registers to their default settings.

To avoid pops, reset does not power down the analog outputs.

After reset is deasserted, and the PLL acquires lock condition,

an initialization routine runs inside the AD1934. This

initialization lasts for approximately 256 MCLKs.

The power-down bits in the PLL and Clock Control 0 and DAC

Control 1 registers power down the respective sections. All

other register settings are retained. To guarantee proper startup,

the reset pin should be pulled low by an external resistor.

AD1934

Rev. C | Page 13 of 28

SERIAL CONTROL PORT

The AD1934 has an SPI control port that permits programming

and reading back of the internal control registers for the DACs

and clock system. There is also a standalone mode available for

operation without serial control that is configured at reset using

the serial control pins. All registers are set to default, except the

internal MCLK enable which is set to 1. Standalone mode only

supports stereo mode with I2S data format and 256 fS master

clock rate. Table 11 shows the SPI control port pins logic state

when configured in standalone and SPI software control mode.

All four SPI control port pins need to be set to logic low for

standalone operation (see Table 11). It is recommended to use a

weak pull-up resistor on CLATCH in applications that have a

microcontroller. This pull-up resistor ensures that the AD1934

recognizes the presence of a microcontroller.

The SPI control port of the AD1934 is a 4-wire serial control

port. The format is similar to the Motorola SPI format except

the input data-word is 24 bits wide. The serial bit clock and

latch can be completely asynchronous to the sample rate of the

DACs. Figure 9 shows the format of the SPI signal. The first

byte is a global address with a read/write bit. For the AD1934,

the address is 0x04, shifted left 1 bit due to the R/W bit. The

second byte is the AD1934 register address and the third byte

is the data.

Table 11. SPI vs. Standalone Mode Configuration

DAC Control COUT CIN CLATCH CCLK

SPI OUT IN 1 (Pull-Up) IN

Standalone 0 0 0 0

D22D23 D9

LATCH

CCLK

CIN

COUT

CCH

CCL

CDS

CDH

CLS

CCP

CLH

COTS

COD

COE

06106-010

Figure 9. Format of SPI Signal

AD1934

Rev. C | Page 14 of 28

POWER SUPPLY AND VOLTAGE REFERENCE

The AD1934 is designed for 3.3 V supplies. Separate power

supply pins are provided for the analog and digital sections.

These pins should be bypassed with 100 nF ceramic chip

capacitors, as close to the pins as possible, to minimize noise

pickup. A bulk aluminum electrolytic capacitor of at least 22 μF

should also be provided on the same PC board as the DAC. For

critical applications, improved performance is obtained with

separate supplies for the analog and digital sections. If this is

not possible, it is recommended that the analog and digital

supplies be isolated by means of a ferrite bead in series with

each supply. It is important that the analog supply be as

clean as possible.

All digital inputs are compatible with TTL and CMOS levels.

All outputs are driven from the 3.3 V DVDD supply and are

compatible with TTL and 3.3 V CMOS levels.

The DAC internal voltage reference (VREF) is brought out on

FILTR and should be bypassed as close as possible to the chip,

with a parallel combination of 10 μF and 100 nF. Any external

current drawn should be limited to less than 50 μA.

The internal reference can be disabled in PLL and Clock

Control 1 Register and FILTR can be driven from an external

source. This can be used to scale the DAC output to the clipping

level of a power amplifier based on its power supply voltage.

The CM pin is the internal common-mode reference. It should

be bypassed as close as possible to the chip, with a parallel

combination of 47 μF and 100 nF. This voltage can be used to

bias external op amps to the common-mode voltage of the input

and output signal pins. The output current should be limited to

less than 0.5 mA source and 2 mA sink.

SERIAL DATA PORTS—DATA FORMAT

The eight DAC channels use a common serial bit clock (DBCLK)

and a common left-right framing clock (DLRCLK) in the serial

data port. The clock signals are all synchronous with the sample

rate. The normal stereo serial modes are shown in Figure 15.

The DAC serial data modes default to I2S. The ports can also be

programmed for left-justified, right-justified, and TDM modes.

The word width is 24 bits by default and can be programmed

for 16 or 20 bits. The DAC serial formats are programmable

according to DAC Control 0 Register. The polarity of the

DBCLK and DLRCLK is programmable according to DAC

Control 1 Register. The auxiliary TDM port is also provided for

applications requiring more than eight DAC channels. In this

mode, the AUXTDMLRCLK and AUXTDMBCLK pins are

configured as TDM port clocks. In regular TDM mode, the

DLRCLK and DBCLK pins are used as the TDM port clocks.

The auxiliary TDM serial port’s format and its serial clock

polarity is programmable according to the Auxiliary TDM Port

Control 0 Register and Control 1 Register. Both DAC and

auxiliary TDM serial ports are programmable to become the

bus masters according to DAC Control 1 Register and auxiliary

TDM Control 1 Register. By default, both auxiliary TDM and

DAC serial ports are in the slave mode.

TIME-DIVISION MULTIPLEXED (TDM) MODES

The AD1934 serial ports also have several different TDM serial

data modes. The most commonly used configuration is shown

in Figure 10. In Figure 10, the eight on-chip DAC data slots are

packed into one TDM stream. In this mode, DBCLK is 256 fS.

The I/O pins of the serial ports are defined according to the

serial mode selected. For a detailed description of the function

of each pin in TDM and AUX Modes, see Table 12.

The AD1934 allows systems with more than eight DAC channels

to be easily configured by the use of an auxiliary serial data port.

The DAC TDM-AUX mode is shown in Figure 11. In this mode,

the AUX channels are the last four slots of the 16-channel TDM

data stream. These slots are extracted and output to the AUX

serial port. One major difference between the TDM mode and

an auxiliary TDM mode is the assignment of the TDM port

pins, as shown in Table 12. In auxiliary TDM mode, DBCLK

and DLRCLK are assigned as the auxiliary port clocks, and

AUXTDMBCLK and AUXTDMLRCLK are assigned as the

TDM port clocks. In regular TDM or 16-channel, daisy-chain

TDM mode, the DLRCLK and DBCLK pins are set as the TDM

port clocks. It should be noted that due to the high

AUXTDMBCLK frequency, 16-channel auxiliary TDM mode is

available only in the 48 kHz/44.1 kHz/32 kHz sample rate.

SLOT 1

LEFT 1

SLOT 2

RIGHT 1

SLOT 3

LEFT 2

SLOT 4

RIGHT 2

MSB MSB–1 MSB–2 DATA

BCLK

LRCLK

SLOT 5

LEFT 3

SLOT 6

RIGHT 3

SLOT 7

LEFT 4

SLOT 8

RIGHT 4

LRCLK

BCLK

DATA

256 BCLKs

32 BCLK

06106-017

Figure 10. DAC TDM (8-Channel I2S Mode)

AD1934

Rev. C | Page 15 of 28

Table 12. Pin Function Changes in TDM and AUX Modes

Pin Name Stereo Modes TDM Modes AUX Modes

AUXDATA1 Not Used (Float) Not Used (Float) AUX Data Out 1 (to External DAC 1)

DSDATA1 DAC1 Data In DAC TDM Data In TDM Data In

DSDATA2 DAC2 Data In DAC TDM Data Out Not Used (Ground)

DSDATA3 DAC3 Data In DAC TDM Data In 2 (Dual-Line Mode) Not Used (Ground)

DSDATA4 DAC4 Data In DAC TDM Data Out 2 (Dual-Line Mode) AUX Data Out 2 (to External DAC 2)

AUXTDMLRCLK Not Used (Ground) Not Used (Ground) TDM Frame Sync In/Out

AUXTDMBCLK Not Used (Ground) Not Used (Ground) TDM BCLK In/Out

DLRCLK DAC LRCLK In/Out DAC TDM Frame Sync In/Out AUX LRCLK In/Out

DBCLK DAC BCLK In/Out DAC TDM BCLK In/Out AUX BCLK In/Out

LEFT RIGHT

MSB MSB

AUXTDMLRCLK

AUXTDMBCLK

DSDATA1

(TDM_IN)

DLRCLK

(AUX PORT)

DBCLK

(AUX PORT)

AUXDATA1

(AUX1_OUT)

DSDATA4

(AUX2_OUT)

MSB

EMPTY EMPTY EMPTY EMPTY DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2

8-ON-CHIP DAC CHANNELS

AUXILIARY DAC CHANNELS

WILL APPEAR AT

AUX DAC PORTSUNUSED SLOTS

32 BITS

6106-051

Figure 11. 16-Channel DAC TDM-AUX Mode

AD1934

Rev. C | Page 16 of 28

DAISY-CHAIN MODE

The AD1934 also allows a daisy-chain configuration to expand

the system 16 DACs (see Figure 12). In this mode, the DBCLK

frequency is 512 fS. The first eight slots of the DAC TDM data

stream belong to the first AD1934 in the chain and the last eight

slots belong to the second AD1934. The second AD1934 is the

device attached to the DSP TDM port.

To accommodate 16 channels at a 96 kHz sample rate, the

AD1934 can be configured into a dual-line, DAC TDM mode,

as shown in Figure 13. This mode allows a slower DBCLK than

normally required by the one-line TDM mode.

Again, the first four channels of each TDM input belong to the

first AD1934 in the chain and the last four channels belong to

the second AD1934.

The dual-line, DAC TDM mode can also be used to send data at

a 192 kHz sample rate into the AD1934, as shown in Figure 14.

The I/O pins of the serial ports are defined according to the

serial mode selected. See Tabl e 1 3 for a detailed description of

the function of each pin. See Figure 18 for a typical AD1934

configuration with two external stereo DACs. Figure 15 and

Figure 16 show the serial mode formats. For maximum

flexibility, the polarity of LRCLK and BCLK are programmable.

In these figures, all of the clocks are shown with their normal

polarity. The default mode is I2S.

DLRCLK

DBCLK

8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN

8 UNUSED SLOTS

8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN

MSB

DSDATA1 (TDM_IN)

OF THE SECOND AD1934

DSDATA2 (TDM_OUT)

OF THE SECOND AD1934

THIS IS THE TDM

TO THE FIRST AD1934

DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4

DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4

32 BITS

DSP

SECOND

AD1934

FIRST

AD1934

06106-054

Figure 12. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain)

DLRCLK

DBCLK

8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN

DSDATA1

(IN) DAC L1 DAC R1 DAC L2 DAC R2 DAC L1 DAC R1 DAC L2 DAC R2

DSDATA3

(IN) DAC L3 DAC R3 DAC L4 DAC R4 DAC L3 DAC R3 DAC L4 DAC R4

DSDATA2

(OUT) DAC L1 DAC R1 DAC L2 DAC R2

DSDATA4

(OUT) DAC L3 DAC R3 DAC L4 DAC R4

32 BITS

DSP

SECOND

AD1934

FIRST

AD1934

MSB

06106-055

Figure 13. Dual-Line, DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain; DSDATA3 and DSDATA4 Are the Daisy Chain)

AD1934

Rev. C | Page 17 of 28

06106-058

DLRCLK

DBCLK

DSDATA1 DAC L1 DAC R1 DAC L2 DAC R2

DSDATA2 DAC L3 DAC R3 DAC L4 DAC R4

32 BITS

MSB

Figure 14. Dual-Line, DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode)

LRCLK

BCLK

SDAT

LRCLK

BCLK

SDAT

LRCLK

BCLK

SDAT

LSB LSB

LSB

LSB LSB

LEFT CHANNEL RIGHT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

LEFT CHANNEL RIGHT CHANNEL

MSB MSB

MSB

MSB MSB

RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL

DSP MODE—16 BITS TO 24 BITS PER CHANNEL

I2S MODE—16 BITS TO 24 BITS PER CHANNEL

LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL

LRCLK

BCLK

SDAT

LSB LSB

NOTES

1. DSP MODE DOES NOT IDENTIFY CHANNEL.

2. LRCLK NORMALLY OPERATES AT

S EXCEPT FOR DSP MODE, WHICH IS 2 ×

3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.

MSB MSB

06106-013

Figure 15. Stereo Serial Modes

AD1934

Rev. C | Page 18 of 28

DBCLK

DLRCLK

DSDATA

LEFT-JUSTIFIED

MODE

DSDATA

RIGHT-JUSTIFIED

MODE

DSDATA

S-JUSTIFIED

MODE

DLH

DBH

DBL

DLS

DDS

MSB

MSB LSB

MSB–1

DDH

DDS

DDH

DDS

DDH

DDS

06106-014

Figure 16. DAC Serial Timing

AUXTDMBCLK

AUXTDMLRCLK

DSDATA1

LEFT-JUSTIFIED

MODE

DSDATA1

RIGHT-JUSTIFIED

MODE

DSDATA1

S-JUSTIFIED

MODE

ABH

LSB

MSB

MSB–1

ABL

ALS

ALH

06106-015

Figure 17. AUXTDM Serial Timing

AD1934

Rev. C | Page 19 of 28

Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12)

Pin Name Stereo Modes TDM Modes AUX Modes

AUXDATA1 Not Used (Float) Not Used (Float) AUX Data Out 1 (to External DAC 1)

DSDATA1 DAC1 Data In DAC TDM Data In TDM Data In

DSDATA2 DAC2 Data In DAC TDM Data Out Not Used (Ground)

DSDATA3 DAC3 Data In DAC TDM Data In 2 (Dual-Line Mode) Not Used (Ground)

DSDATA4 DAC4 Data In DAC TDM Data Out 2 (Dual-Line Mode) AUX Data Out 2 (to External DAC 2)

AUXTDMLRCLK Not Used (Ground) Not Used (Ground) TDM Frame Sync In/Out

AUXTDMBCLK Not Used (Ground) Not Used (Ground) TDM BCLK In/Out

DLRCLK DAC LRCLK In/Out DAC TDM Frame Sync In/Out AUX LRCLK In/Out

DBCLK DAC BCLK In/Out DAC TDM BCLK In/Out AUX BCLK In/Out

AUX

DAC 1

AUX

DAC 2

LRCLK

BCLK

DATA

MCLK

LRCLK

BCLK

DATA

MCLK

30MHz

12.288MHz

SHARC IS RUNNING IN SLAVE MODE

(INTERRUPT-DRIVEN)

SHARC

AD1934

TDM MASTER

AUX MASTER

FSYNC-TDM (RFS)

RxCLK

TxCLK

TxDATA

TFS (NC)

AUXDATA1

DSDATA4

DBCLK

DLRCLK

DSDATA2

DSDATA3

MCLK

AUXTDMLRCLK AUXTDMBCLK DSDATA1

06106-019

Figure 18. Example of AUX Mode Connection to SHARC® (AD1934 as TDM Master/AUX Master Shown)

AD1934

Rev. C | Page 20 of 28

CONTROL REGISTERS

DEFINITIONS

The global address for the AD1934 is 0x04, shifted left 1 bit due to the R/W bit. All registers are reset to 0, except for the DAC volume

registers that are set to full volume.

Note that the first setting in each control register parameter is the default setting.

Table 14. Register Format

Global Address R/W Register Address Data

Bit 23:17 16 15:8 7:0

Table 15. Register Addresses and Functions

Address Function

0 PLL and Clock Control 0

1 PLL and Clock Control 1

2 DAC Control 0

3 DAC Control 1

4 DAC Control 2

5 DAC individual channel mutes

6 DAC 1L volume control

7 DAC 1R volume control

8 DAC 2L volume control

9 DAC 2R volume control

10 DAC 3L volume control

11 DAC 3R volume control

12 DAC 4L volume control

13 DAC 4R volume control

14 Reserved

15 Auxiliary TDM Port Control 0

16 Auxiliary TDM Port Control 1

PLL AND CLOCK CONTROL REGISTERS

Table 16. PLL and Clock Control 0

Bit Value Function Description

0 0 Normal operation PLL power-down

1 Power-down

2:1 00 INPUT 256 (×44.1 kHz or 48 kHz) MCLK pin functionality (PLL active)

01 INPUT 384 (×44.1 kHz or 48 kHz)

10 INPUT 512 (×44.1 kHz or 48 kHz)

11 INPUT 768 (×44.1 kHz or 48 kHz)

4:3 00 XTAL oscillator enabled MCLKO pin

01 256 × fS VCO output

10 512 × fS VCO output

11 Off

6:5 00 MCLK PLL input

01 DLRCLK

10 AUXTDMLRCLK

11 Reserved

7 0 Disable: DAC idle Internal MCLK enable

1 Enable: DAC active

AD1934

Rev. C | Page 21 of 28

Table 17. PLL and Clock Control 1

Bit Value Function Description

0 0 PLL clock DAC clock source select

1 MCLK

1 0 PLL clock Clock source select

1 MCLK

2 0 Enabled On-chip voltage reference

1 Disabled

3 0 Not locked PLL lock indicator (read-only)

1 Locked

7:4 0000 Reserved

DAC CONTROL REGISTERS

Table 18. DAC Control 0

Bit Value Function Description

0 0 Normal Power-down

1 Power-down

2:1 00 32 kHz/44.1 kHz/48 kHz Sample rate

01 64 kHz/88.2 kHz/96 kHz

10 128 kHz/176.4 kHz/192 kHz

11 Reserved

5:3 000 1 SDATA delay (BCLK periods)

001 0

010 8

011 12

100 16

101 Reserved

110 Reserved

111 Reserved

7:6 00 Stereo (normal) Serial format

01 TDM (daisy chain)

10 DAC aux mode (DAC-, TDM-coupled)

11 Dual-line TDM

Table 19. DAC Control 1

Bit Value Function Description

0 0 Latch in midcycle (normal) BCLK active edge (TDM in)

1 Latch in at end of cycle (pipeline)

2:1 00 64 (2 channels) BCLKs per frame

01 128 (4 channels)

10 256 (8 channels)

11 512 (16 channels)

3 0 Left low LRCLK polarity

1 Left high

4 0 Slave LRCLK master/slave

1 Master

5 0 Slave BCLK master/slave

1 Master

6 0 DBCLK pin BCLK source

1 Internally generated

7 0 Normal BCLK polarity

1 Inverted

AD1934

Rev. C | Page 22 of 28

Table 20. DAC Control 2

Bit Value Function Description

0 0 Unmute Master mute

1 Mute

2:1 00 Flat De-emphasis (32 kHz/44.1 kHz/48 kHz mode only)

01 48 kHz curve

10 44.1 kHz curve

11 32 kHz curve

4:3 00 24 Word width

01 20

10 Reserved

11 16

5 0 Noninverted DAC output polarity

1 Inverted

7:6 00 Reserved

Table 21. DAC Individual Channel Mutes

Bit Value Function Description

0 0 Unmute DAC 1 left mute

1 Mute

1 0 Unmute DAC 1 right mute

1 Mute

2 0 Unmute DAC 2 left mute

1 Mute

3 0 Unmute DAC 2 right mute

1 Mute

4 0 Unmute DAC 3 left mute

1 Mute

5 0 Unmute DAC 3 right mute

1 Mute

6 0 Unmute DAC 4 left mute

1 Mute

7 0 Unmute DAC 4 right mute

1 Mute

Table 22. DAC Volume Controls

Bit Value Function Description

7:0 0 No attenuation DAC volume control

1 to 254 −3/8 dB per step

255 Full attenuation

AD1934

Rev. C | Page 23 of 28

AUXILIARY TDM PORT CONTROL REGISTERS

Table 23. Auxiliary TDM Control 0

Bit Value Function Description

1:0 00 24 Word width

01 20

10 Reserved

11 16

4:2 000 1 SDATA delay (BCLK periods)

001 0

010 8

011 12

100 16

101 Reserved

110 Reserved

111 Reserved

6:5 00 Reserved Serial format

01 Reserved

10 DAC aux mode

11 Reserved

7 0 Latch in midcycle (normal) BCLK active edge (TDM in)

1 Latch in at end of cycle (pipeline)

Table 24. Auxiliary TDM Control 1

Bit Value Function Description

0 0 50/50 (allows 32/24/20/16 BCLK/channel) LRCLK format

1 Pulse (32 BCLK/channel)

1 0 Drive out on falling edge (DEF) BCLK polarity

1 Drive out on rising edge

2 0 Left low LRCLK polarity

1 Left high

3 0 Slave LRCLK master/slave

1 Master

5:4 00 64 BCLKs per frame

01 128

10 256

11 512

6 0 Slave BCLK master/slave

1 Master

7 0 AUXTDMBCLK pin BCLK source

1 Internally generated

ADDITIONAL MODES

The AD1934 offers several additional modes for board level

design enhancements. To reduce the EMI in board level design,

serial data can be transmitted without an explicit BCLK. See

Figure 19 for an example of a DAC TDM data transmission

mode that does not require high speed DBCLK. This configuration

is applicable when the AD1934 master clock is generated by the

PLL with the DLRCLK as the PLL reference frequency.

To relax the requirement for the setup time of the AD1934 in

cases of high speed TDM data transmission, the AD1934 can

latch in the data using the falling edge of DBCLK. This

effectively dedicates the entire BCLK period to the setup time.

This mode is useful in cases where the source has a large delay

time in the serial data driver. Figure 20 shows this pipeline

mode of data transmission.

Both the BLCK-less and pipeline modes are available.

AD1934

Rev. C | Page 24 of 28

DLRCLK

INTERNAL

DBCLK

DSDATA

DLRCLK

INTERNAL

DBCLK

TDM-DSDATA

32 BITS

06106-059

Figure 19. Serial DAC Data Transmission in TDM Format Without DBCLK (Applicable Only If PLL Locks to DLRCLK)

DLRCLK

DBCLK

DSDATA

DATA MUST BE VALID

AT THIS BCLK EDGE

MSB

06106-060

Figure 20. I2S Pipeline Mode in DAC Serial Data Transmission (Applicable in Stereo and TDM Useful for High Frequency TDM Transmission)

AD1934

Rev. C | Page 25 of 28

APPLICATION CIRCUITS

2OP275

–

4.75kΩ4.75kΩ

4.7µF

DAC OUT

240pF

NPO

270pF

NPO

3.3nF

NPO

AUDIO

OUTPUT

4.99kΩ

604Ω

4.99kΩ

49.9kΩ

06106-024

Typical applications circuits are shown in Figure 21, Figure 22,

and Figure 23. Recommended loop filters for LR clock and

master clock as the PLL reference are shown in Figure 21.

Output filters for the DAC outputs are shown in Figure 22 and

Figure 23 for the noninverting and inverting cases, respectively.

39nF

+2.2nF

LF LRCLK

VDD2

3.32kΩ

5.6nF

390pF

LF MCLK

AVDD2

562Ω

6106-027

Figure 22. Typical DAC Output Filter Circuit (Single-Ended, Noninverting)

3OP275

–

3.01kΩ11kΩ

4.7µF

DAC

OUT

0.1µF

270pF

NPO

68pF

NPO

2.2nF

NPO

AUDIO

OUTPUT

604Ω

49.9kΩ

11kΩ

06106-025

Figure 21. Recommended Loop Filters for LRCLK or MCLK PLL Reference

Figure 23. Typical DAC Output Filter Circuit (Single-Ended, Inverting)

AD1934

Rev. C | Page 26 of 28

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

0.50

BSC

LEAD PITCH

1.60

MAX

0.75

0.60

0.45

VIEW A

PIN 1

0.20

0.09

1.45

1.40

1.35

0.08

COPLANARITY

VIEW A

ROTATED 90° CCW

SEATING

PLANE

7°

3.5°

0°

0.15

0.05

9.20

9.00 SQ

8.80

7.20

7.00 SQ

6.80

051706-A

Figure 24. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

ORDERING GUIDE

Model1, 2 Temperature Range Package Description Package Option

AD1934YSTZ −40°C to +105°C 48-Lead LQFP ST-48

AD1934YSTZ-RL −40°C to +105°C 48-Lead LQFP, 13” Tape and Reel ST-48

AD1934WBSTZ −40°C to +105°C 48-Lead LQFP ST-48

AD1934WBSTZ-RL −40°C to +105°C 48-Lead LQFP, 13” Tape and Reel ST-48

EVAL-AD1938AZ Evaluation Board

1 Z = RoHS Compliant Part.

2 W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS

The AD1934WBSTZ and AD1934WBSTZ-RL models are available with controlled manufacturing to support the quality and reliability

requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial

models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products

shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product

ordering information and to obtain the specific Automotive Reliability reports for these models.

AD1934

Rev. C | Page 27 of 28

NOTES

AD1934

Rev. C | Page 28 of 28

NOTES

registered trademarks are the property of their respective owners.

D06106-0-7/11(C)