1. General description
The 74AUP1G08 provides the single 2-input AND function.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range fr om 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the outpu t, pr eve nting the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A. exceeds 5000 V
MM JESD22-A115-A exce eds 20 0 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 A (maximum)
Latch-up pe rform a nc e exceeds 100 mA per JESD 78 Clas s II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 Cto+85C and 40 Cto+125C
74AUP1G08
Low-power 2-input AND gate
Rev. 4 — 15 November 2011 Product data sheet
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 2 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AUP1G08GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm SOT353-1
74AUP1G08GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 1.45 0.5 mm SOT886
74AUP1G08GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 10.5 mm SOT891
74AUP1G08GN 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm SOT1115
74AUP1G08GS 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm SOT1202
Table 2. Marking
Type number Marking code[1]
74AUP1G08GW pE
74AUP1G08GM pE
74AUP1G08GF pE
74AUP1G08GN pE
74AUP1G08GS pE
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram
mna113
B
AY
2
14
mna114
24
&
1
mna221
A
B
Y
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 3 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level.
Fig 4. Pin configuration
SOT353-1 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891,
SOT1115 and SOT1202
74AUP1G08
BV
CC
A
GND Y
001aaf025
1
2
3
5
4
74AUP1G08
A
001aaf026
B
GND
n.c.
VCC
Y
Transparent top view
2
3
1
5
4
6
74AUP1G08
A
001aaf027
B
GND
n.c.
VCC
Y
Transparent top view
2
3
1
5
4
6
Table 3. Pin description
Symbol Pin Description
TSSOP5 XSON6
B 1 1 data input B
A 2 2 data input A
GND 3 3 ground (0 V)
Y 4 4 data output Y
n.c. - 5 not connected
VCC 5 6 supply voltage
Table 4. Function table[1]
Input Output
A B Y
LL L
LH L
HL L
HH H
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 4 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
8. Limiting values
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +4.6 V
IIK input clamping current VI<0V 50 - mA
VIinput voltage [1] 0.5 +4.6 V
IOK output clamping current VO<0V 50 - mA
VOoutput voltage Active mode an d Pow e r-d ow n m ode [1] 0.5 +4.6 V
IOoutput cur r en t VO=0 VtoV
CC -20 mA
ICC supply current - +50 mA
IGND ground curre nt 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C[2] -250mW
Table 6. Recommended operating con ditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.8 3.6 V
VIinput voltage 0 3.6 V
VOoutput voltage Active mode 0 VCC V
Power-down mode; VCC =0V 0 3.6 V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC = 0.8 V to 3.6 V 0 200 ns/V
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 5 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 C
VIH HIGH-level input voltage VCC = 0.8 V 0.70 VCC -- V
VCC = 0.9 V to 1.95 V 0.65 VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30 VCC V
VCC = 0.9 V to 1.95 V - - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.1 - - V
IO = 1.1 mA; VCC = 1.1 V 0.75 VCC -- V
IO = 1.7 mA; VCC = 1.4 V 1.11 - - V
IO = 1.9 mA; VCC = 1.65 V 1.32 - - V
IO = 2.3 mA; VCC = 2.3 V 2.05 - - V
IO = 3.1 mA; VCC = 2.3 V 1.9 - - V
IO = 2.7 mA; VCC = 3.0 V 2.72 - - V
IO = 4.0 mA; VCC = 3.0 V 2.6 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3 VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.31 V
IO = 1.9 mA; VCC = 1.65 V - - 0.31 V
IO = 2.3 mA; VCC = 2.3 V - - 0.31 V
IO = 3.1 mA; VCC = 2.3 V - - 0.44 V
IO = 2.7 mA; VCC = 3.0 V - - 0.31 V
IO = 4.0 mA; VCC = 3.0 V - - 0.44 V
IIinput leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.2 A
IOFF additional power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V --0.2 A
ICC supply current VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V --0.5A
ICC additional supply current VI = VCC 0.6 V; IO = 0 A;
VCC =3.3V [1] --40A
CIinput capacitance VCC = 0 V to 3.6 V; VI = GND or VCC -0.8-pF
COoutput capacitance VO = GND; VCC = 0 V - 1.7 - pF
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 6 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
Tamb = 40 C to +85 C
VIH HIGH-level input voltage VCC = 0.8 V 0.70 VCC -- V
VCC = 0.9 V to 1.95 V 0.65 VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.30 VCC V
VCC = 0.9 V to 1.95 V - - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.1 - - V
IO = 1.1 mA; VCC = 1.1 V 0.7 VCC -- V
IO = 1.7 mA; VCC = 1.4 V 1.03 - - V
IO = 1.9 mA; VCC = 1.65 V 1.30 - - V
IO = 2.3 mA; VCC = 2.3 V 1.97 - - V
IO = 3.1 mA; VCC = 2.3 V 1.85 - - V
IO = 2.7 mA; VCC = 3.0 V 2.67 - - V
IO = 4.0 mA; VCC = 3.0 V 2.55 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3 VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.37 V
IO = 1.9 mA; VCC = 1.65 V - - 0.35 V
IO = 2.3 mA; VCC = 2.3 V - - 0.33 V
IO = 3.1 mA; VCC = 2.3 V - - 0.45 V
IO = 2.7 mA; VCC = 3.0 V - - 0.33 V
IO = 4.0 mA; VCC = 3.0 V - - 0.45 V
IIinput leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A
IOFF additional power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V --0.6 A
ICC supply current VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V --0.9A
ICC additional supply current VI = VCC 0.6 V; IO = 0 A;
VCC =3.3V [1] --50A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 7 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
[1] One input at VCC 0.6 V, other input at VCC or GND.
Tamb = 40 C to +125 C
VIH HIGH-level input voltage VCC = 0.8 V 0.75 VCC -- V
VCC = 0.9 V to 1.95 V 0.70 VCC -- V
VCC = 2.3 V to 2.7 V 1.6 - - V
VCC = 3.0 V to 3.6 V 2.0 - - V
VIL LOW-level input voltage VCC = 0.8 V - - 0.25 VCC V
VCC = 0.9 V to 1.95 V - - 0.30 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 V
VOH HIGH-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.11 - - V
IO = 1.1 mA; VCC = 1.1 V 0.6 VCC -- V
IO = 1.7 mA; VCC = 1.4 V 0.93 - - V
IO = 1.9 mA; VCC = 1.65 V 1.17 - - V
IO = 2.3 mA; VCC = 2.3 V 1.77 - - V
IO = 3.1 mA; VCC = 2.3 V 1.67 - - V
IO = 2.7 mA; VCC = 3.0 V 2.40 - - V
IO = 4.0 mA; VCC = 3.0 V 2.30 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V
IO = 1.1 mA; VCC = 1.1 V - - 0.33 VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.41 V
IO = 1.9 mA; VCC = 1.65 V - - 0.39 V
IO = 2.3 mA; VCC = 2.3 V - - 0.36 V
IO = 3.1 mA; VCC = 2.3 V - - 0.50 V
IO = 2.7 mA; VCC = 3.0 V - - 0.36 V
IO = 4.0 mA; VCC = 3.0 V - - 0.50 V
IIinput leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A
IOFF additional power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V --0.75 A
ICC supply current VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V --1.4A
ICC additional supply current VI = VCC 0.6 V; IO = 0 A;
VCC =3.3V [1] --75A
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 8 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8
Symbol Parameter Conditions Min Typ [1] Max Unit
Tamb = 25 C; CL = 5 pF
tpd propagation delay A, B to Y; see Figure 7 [2]
VCC = 0.8 V - 17.0 - ns
VCC = 1.1 V to 1.3 V 2.6 5.1 10.8 ns
VCC = 1.4 V to 1.6 V 1.6 3.7 6.5 ns
VCC = 1.65 V to 1.95 V 1.3 3.0 5.2 ns
VCC = 2.3 V to 2.7 V 1.1 2.4 4.0 ns
VCC = 3.0 V to 3.6 V 1.0 2.2 3.5 ns
Tamb = 25 C; CL = 10 pF
tpd propagation delay A, B to Y; see Figure 7 [2]
VCC = 0.8 V - 20.6 - ns
VCC = 1.1 V to 1.3 V 2.4 6.0 12.5 ns
VCC = 1.4 V to 1.6 V 2.0 4.3 7.6 ns
VCC = 1.65 V to 1.95 V 1.7 3.6 6.1 ns
VCC = 2.3 V to 2.7 V 1.4 2.9 4.8 ns
VCC = 3.0 V to 3.6 V 1.3 2.7 4.2 ns
Tamb = 25 C; CL = 15 pF
tpd propagation delay A, B to Y; see Figure 7 [2]
VCC = 0.8 V - 24.1 - ns
VCC = 1.1 V to 1.3 V 3.4 6.8 14.2 ns
VCC = 1.4 V to 1.6 V 2.3 4.9 8.6 ns
VCC = 1.65 V to 1.95 V 1.9 4.0 6.9 ns
VCC = 2.3 V to 2.7 V 1.7 3.4 5.5 ns
VCC = 3.0 V to 3.6 V 1.5 3.1 4.8 ns
Tamb = 25 C; CL = 30 pF
tpd propagation delay A, B to Y; see Figure 7 [2]
VCC = 0.8 V - 34.4 - ns
VCC = 1.1 V to 1.3 V 4.6 9.1 19.4 ns
VCC = 1.4 V to 1.6 V 3.4 6.4 11.5 ns
VCC = 1.65 V to 1.95 V 2.6 5.3 9.1 ns
VCC = 2.3 V to 2.7 V 2.3 4.5 7.2 ns
VCC = 3.0 V to 3.6 V 2.2 4.2 6.2 ns
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 9 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
[1] All typical values are measured at nominal VCC.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of the outputs.
Tamb = 25 C
CPD power dissipation capacitance f = 1 MHz; VI= GND to VCC [3]
VCC = 0.8 V - 2.5 - pF
VCC = 1.1 V to 1.3 V - 2.7 - pF
VCC = 1.4 V to 1.6 V - 2.8 - pF
VCC = 1.65 V to 1.95 V - 2.9 - pF
VCC = 2.3 V to 2.7 V - 3.5 - pF
VCC = 3.0 V to 3.6 V - 4.0 - pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8
Symbol Parameter Conditions Min Typ [1] Max Unit
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Max Min Max
CL = 5 pF
tpd propagation delay A, B to Y; see Figure 7 [1]
VCC = 1.1 V to 1.3 V 2.1 11.7 2.1 12.9 ns
VCC = 1.4 V to 1.6 V 1.5 7.5 1.5 8.3 ns
VCC = 1.65 V to 1.95 V 1.3 6.1 1.3 6.7 ns
VCC = 2.3 V to 2.7 V 1.0 4.8 1.0 5.3 ns
VCC = 3.0 V to 3.6 V 0.9 4.3 0.9 4.8 ns
CL = 10 pF
tpd propagation delay A, B to Y; see Figure 7 [1]
VCC = 1.1 V to 1.3 V 2.2 13.6 2.2 15.0 ns
VCC = 1.4 V to 1.6 V 1.8 8.9 1.8 9.8 ns
VCC = 1.65 V to 1.95 V 1.6 7.2 1.6 7.9 ns
VCC = 2.3 V to 2.7 V 1.3 5.7 1.3 6.3 ns
VCC = 3.0 V to 3.6 V 1.2 4.7 1.2 5.2 ns
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 10 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
[1] tpd is the same as tPLH and tPHL.
12. Waveforms
CL = 15 pF
tpd propagation delay A, B to Y; see Figure 7 [1]
VCC = 1.1 V to 1.3 V 3.1 15.7 3.1 17.3 ns
VCC = 1.4 V to 1.6 V 2.1 10.1 2.1 11.2 ns
VCC = 1.65 V to 1.95 V 1.8 8.2 1.8 9.0 ns
VCC = 2.3 V to 2.7 V 1.6 6.5 1.6 7.2 ns
VCC = 3.0 V to 3.6 V 1.5 5.9 1.5 6.5 ns
CL = 30 pF
tpd propagation delay A, B to Y; see Figure 7 [1]
VCC = 1.1 V to 1.3 V 4.1 21.8 4.1 24.0 ns
VCC = 1.4 V to 1.6 V 2.9 13.6 2.9 15.0 ns
VCC = 1.65 V to 1.95 V 2.4 10.9 2.4 12.1 ns
VCC = 2.3 V to 2.7 V 2.2 8.6 2.2 9.5 ns
VCC = 3.0 V to 3.6 V 2.1 7.5 2.1 8.3 ns
Table 9. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Max Min Max
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig 7. The data input (A or B) to output (Y) propagation delays
mna614
tPHL tPLH
VM
VM
A, B input
Y output
GND
VI
VOH
VOL
Table 10. Measurement points
Supply voltage Output Input
VCC VMVMVItr = tf
0.8 V to 3.6 V 0.5 VCC 0.5 VCC VCC 3.0 ns
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Product data sheet Rev. 4 — 15 November 2011 11 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
[1] For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M.
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8. Test circuit for measuring switching times
001aac521
DUT
RT
VIVO
V
EXT
V
CC
RL
5 kΩ
CL
G
Table 11. Test data
Supply voltage Load VEXT
VCC CLRL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ
0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 Mopen GND 2 VCC
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Product data sheet Rev. 4 — 15 November 2011 12 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
13. Package outline
Fig 9. Package outline SOT353-1 (TSSOP5)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(1) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.1
01.0
0.8 0.30
0.15 0.25
0.08 2.25
1.85 1.35
1.15 0.65
e1
1.3 2.25
2.0 0.60
0.15 7°
0°
0.1 0.10.30.425
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.46
0.21
SOT353-1 MO-203 SC-88A 00-09-01
03-02-19
wM
bp
D
Z
e
e1
0.15
13
54
θ
A
A2
A1
Lp
(A3)
detail X
L
HE
E
c
vMA
X
A
y
1.5 3 mm0
scale
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1
1.1
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Product data sheet Rev. 4 — 15 November 2011 13 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
Fig 10. Package outline SOT886 (XSON6)
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 14 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
Fig 11. Package outline SOT891 (XSON6)
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 15 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
Fig 12. Package outline SOT1115 (XSON6)
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 16 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
Fig 13. Package outline SOT1202 (XSON6)
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Product data sheet Rev. 4 — 15 November 2011 17 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
14. Abbreviations
15. Revision history
Table 12. Abbreviations
Acronym Description
CDM Charged De vice Model
DUT Device Under Test
ESD ElectroSt atic Discharge
HBM Human Body Model
MM Machine Model
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74AUP1G08 v.4 20111115 Product data sheet - 74AUP1G08 v.3
Modifications: •Legal pages updated.
74AUP1G08 v.3 20101007 Product dat a sheet - 74AUP1G08 v.2
74AUP1G08 v.2 20060629 Product dat a sheet - 74AUP1G08 v.1
74AUP1G08 v.1 20050720 Product dat a sheet - -
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 18 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liabili ty towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-crit ical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Te rms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the prod uct specification.
74AUP1G08 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 15 November 2011 19 of 20
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims result ing from customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74AUP1G08
Low-power 2-input AND gate
© NXP B.V. 2011. All rig h ts reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of rele ase: 15 November 2011
Document identifier: 74AUP1G08
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
17 Contact information. . . . . . . . . . . . . . . . . . . . . 19
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20