ANALOG DEVICES INC ANALOG DEVICES 42E D Ml 0816800 0028797 0 MMANA ~ Dual 8-Bit Buffered Multiplying CMOS D/A Converter 51-09-08 PM-T528 FEATURES On-Chip Latches For Both DACs +5V To +15V Single Supply Operation DACs Matched To 1% Four-Quadrant Multiplication TTL/CMOS Compatible 8-Bit Endpoint Linearity (+1/2 LSB) Low Power Consumption Microprocessor Compatible Improved ESD Resistance Automatically insertable Cerdip and Plastic Packages Available in Surface Mount SO, PLCC and LCC Packages Available In Die Form e e e e e e Full Temperature Operation e e e e APPLICATIONS Digital Gain/Attenuation Control Digital Control Of Filter Parameters Digitally-Controlled Audio Circults @ X-Y Graphics Digital/Synchro Conversion Robotics {deal For Battery-Operated Equipment CROSS REFERENCE TEMPERATURE PMI ADI RANGE PM7528AR AD7528UD PM7528BR AD7528TD MIL PM7528BR AD7528SD PM7528ER AD7528CQ PM7528FR AD75288Q IND PM7528FR AD7528AQ PM7528GP PM7528GP PM7528FP AD7528LN COM PM7528FPC AD7528KP FUNCTIONAL DIAGRAM O80 DATA INPUTS oa7 OAC AT DAC S cs PM-7528 CONTROL LOGIC Vrer8 ORDERING INFORMATION! ; : PACKAGE EXTENDED MILITARY* INDUSTRIAL COMMERCIAL RELATIVE GAIN TEMPERATURE TEMPERATURE TEMPERATURE ACCURACY ERROR -S5CTO +125C -40CTO+85C 0C TO 470C #1/2LSB +1LSB PM7528AR PM7528ER PM7528GP 21/2LSB {LSB PM7528ARC/aa3 ~ - #1/2 LSB #2LSB PM7528BR PM7528FR - 21/2LSB s2LSB PM7528BRC/e83 PM7528FP - 21/2 LSB #2LSB - PM7528FPC ~ 21/2 LSB #2LSB - PM7528FS - * Fordevices processed n total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet. t Burn-in is available on cial and { tal temp @ range parts In CerDIP, plastic DIP, and TO-can packages. GENERAL DESCRIPTION The PM-7528 contains two 8-bit multiplying digital-to-analog converters. Excellent DAC-to-DAC matching and tracking results from monolithic construction. The PM-7528 consists of two thin-film R-2R resistor-ladder networks, tracking span re- sistors, two data latches, one input buffer, and control logic. Operation from a 5 to. 15 volt single power supply dissipates only 20mW of power ina space saving 20-pin 0.3 wide DIP. The PM-7528 features circuitry designed to protect against damage from electrostatic discharges. Digital input data is directed into one of the DAC data latches determined by the DAC sefection control line DAC A/DAC B, The 8-bit wide input data path provides TTL/CMOS compatibliity. The data load cycle is similar to the write cycle of a random access memory. The PM-7528 is bus compatible with most 8-bit microprocessors, including the 6800, 8080, 8085, and Z80. PIN CONNECTIONS 20-PIN EPOXY DIP (P-Suftix) 20-PIN HERMETIC DIP (R-Suffix) 20-PIN SOL (S-Sulfix) PLCC PACKAGE (PC-Suffix) LCC PACKAGE (RC-Suffix) REV. A DIGITAL-TO-ANALOG CONVERTERS 2-423ANALOG DEVICES INC PM-7528 ABSOLUTE MAXIMUM RATINGS (T,=+25C, unless otherwise noted) Vpp 19 AGND OV, #17V 3 t0 DGND wns OV, 417V A2RID to DAND vas OV, Vow Digital Input Voitage to DGND .. -0. 3V, +15V Voiy2, Voi 2910 AGND .. 0.3, +15V VoecA, Voce B to AGND .. Vara: Vaeg8 to AGND Operating Temperature Range AR, ARC, BR,BRC Versions..... ER, FR, FP, FPC, FS Versions GP Version cesses tnoanees Junction Temperature . Storage Temperature Lead Temperature (Soldering, 60 ec) 4 Yee D MM 0816800 0028794 2 MB ANA T-51-09-08 PACKAGE TYPE HN {Nofe 1} %F UNITS 20-Pin Hermetic DIP (R) 80 15 "CW 20-Pin Plastic DIP (P) 74 92 cw 20-Gontact LCC (RC) _76 36 Cw 20-Pin SO (8) 89 27 CW 20-Contact PLCC (PC) 9a 38 "ow NOTE: 1. @, is spacifiad for worst case mounting conditions, Le., Ba Is specified for device in socket for TO, CerDIP, P-DIP, and LCG packages. @,, is specified far device soldered to printed circuit board for SO and FLCC packages. CAUTION: 1. Do not apply voltages higher than V, , or fess than GND potential on any ter- minal except Va REF 2. The digital contro! inputs are zener-protected; however, permanent damage May occur on unprotected units from high-energy electrostatic fields. Keep units In conductive foam at all times until ready to use. 3. Donotinsert this device into powered sockets; remove power before insertion or removal, . Use proper antistatic handling procedures. 5. Stresses above those listed under Absolute Maximum Ratings" may cause permanent damage to the device. a ELECTRICAL CHARACTERISTICS at V9 = +5V or +15V, VageA = Vag, 8 =+10V, OUT A= OUT B = OV; Ty=-55C to +125C apply for PM-7528AR/ARC/BR/BRC; Tes PM7528GP, unless otherwise noted, 40C to +85C apply for PM-7528ER/FA/FP/FPC/FS; Ty = 0C o +70C apply for PM-7528 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY (Note 1) Resolution N 8 - ad Bits Relative Accuracy (Note 2) NL - _ 21/2 LSB Differential Nonlinearity (Note 3) ONL - _ #1 LSB PM7528A/E/G _ = HH = 425 Ta= 425C PM7528B/F - - 2 Full Scale Gain Error G Von = +6V PM7528A/E/G - =_ 3 LsB {Note 4) FSE Ta = Full Temp. Range PM7528B/F - +4 Vpop = +15V PM7528A/E/G - - #1 T, = Full Temp. Range PM7528B/F _~ _ +3 Gain Temperature : Coefficient Vop = +5V - +0.007 (&Gain/ Temperature) TOGrs Vop = +15V _ +0,0035 **C (Notes 4, 10) . Ty = +25C ~ 5 +50 Output Leakage Current Vop = +5V +400 Out A (Pin 2)/Out B (Pin 20) hka Ta = Full Temp. Range nA Note 5: (Note 5) Voo = +15V _ 4208 Ta = Full Temp. Range Input Resistance (Vege A. Var 8) Rarer 8 - 15 kn (Note 6) AN, Var A/Vaer 8 AVper A,B _ O41 + % (Input Resistance Match) 2-424 DIGITAL-TO-ANALOG CONVERTERS REV. AANALOG DEVICES INC a A Hee D MM 0816400 0008799 4 MANA T-51-09-08 PM-7528 ELECTRICAL CHARACTERISTICS at V,,, = +5V or +15V, VaccA = VpepB =+10V, OUT A = OUT B = OV; T,= 55C to +125C apply for PM-7528AR/ARC/BR/BRC; T, = 40C to +85C apply for PM-7528ER/FR/FP/FPCIFS; T, = 0C to +70C apply for PM7528GP, unless otherwise noted. Continued PM-7528 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (Note 9) Digital Input High Vy Vop = +8V 24 _ - v (Note 8) (NH Vop = +18V 13.5 _ - Digital tnput Low V Vop = +5V - - 0.8 Vv (Note 8) INL Vop = +18V - _ 16 input Current \ Ta = +25C = .001 1 A {Note 7) IN Ta = Full Temp. Range = - +10 I input Capacitance Cc 080-087 _ - 10 oF (Note 10) N WA, GS, DAG ADAG B - _ 18 P SWITCHING CHARACTERISTICS at Vpp = +5V (Notes 10, 11) Chip Setact to t Ta = +25C 200 _ =- ns Write Set-Up Time cs T, = Full Temp. Range 230 _ - Chip Select to t Ta = +25C 20 _ - ns Write Hold Time cH T, = Full Temp. Range 30 = DAC Select to t Ty = +26C 200 - - ne Write Set-Up Time as Ta = Full Temp. Range 230 ~ ~ . DAC Select to t Ta = +25C 20 - ~ ; Write Hold Time AH T, = Full Tamp. Range 30 - - " Data Valid to t Ta = +25C 110 = - ns Write Set-Up Time bs T, = Full Temp. Range 130 - - Data Valid to t 0 _ _ ns Write Hold Time BH Ta = +25C 180 - - ite Pulse Width A ; Write Pulse Wid wr Ta = Full Temp. Range 200 ~ ~ ns SWITCHING CHARACTERISTICS at Vpp = +15V (Notes 10, 11} Chip Select to t Ty = +26C 60 - _ ris Write Set-Up Time cs Ta = Full Temp. Range 80 _ - Chip Select to t Ta = +25C 10 = _ n Write Hold Time cH Tq = Full Temp. Range 15 - - s DAC Select to t Ta = +26C 60 _ _ ns Write Set-Up Time as Tq = Full Temp. Range 80 - - DAC Select to t Ta = +26C 10 - - is Write Hold Time AH T, = Fuil Temp. Range 15 - - n Data Valid to ' Ty = 425C 50 _ - Write Set-Up Time os T, = Full Temp. Range 70 - _ ns Data Valid to t 10 Write Hold Time OH ~ ~ ns Ta = +25C 60 ad - ite Pulse Wi A Write Pulse Width twr T, = Full Temp. Range 80 _ _ ns REV. A DIGITAL-TO-ANALOG CONVERTERS 2-425ANALOG DEVICES INC PM-7528 apply for PM-7528AR/ARC/BRYBRC; T, = 40C to +85C apply for PM-7528ER/FFVFP/FPC/FS; T, = 0C to +70C apply for PM7528GP, unless otherwise noted. Continued #2 Gee D MM 0416800 O0e4600 7 MANA T-51-09-08 ELECTRICAL CHARACTERISTICS at V,,, = +5V or +15V, VageA = VageB = +10V, OUT A= OUTB = OV; Tyx-85C to +125C PM-7528 PARAMETER SYMBOL CONDITIONS MIN TYP MAX. UNITS POWER SUPPLY (Note 12) Supply Current All Digital Inputs Vig_ or Viqu _ _ 1 mA (Note 21) loo All Digital Inputs OV or Vpp - - 100 uA AC PERFORMANCE CHARACTERISTICS (Note 13) Vop = +5V Ta = +25" - - 0.02 DC Supply Rejection Ratio r = Full Temp Range _ _ 0 a (AGain/AVp9) PSAR A : , %6/% (Note 14) Vop = +18V Ta = +25C - - 0.01 Ty = Full Temp. Range - - 0,02 Vop = +5V Ta = +25C - - 220 Propagation Delay teo Ta = Full Temp. Range ~ = 270 ns (Notes 15, 16, 17) Vop = +18V Ty = +25C - - 80 Ta = Full Temp. Range _ 100 Vop = +5V Ta = +25C - - 350 Current Settling Time ty Ta = Full Temp. Range - - _ 400 ns (Notes 16, 17, 22) Vop = +15V Ta = +25C _ - 180 Ta = Full Temp. Range ~ - 200 = +25 Digital Charge Injection Q A = oy _ 160 _ (Note 18) oD nVs Voo = +15V 440 Cour A DAC Latches Loaded - - 50 Cour 8 with 00000600 -_ - 50 Output Capacitance pF CourA DAC Latches Loaded ~ - 120 Cour 8 with 11491114 - ~ 120 Vaer A to OUT A; FT, Ta = +25C - _ -70 AG Feedthrough Ta = Full Temp. Range - _ ~65 dB (Note 19) Vaer B to OUT B; FTg Ta = +25C - - ~70 T, = Full Temp. Range - - 65 2-426 DIGITAL-TO-ANALOG CONVERTERS REV. AANALOG DEVICES INC u2E D MM O8f6400 0028801 9 MANA . T-81-09-08 __ PN-7528 ELECTRICAL CHARACTERISTICS at V_, = +5V or+15V, VaecA = Vp_-B =+10V, OUTA= OUTB =0V; T,=-55C to +125C apply for PM-7528AR/ARC/BR/BRG; T, = 40C to +85C apply for PM-7528ER/FR/FP/FPCIFS; T, = 0G to +70C apply for PM7528GP, unless otherwise noted. Continued PM-7528 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AC PERFORMANCE CHARACTERISTICS (Note 13) Vaer A to OUT B; Vaer A = 20V).p Sinewave CClaa @t = 100kHz - ~77 - Vaer 8 = OV. Channel-to-Channel Ta = +25C dB Isolation (Note 20) Vagr 8 to OUT A; Vaer 8 = 20V)., Sinewave CClag @ f = 100kHz _ -77 - Vaee A = OV. Ta = +25C For Code Transition From 00000000 to 11111411. Ty = 425C Digital Crosstalk Q A Vop = +5V - 30 - nVs Vop = +15V - 60 = on . Vin = 6Vrms @ f = 1kHz. _ Harmonic Distortion THD Ty = 425C 85 dB NOTES: i. See timing diagram. says 12. See Figure 3. 1. Specifications apply to both DAC A and DAC B. . . 2. This is an endpoint linearity specification. 13. pes characteristics are for design guidance only and are not subject 3. All grades guaranteed to be monotonic over the full operating 14 AY es a +5%, temperature range. . Oe, . 4. Measured using internal Reg A and Reg B. Both DAC latches toaded with ie rom oe inte ~ cura Oo aon G = 13pF 11111111. Gain error is adjustable using circuits of Figures 5 and 6. ne WH GS = OV, DBO-DB7 ovto Ven ory, oe OV. + Sex = NPP . loaded with . . wee = 00 9F Yoo . 4 pac oaded wi 9000000 Or heninal j . _ 18. For code transition 00000000 to 11111111. \- put resistance TC = +50ppm/C; typical input resistance = 11k0. 19. Vagp A. Vaee B = 20Vp-p Sinewave @ f = 100kHz 7. Vin = OV oF Voo. _ . Vrer A, Vaer B = 20Vp-p = . 8. For all data bits OB0-DB7, WA, CS, DAC A/DAC 8. ae path OG latches oul Temp Range 9. Logi t MOS gates. Typical i + 25C) is less th op ee AY . " Fogle inputs are MOS gates. Typical input current (+25G) is leas than 22. Extrapolated: t, (1/2 LSB) =t,D + 6.27, where r= the measured first time 10. Guaranteed and not tested. REV. A constant of the final RC decay, DIGITAL-TO-ANALOG CONVERTERS 2-427ANALOG DEVICES INC PM-7528 DICE CHARACTERISTICS a A W2E D MM O8%ba00 d0c40c GO MANA T-51-09-08 4. ANALOG GROUND (AGND) 2. OUTPUT A (OUT A) 3. DAC A FEEDBACK RESISTOR (A;gA) 4, DAC A REFERENCE INPUT (VperA) . DIGITAL GROUND (DGNO) 6. DIGITAL SELECTION (DAC A/DAC B) 7. DIGITAL INPUT 0B7 (MSB) 8 DIGITAL INPUT D086 9. DIGITAL INPUT OB5 10. DIGITAL INPUT DB4 DIE SIZE 0.086 x 0.092 Inch, 7,192 sq. mils (2.184 < 2.337 mm, 5.105 sq. mm) 11. DIGITAL INPUT 083 12, DIGITAL INPUT DB2 - 1. DIGITAL INPUT DBi 14. DIGITAL INPUT DBO (LS8) 15, CHIP SELECT (C8) 16. WRITE (WR) 1% POSITIVE POWER SUPPLY (pp) 18, DAC 8 REFERENCE INPUT (VaceB) 19, DAC B FEEDBACK RESISTOR (Rr38) 20. OUTPUT B (OUT B) WAFER TEST LIMITS at Vpp=+5V or + 15V, VaerA = Vaerp B= +10V, OUT A=OUT B= OV; Ta= 25C, unless otherwise noted. PM-7528G PARAMETER SYMBOL CONDITIONS LIMIT UNITS Relative Accuracy NL Endpoint Linearity Error +% LSB MAX Differential Nonlinearity DNL af : LSB MAX Gain Error Gese DAC Latches Loaded with 11111111 2 LSB MAX DAC Latches Loaded with 00000000 M Output Leakage like Pad 2 and 20 +50 nA MAX KQMIN/ input Resistance Pre Pad 4 and 18 B/S KOMAX VaerA/VaerB Input Resistance Match VaerA. B # % MAX Digital Input y, Vpp = 5V 2.4 V, High i Voo = 15V 13.5 MIN Digitat Input V, Vop = 5V 0.8 V, Low iu Vpp = 15V 15 MAX Input Current lin Vin = OV OF Vop 1 HA MAX All Digital Inputs Vig, OF Vines 1 Supply Current 'oo All Digital inputs OV or Vpp 0.1 mA MAX OC Supply Rejection PSRR Vpp = 8% (AGain/ Vpp) 0.02 %/% MAX NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield toss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing. TYPICAL ELECTRICAL CHARACTERISTICS at Vpp = +5V or +18V, Vper A = Vrge B = +10V, OUT A = OUT B = OV; Ta = 25C, unless otherwise noted. (Note 13) PM-7528G PARAMETER SYMBOL CONDITIONS TYPICAL UNITS Digital Input Capacitance Gn 6 pF SourA 22 NF our DAC Latches Loaded with 00000000 29 pr Output Capacitance CAA 40 cous DAG Latches Loaded with 11114111 40 pF Propagation Delay t Vop = 15V 70 ns (Notes 15, 16, 17) pO Vop = 8V 150 2-428 DIGITAL-TO-ANALOG CONVERTERS REV. AANALOG DEVICES INC -4eE D) oF 0616400 00284603 MANA PM-7528 TYPICAL PERFORMANCE CHARACTERISTICS TOTAL UNADJUSTED ERROR vs DIGITAL INPUT RELATIVE ACCURACY vs REFERENCE VOLTAGE v2 Ta = 25C Yop? Ta 228C Wa o Wa ~4 FOR THIS a RELATIVE ACCURACY (LSB) V4 TOTAL UNADJUSTED ERROR (LS8) ~14 Is o 64 U2 128 192 256 10 -@ -6 -4 -2 0 2 4 6 8 T-51-09-08 FULL-SCALE GAIN ERROR vs TEMPERATURE 2 3. & 0.08 z 3 d 0.04 8 3 0,02 10 in ~80 -25 0 25 50 78 100 128 TEMPERATURE (Cy FEEDTHROUGH vs FREQUENCY =6 Vas -20 FR, = 1000 FEEDTHROUGH (48) 120 104 1k 10k 100k FREQUENCY {Hz} 1M TEST CIRCUIT FOR GAIN vs FREQUENCY DIGITAL CODE REFERENCE VOLTAGE (VOLTS) GAIN AND PHASE SHIFT OUTPUT vs FREQUENCY LEAKAGE CURRENT WITH RESISTIVE LOAD vs TEMPERATURE AND OP-01 AMPLIFIER 1000 ee 4 2 z z a 3 2 100 x a 2 5 o g g a UB -0 -25 0 2 s0 76 #100) (126 1k 10k 100K 1 TEMPERATURE (C} FREQUENCY {Hz) GAIN (Vourt/VacriN) vs FREQUENCY ALL BITS ON 0 ~24 s -48 Vagsitt z ; < o -n 96 120 1 10 100 1000 10000 FREQUENCY (kHz) REV. A DIGITAL-TO-ANALOG CONVERTERS 2-429ANALOG DEVICES INC 4eE D MM 0816400 0028404 4. mM ANA PM-7528 TYPICAL PERFORMANCE CHARACTERISTICS T-51-09-08 TOTAL HARMONIC DISTORTION ANALOG CROSSTALK POWER SUPPLY REJECTION va FREQUENCY vs FREQUENCY vs TEMPERATURE 0 0.0T =6Vams Yout v; or 6, REF > Yam 20 waste MS op RATIO = 0.c0t -80 0.0001 TOTAL HARMONIC DISTORTION (dB} , & ANALOG CROSSTALK (dB} & POWER SUPPLY RESECTION (%/%) Yoo 7 14 TO -120 -120 0.00001 . o1 1 10 100 tk 10k 100k 1M 10M 15-50-25 0 25 0 78 100 125 FREQUENCY (kHa) FREQUENCY (Hz} ; TEMPERATURE [C} SUPPLY CURRENT vs TEMPERATURE Qt SUPPLY CURRENT (mA} Vinh 2 13.5 0.01 -76 -80 --250 0 0 6-25 O75 100s 125 TEMPERATURE (CI VOLTAGE SWITCHING MODE CHARACTERISTICS RELATIVE ACCURACY GAIN AND PHASE VOLTAGE SWITCHING vs REFERENCE VOLTAGE vs FREQUENCY MODE TEST CIRCUIT 3 T : Ty 2 25C : 2 ; AT EACH REFERENCE VOLTAGE, ALL = 4 3 DIGITAL CODES WERE TESTED, THEN a & THE MAXIMUM ERROR IS PLOTTED HERE. 2 ql =z g 6 MAXIMUM POSITIVE ERAOA yg a = w g 2p | Yop * 154 4 < uw 2 MAXIMUM 2 -2 Ao NEGATIVE ERROR a VRertiny * }00Vans * 2Vp Vpp 2 15V - Yoo * rai = tintin 43 | GAIN (FREQ) * Voyr AlVper 4 {IN} 0 2 4 6 a 10 1 10 100 1000 10000 REFERENCE VOLTAGE (VOLTSt FAEQUENCY {kHe} 2-430 DIGITAL-TO-ANALOG CONVERTERS REV. AANALOG DEVICES INC 2 | O41b609 A0eaads & MANA 1-61 -09-08 PM-7508 PARAMETER DEFINITIONS RELATIVE ACCURACY Relative accuracy, or endpoint nonlinearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale, and is normally expressed in LSB's or as a percentage of full scale reading. DIFFERENTIAL NONLINEARITY Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of +1 LSB maximum over the operating temperature range ensures monotonicity. GAIN ERROR Gain error, or full-scale error, is a measure of the output error between an Ideal DAC and the actual device output. The Ideal full-scale output is Vaer minus 1 LSB. Gain error of both DAC's in the PM-7528 is adjustable to zero with external resistance. OUTPUT CAPACITANCE Capacitance from OUT A or OUT B to AGND. DIGITAL CHARGE INJECTION The amount of charge Injected from the digital inputs to the analog output when the inputs change states. This is normally specified as the area of the glitch in either pAsecs or nVsecs, depending upon whether the glitch is measured as a current or voltage signal. Digital charge Injection is measured with Vper A, Vrer B = AGND. PROPAGATION DELAY This Is a measure of the Internal delays of the circuit. It is defined as the time from a digital input change to the analog output current reaching 90% of its final value. CHANNEL-TO-CHANNEL ISOLATION The portion of input signal from one DACs reference input which appears at the output of the other DAC, expressed as a ratio in dB. DIGITAL CROSSTALK The glitch energy transferred to the output of one converter, due to a change in digital input code to the other converter, specified in nVsec. WRITE CYCLE TIMING DIAGRAM AC FEEDTHROUGH AC signal due to capacitive coupling from Ver to output with all switches off. INTERFACE LOGIC INFORMATION DAC SELECTION : / Both DAC latches share a common 8-bit input port. The control input DAC A/DAC B selects which DAC can accept data from the input port. MODE SELECTION The inputs GS and WR controf the. operating mode of the selected DAC. See Mode Selection Table below. WRITE MODE When GS and WR are both low, the selected DAC is in the write mode. The Input data latches of the selected DAC are trans- parent and its analog output responds to the data on the data bit lines DBO-DB7. HOLD MODE The selected DAC latch retains the data which was present on the data lines just prior to CS or WRassuming a high state. Both analog outputs remain at the values corresponding to the data in their respective latches. MODE SELECTION TABLE DACA/DACB GS WR DACA __sCODACB L L L_WRITE HOLD H L L_-_ HOLD _ WRITE x H x HOLD HOLD x x H HOLD HOLD L = Low State H = High State X= Don't Care - CIRCUIT INFORMATIOND/A SECTION The PM-7528 contains two identical 8-bit multiplying digital-to- analog converters, DAC A and DAC B. Each DAC Includes a stable thin-film R-2R resistor ladder and eight NMOS current steering switches. Figure 1 shows a simplified equivalent circuit l i DAC Ayoac NOTES: 1. ALL INPUT SIGNAL RISE ANO FALL WRITE TIMES MEASURED FROM 10% TO S0% OF Vop- QD Vop 7 #5V. ty = te = 20ns; V Vo = +18V, t, = ty 40ns, Vin oo 2. TIMING MEASUREMENT REFERENCE DATA IN (080-087) DATA IN STABLE Vin? Vie Mu Lever 1s HHL - Q REV. A DIGITAL-TO-ANALOG CONVERTERS 2-431ANALOG DEVICES INC PM-7528 of either DAC. The inverted R-2R ladder takes a voltage or current reference and divides it in a binary manner among the sight current steering switches. The number of switches selected to the output (OUT) add their currents together forming an analog output current representation of the switch selection. The DAC OUT and analog ground (AGND) should be maintained at the same voltage for proper operation. The internal feedback resistor (Reg) has anormally closed switch in series as shown in Figure 1. This switch improves linearity performance over temperature and power supply rejection; however when the circuit is not powered up the switch assumes an open state. FIGURE 1: Simplified functional circuit for DAC A or DAC B. aR a Rep 1 0o0uT AGND DAC DATA LATCHES AND DRIVERS EQUIVALENT CIRCUIT ANALYSIS The equivalent circuit of DAC A shown in Figure 2 is similar to DAC B. DAC A and DAC B both share the analog ground pin 1 (AGND). With all digital inputs high, the reference current flows to OUT A. A small leakage current (lLeaxaGge) flows across internal junctions, doubling every 10C. The R-2R ladder termination resistor generates a constant 1/256 current which is 1 LSB of the reference current (IRer). Cour is the paraliel combination of the NMOS current steering- switches. The value of Cour depends on the number of switches connected to the output. The range of Coyr is 50pF to 120pF maximum. The equivalent output resistance Ro varies with Input code from 0.8R to 3R, where R is the nominal ladder resistor of the R-2R ladder. FIGURE 2: PM-7528 DAC A equivatent circuit, All digital inputs high. Ag = 11k eo 42E D MM 0416800 0026606 8 MANA T-51-09. ~08 CIRCUIT INFORMATIONDIGITAL SECTION The digital inputs provide TTL Input compatibility (Viv = 2.4, Vine = 0.8V) when the PM-7528 operates. with Vpp of +5V. The digital inputs effect the amount of quiescent supply current as shown in Figure 3. Peak supply current occurs as the digital Input (Vin) passes through the transition voltage. Maintaining the digital input voltages as close as possible to the supplies (Vop and DGND) minimizes. supply current consumption. When operating the PM-7528 from CMOS logic the digital inputs are driven very close to the supply rails, minimizing power consumption. Digital input protection from electrostatic discharge and electro- static buildup occurs in the input network shown in Figure 4, FIGURE 3: Typical plots of supply current, Ipp vs logic input voltage (Viy), for Vop = +5V, +10V, and +15V. 30 = ALL DIGITAL < = 5 20 wW < = 2 Qo 5 a 5 a 10 | 3 2 a q 0 5 10 8 Vin ~ DIGITAL INPUT (VOLTS) BURN-IN CIRCUIT 3 3! T T! 20 18 Sk 100Ks2 b j2 3 C18 A PARALLEL COMBINATION OF 4.7nF AND 0.01uF CAPACITORS ON EVERY TENTH SOCKET. 2-432 DIGITAL-TO-ANALOG CONVERTERS REV. AANALOG DEVICES INC 2 4eE D MM 0416400 0026607 T MANA 1-51-09-08 _pML7598 drive-circuitry, is shown. FIGURE 4: Simplified equivalent gate-input protection circuit. One of eight current switches, and its associated internal CMOS- DIGITAL INPUT 4h -| E TO CURRENT LADDER t J I +-| 5 I QUTA = AGND DGNOD 4E AH 2-3. APPLICATIONS INFORMATION The most common application of this DAC is voltage output operation. Unipolar output operation provides a 0 to 10 volt output swing when connected, as shown In Figure 5. The maximum output voltage polarity is the inverse of the input reference voltage, since the op amp inverts the Input currents. The transfer equation for unipolar operation Is Voyy = -Vin X D/256, where D is the decimal value of the data bit inputs DBO thru DB7 and Vin Is the reference input voltage. The transfer equation highlights another popular application of CMOS DACs, multiplication. The output voltage Is the product of the reference voltage and the digita! input code. The reference Input voltage can be any value in the range of 25 volts for both DC or AC signals. The circuit in Figure performs two-quadrant multiplication. Table 1 provides example analog outputs for the given digital Input codes. For bipolar output operation connect the PM-7528 as shown in Figure 6. This circuit configuration provides an offset current, derived from the reference, to enable the output op amp to swing in both polarities. The digital input coding becomes offset binary. Table 2 provides some example analog outputs for various digital Inputs (D). The transfer equation for bipolar operationis Vour = Vin X (D/128 - 1), where Dis the decimal value of the data bit Inputs OB0 thru DBZ. This circuit provides full four-quadrant multiplication able to accept both polarities on ail inputs as well as the circuit output. FIGURE 5: Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication). See Table 1. DATA INPUTS (2) INPUT BUFFER DAC : CONTROL Loaic NOTES: AI, RZ AND f3, R4 USED ONLY If GAIN ADJUSTMENT [S REQUIRED. SEE TABLE FOR RECOMMENDED VALUES, MAKE GAIN AOJUSTMENT WITH DIGITAL INPUT OF 255, WHEN USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION. Vind (210V} 7 C1, C2 PHASE COMPENSATION (10pF-159F) IS REQUIRED Vout A Vour 8 R3) ee RECOMMENDED TRIM RESISTOR VALUES vs GRADE TRIM RESISTOR HP/ER/BR GP/ER/AR AI. 6000 2000 R2, R4 1602 622 REV. A DIGITAL-TO-ANALOG CONVERTERS 2-433ANALOG DEVICES INC PM-7528 TABLE 1: Unipolar Binary Code Table. See Figure 5. 4Y2E D Ml Oa) aw od 6400 0028808 L MMANA T~51-09.08 TABLE 2: Bipolar (Offset Binary) Code Table. See Figure 6. DAC LATCH CONTENTS DAC LATCH CONTENTS ANALOG OUTPUT ANALOG OUTPUT MSB LSB (DAC A or DAC B) MSB LSB (DAG A or DAC B) 4444404 vw (33s ) 41444441 ww (2 10000001 Vin ( 336 10000001 wv ( 325 ) 10000000 Viv ( 335 ) = 10000000 0 7 o1itittt vw ( 336 o1ittt44 vw (3) 00000001 vw ( 355 ) 00000001 | Vn ( 338 ) 00000000 Vin ( 53g )=9 00000000 viv ( 35 ) NOTE: 1 LSB = (2)(Vin) = ag (Vn) NOTE: 1 LSB = (27)(Viq) = ag (Vin) FIGURE 6: Dual DAC Bipolar Operation (4 Quadrant Multiplication). See Table 2. Vina (210V) < > Von 0-4] oso] y DATA INPUT Y INPUTS Q 7 BUFFER LATCH oa7 J 6 PM-7528 ADJUST AL FOR Vout A= OV WITH CODE 10000000 IN DAC A LATCH. ADJUST AZ FOR V, > OV WITH CODE 10000000 IN OAC B LATCH. 2? MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS REG, A? ANO RQ, Ald. 3 C1, C2 PHASE COMPENSATION (10pF-169F) MAY BE REQUIRED IF AT/A3 IS A HIGH-SPEED AMPLIFIER. DAC B 0. CONTROL AGNO AGNO So -~/ 1 Loaic Ra wros 0 19, | Rea 6 Le \ 2 TT LATCH pace ) ours 5 Ag is Zast OGND ~ 38 D 10KR R AGND R102 AA NOTES: 20K * Al, 2 ANO R3, A4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. veep SEE TAGLE IN FIGURE FOR RECOMMENDED VALUES. ten Vout 5 Ska AGNES 2-434 DIGITAL-TO-ANALOG CONVERTERS REV. AANALOG DEVICES INC 42E D MM 0814800 0028809 3 MANA - APPLICATION HINTS To ensure system performance consistent with PM-7528 specifi- cations, careful attention must be given to the following points: 1. GENERAL GROUND MANAGEMENT: AC or transient voltages between the PM-7528 AGND and DGND can cause noise injection Into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal, is to tie AGND and DGND together at the PM-7528, In more complex systems where the AGND-DGND con- nection Is on the back-plane, it is recommended that diodes (1N914 or equivalent) be connected In inverse parallel between the PM-7528 AGND and OGND pins. 2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a code-dependent output resistance which in turn causes a code-dependent amplifier noise gain. The effect is a code- dependent differential nonlinearity term at the amplifier output with a maximum magnitude of 0.67 Vog (Vos is amplifier tnput-offset voltage). This differential nonlinearity term adds to the R/2R differential nonlinearity. To maintain monotonic operation, itis recommended that amplifler Vog be no greater than 10% of 1 LSB over the temperature range of interest. 3. HIGH-FREQUENCY CONSIDERATIONS: The output capacitance of a CMOS DAC works In conjunction with the amplifier feedback resistance to add a pole to the open-loop response; this can cause ringing or oscillation. Stability can be restored by adding a phase-compensation capacitor in paraitel with the feedback resistor. 4. DYNAMIC PERFORMANCE: The dynamic performance of the two DAGs In the PM-7528 will depend upon the gain and phase characteristics of the output amplifiers, together with the optimum choice of the PC board layout and decoupling components. . CIRCUIT LAYOUT SUGGESTIONS: Analog and digital ground traces should be routed between package pins to isolate the digital inputs from the analog circuitry. Analog ground traces should also be placed btween pins 17-18, 18-19, 3-4, 4-5 to minimize reference feedthrough to the output in multiplying applications. A power supply bypass capacitor (0.14F) is recommended across Vpp to DGND. SINGLE SUPPLY OPERATION, VOLTAGE SWITCHING With the PM-7528 connected in the voltage switching mode of _ Operation, Figure 7, only one power supply is necessary. There is no voltage inversion between the reference input polarity and the output in the voltage switching mode. Two characteristic curves in the typical performance character- istics section were generated using this voltage switching mode of operation. The first graph, linearity error versus input reference voitage, shows that to maintain a 1/2 LSB maximum linearity error, Vaeg should be less than 1.5 volts for Vpp=5 volts or less than 6 volts for Vpp = 15 volts. The gain-phase response graph shows a dominant pole response for single supply applications where the reference input is an AC signal. In this application the reference input should remain between 1.5 volts and ground when Vpp = 5 volts. Additionally settling time measures 400 to 500 nano seconds for a digital input change of 255 to 0 when Vop = 5V. REV. A constant output resistance (~ 11K ) independent of the digital input code. The output should be buffered with a voltage follower when driving low impedance loads. FIGURE 7: PM-7528 in Single Supply, Voltage Switching Mode 0 Your VREFUIN) 0 oToev VaerA OUTA Yoo DACA DGND IAGNO PM-7528 qt re SINGLE SUPPLY, CURRENT SWITCHING An alternate single-supply operating mode of the PM-7528 results when offsetting the analog ground. Figure 8 shows the method of connection. The advantage of this connection method is the ability to set the output voltage swing in the center of the supply voltage. This allows use of lower cost op amps that would not work in single-supply voltage-switching applications. The transfer equation in this mode of operation is; Vout(D) = 0/256 (AGND ~ Veer).-+ AGND where D is the whole number binary input A popular connection In the current-steering single-supply ~ mode consists of a 2.5 volt reference connected to AGND, the Vaer input grounded, Vpp connected to 5 volts and the external (V+) op amp tied to 12 volts. This hookup results in the: following transfer equation; Vour(D) = 2.5 (1 + D/256) where Vout (255) = 2.5 (1 + 255/256) = 5V Vout (0) = 2.5V To maintain best linearity keep AGND equal to or less than 2.5 volts when Vpp is 5 volts. . FIGURE 8: PM-7528 in Single Supply, Current-Steering Mode sv +12V oO Yoo Fre O 2.5V $ Vout s 8 Vaer PM-7528 OUT 7 = Toe VOLTAGE REFERENCE DIGITAL-TO-ANALOG CONVERTERS 2-435 T-51-09-08 PM-7528 The output terminal in the voltage switching mode has aa? ANALOG DEVICES INC 42E D MM 0816800 0028610 T, MANA PROGRAMMABLE WINDOW COMPARATOR input signal range depends on the reference and polarity, that is A programmable window-comparator in Figure 9 will determine the test input range is 0 to minus Vagr. The A and B data latches if voltage inputs applied to the DAC feedback resistors are are programmed with the upper and lower test limits. A signal within limits programmed into the PM-7528 data latches. The within the programmed limits will drive the output to logic high. FIGURE 9: Digitally Programmable Window Comparator (Upper and Lower Limit Detector). 28 eer Vee CMP-OT DATA INPUTS COMPARATOR cs PM-7528 ourur Wr OAC Ayoac 8 Vaer CMP-Ot COMPARATOR MICROPROCESSOR INTERFACE FIGURE 10: PM-7528 Dual DAC to 6800 CPU Interface. FIGURE 11: PM-7528 Dual DAC to 8085 CPU Interface. - h AQ-A15 ADORESS BUS AS-AIS: AODRESS BUS Ate av ADORE: Tt >-pale ADDRESS tp DAT AIOAC B VMA DECODE DECODE _| LOGIC oS cs L gry ee Pe 200 any PM-7528 TT M-7528 2 wa vaca wR dat MIRA [oace DBO ALE | LATCH i) a7 a212 a7 00-07 DATA BUS. ADQ-AD7 ; ADDA/DATA BUS ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY. " * ANALOG cinculTAY HAS BEEN OMITTEO FOR CLARITY. **a = DECODED 7628 ADOR ** @ = DECODED 7528 ADDR DACA A+1+2 DECODED 7828 ADDR DAC B A+#1= DECODED 7528 AODA DAC B g0us INSTRUCTION SHLD {STORE H & L DIRECT) CAN UPDATE BOTH DACS WITH DATA FROM H AND L REGISTERS. 2-436 DIGITAL-TO-ANALOG CONVERTERS REV. AANALOG DEVICES INC U2E D M@ 0816800 OO28811 1 MMANA | T-51-09-08 PM-7508 DIGITALLY CONTROLLED SIGNAL ATTENUATOR generate logarithmic attenuation, Table 4 was generated based Figure 12 shows the PM-7528 configured as a two-channel on the equation: programmable attenuator. Applications include stereo, audio, an - x Attenuation (dB), - and telephone signal!-level control applications. In order to Digital Input = 266 x exp ( 20 ) FIGURE 12: Digitally-Controlled Dual Telephone Attenuator. Yoo 17 3 | * Ea Vind & DACA PO Vou A V DATA BUS PM-7528. 087 15 . ots 18 : oWn 20 <2 0 Saga Your 7 bacB * O Vin V7 AGND 1 19 OGNO 5 TABLE 4: Attenuation vs. DAC A, DAC B Code for the Circuit of Figure 12 CODE IN CODE IN ATTN. dB DAC INPUT CODE DECIMAL ATTN. dB DAC INPUT CODE DECIMAL 0 411111111 255 8.0 01100110 | 102 0.5 11110010 242 8.5 01100000 96 1.0 11100100 228 9.0 01011011 91 1.5 11010111 215 9.5 01010110 86 2.0 11001011 203 10.0 01010001 81 2.5 11000000 192 ; 10.5 01001100 76 3.0 10110107 181 11.0 01001000 72 3.5 10101011 171 11.5 01000100 68 4.0 10100010 162 12.0 01000000 64 4.5 10011000 152 12.5 00111101 6t 5.0 10010000 144 13.0 00111001 _ 87 5.5 10001000 136 13.5 00110110 _ 64 6.0 10000000 128 14.0 00110011 51 6.5 01111001 121 14.5 00110000 | 48 7.0 01110010 114 15.0 00101110 - 46 7.5 01101100 108 15.5 0010t011~ 43 REV. A DIGITAL-TO-ANALOG CONVERTERS 2-437.