AM486DX2 - Advanced Micro Systems

Advanced

Micro

Devices

Am486 DX2 3.3-Volt Processor

High-Performance, Clock-Doubled, 32-Bit Microprocessor

DISTINCTIVE CHARACTERISTICS

Operating voltage range 3.3 V ± 0.3 V

— 66-MHz and 80-MHz operating frequencies

—Wide range of chipsets and support available

through the AMD® FusionPCSM Program

High Integration On-Chip

—8-Kbyte code and data cache

—Floating-point unit

—Paged, virtual memory management

High-Performance Design

—Frequent instructions execute in one clock

—105.6-million bytes/second burst bus at 33 MHz

—128-million bytes/second burst bus at 40 MHz

—Advanced submicron CMOS technology

—Dynamic bus sizing for 8-, 16-, and 32-bit buses

Complete 32-Bit Architecture

—Address and data buses

—All registers

—8-, 16-, and 32-bit data types

Multiprocessor Support

—Multiprocessor instructions

—Cache consistency protocols

—Support for second-level cache

Standard 168-pin PGA Package

Environmental Protection Agency's “Energy

Star” program compliant

—Energy management capability provides an

excellent base for energy-efficient design

—Works with a variety of energy-efficient,

power-managed devices

Publication# 19200 Rev: D Amendment/0

Issue Date: August 1995

GENERAL DESCRIPTION

The clock-doubled Am486DX2 processor is a high-per-

formance 486 desktop solution that provides optimal

price/performance for high-end 486 power-managed

systems. The Am486DX2 CPU offers superior local bus

graphics performance for Microsoft® Windows®.

The Am486DX2 processor operates with a 1x clock in-

put. This 1x clock simplifies system design by reducing

the clock frequency required by external devices. The

1x clock also reduces RF emission and simplifies clock

generation. The input signal is doubled internally to

achieve the maximum 2x operating frequency. The

phases of the core clock are controlled by an internal

Phase Lock Loop (PLL) circuit.

PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information is

intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

AMD

Am486DX2 Microprocessor

BLOCK DIAGRAM

Floating-

Point

Unit

Floating-

Point

File

Central and

Protection

Test Unit

Control

ROM

Instruction

Decode

Barrel Shifter

ALU

Segmentation

Unit

Descriptor

Registers

Paging Unit

Translation

Lookaside

Buffer

Limit and

Attribute

PLA

Cache Unit

8-Kbyte

Cache

Prefetcher

32-byte

Code Queue

2 x 16 bytes

Address

Drivers

Bus Control

Request

Sequencer

Write Buffers

4 x 80

Data Bus

Transceivers

Burst Bus

Control

Bus Size

Control

Cache

Control

Parity

Generation

and Control

Linear Address Bus

32-Bit Data Bus

232

128

Micro-instruction

Decoded

Instruction

Path

Code

Stream

Physical

Address

PCD, PWT

Base/

Index

Bus

Displacement Bus

Bus Interface

A31−A2,

BE3−BE0

D31−D0

ADS, W/R, D/C, M/IO,

PCD, PWT, RDY, LOCK,

PLOCK, BOFF, A20M,

BREQ, HOLD, HLDA,

RESET, INTR, NMI,

FERR, IGNNE, UP

BRDY, BLAST

BS16, BS8

KEN, FLUSH,

AHOLD, EADS

PCHK,

DP3−DP0

64-Bit Interunit Transfer Bus

Am486 CPU Pipelined 32-Bit Microarchitecture

Boundary

Scan

Control

TDI, TDO

TMS, TCK

Clock

MultiplierCLK

CLKMUL

Core

Clock

Power

Planes

VOLDET

VCC

, VSS

19200C-001

P R E L I M I N A R Y

Am486DX2 Microprocessor

AMD

ORDERING INFORMATION

Standard Products

–8080486DX2

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the elements below.

SPEED OPTION

DEVICE NUMBER/DESCRIPTION

Valid Combinations

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the local

AMD sales office to confirm availability of specific valid

combinations and to check on newly released

combinations.

PACKAGE TYPE

–66 = 66 MHz

–80 = 80 MHz

80486DX2

Am486DX2 3.3-Volt High-Performance, Clock-Doubled,

32-bit Microprocessor

A = 168-pin PGA (Pin Grid Array)

Valid Combinations

-66

-80

80486DX2A

CACHE SIZE

8 = 8 Kbytes

VOLTAGE

V = 3.3-V Core, 5-V Tolerant I/O

CACHE TYPE

T = Write-Through

V8T

ICE MICROCODE

N = No ICE Microcode

NV8T

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

CONNECTION DIAGRAMS

Am486DX2 CPU

Pin Side View

168-Pin PGA (Pin Grid Array) Package

PLOCK

INCBLAST

ADS

VCC

VSS

VCCVCCVCCVCCVCCVCC

VCC

VSSVSS VSS VSS VSS VSS

VSS

A27 A26 A23 VOLDET A14 A12 A10 A6 A4

A28 A25 A18 A15 A11 A8 A3

A31 A17 A19 A21 A24 A22 A20 A16 A13 A9 A5 A7 A2 BREQ PCHK

D0 A29 A30 HLDA

D2 D1 DP0 LOCK

D6 D7 PWT

D14 BE0

D5 D16 BE2 BE1 PCD

D3 DP2 BRDY

D12 INC

DP1 D8 D15 KEN RDY BE3

D10 HOLD

D9 D13 D17 A20M BS8 BOFF

D11 D18 CLK D27 D26 D28 D30 INC INC NC FLUSHFERR RESET BS16

D19 D21 D25 D31 INC INC CLKMUL TMS NMI TDO EADS

D20 D22 TCK D23 DP3 D24 D29 INC INC INC TDI INTR AHOLDIGNNE

2345678910 11 12 13 14 15 16 171

VSS

VCC

VSS

INC

VSS

VCC

VSS

VCC

VSS

VCCVSS

VCC VSS

VCCVSS

M/IOW/R

D/C

VCCVCC

VSS VSS VSSVCCVCC VCC

VSS VSSVSS

19200C-002

Note:

NC = No Connect. To guarantee functionality with future revisions, these pins must not be connected.

INC = Internal No Connect. No special requirements.

P R E L I M I N A R Y

Am486DX2 Microprocessor

AMD

CONNECTION DIAGRAMS

Am486DX2 CPU

Top Side View

168-Pin PGA (Pin Grid Array) Package

INC

PCHKPLOCK

BLAST

ADS

Note:

NC = No Connect. To guarantee functionality with future revisions, these pins must not be connected.

INC = Internal No Connect. No special requirements

VCCVSS

VSS

VSS VCC

VCC

VCCVCC

VSS

VSS VSS A27A26A23VOLDETA14A12

A10A6

A28A25A18A15A11A8A3

A31A17A19A21A24A22A20A16A13A9A5A7A2

D0A29A30

HLDA

VCC

VSS

D2D1DP0

LOCK

D6D7PWT

D14BE0

D5D16BE2BE1PCD

D3DP2BRDY

D12INC

DP1D8D15KENRDYBE3

D10HOLD

D9D13D17A20MBS8BOFF

D11D18CLKD27D26D28D30INCINCNCFLUSH FERRRESETBS16

D19D21D25D31INCINCCLKMULTMSNMITDOEADS

D20D22TCKD23DP3D24D29INCINCINCTDIINTRAHOLD IGNNE

234567891011121314151617 1

VSS

VCCVSS

INC

VSS

VCCVSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

M/IOW/R

D/C

VCC

VSS

VCC

VSS

19200C-003

BREQ

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

PIN DESIGNATIONS (Functional Grouping)

AddressDataControlTestINC/NCVccVss

NamePin

No.Pin

NamePin

No.Pin

NamePin

No.Pin

NamePin

No.Pin

No.

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

Q-14

R-15

S-16

Q-12

S-15

Q-13

R-13

Q-11

S-13

R-12

S-7

Q-10

S-5

R-7

Q-9

Q-3

R-5

Q-4

Q-8

Q-5

Q-7

S-3

Q-6

R-2

S-2

S-1

R-1

P-2

P-3

Q-1

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

P-1

N-2

N-1

H-2

M-3

J-2

L-2

L-3

F-2

D-1

E-3

C-1

G-3

D-2

K-3

F-3

J-3

D-3

C-2

B-1

A-1

B-2

A-2

A-4

A-6

B-6

C-7

C-6

C-8

A-8

C-9

B-8

A20M

ADS

AHOLD

BE0

BE1

BE2

BE3

BLAST

BOFF

BRDY

BREQ

BS8

BS16

CLK

CLKMUL

D/C

DP0

DP1

DP2

DP3

EADS

FERR

FLUSH

HLDA

HOLD

IGNNE

INTR

KEN

LOCK

M/IO

NMI

PCD

PCHK

PWT

PLOCK

RDY

RESET

VOLDET

W/R

D-15

S-17

A-17

K-15

J-16

J-15

F-17

R-16

D-17

H-15

Q-15

D-16

C-17

C-3

B-13

M-15

N-3

F-1

H-3

A-5

B-17

C-14

C-15

P-15

E-15

A-15

A-16

F-15

N-15

N-16

B-15

J-17

Q-17

L-15

Q-16

F-16

C-16

C-11

S-4

N-17

TCK

TDI

TDO

TMS

A-3

A-14

B-16

B-14

A-10

A-12

A-13

B-10

B-12

C-10

C-12

C-13

G-15

J-1

R-17

B-7

B-9

B-11

C-4

C-5

E-2

E-16

G-2

G-16

H-16

K-2

K-16

L-16

M-2

M-16

P-16

R-3

R-6

R-8

R-9

R-10

R-11

R-14

A-7

A-9

A-11

B-3

B-4

B-5

E-1

E-17

G-1

G-17

H-1

H-17

K-1

K-17

L-1

L-17

M-1

M-17

P-17

Q-2

R-4

S-6

S-8

S-9

S-10

S-11

S-12

S-14

P R E L I M I N A R Y

Notes:

INC = Internal No Connect (A-10, A-12, A-13, B-10, B-12, C-10, C-12, G-15, J-1, R-17).

NC = No Connect (C-13).

VOLDET is connected internally to VSS.

CLKMUL must be connected externally to VSS.

Am486DX2 Microprocessor

AMD

LOGIC SYMBOL

DP3−DP0

A31−A4

CLK

A20M

M/IO

Am486

CPU

W/R

D/C

17852B-114

LOCK

4BE3−BE0

Clock

Address Bus

Bus Cycle

Definition

Address Mask

PLOCK

BS8

BS16

ADS

READY

Bus Cycle

Control

INTR

NMI

RESET

Interrupts

PCHK

A3−A2

BRDY

BLAST

PWT

PCD

KEN

FLUSH

EADS

AHOLD

Data Parity

Data Bus

Burst

Control

Page

Cacheability

Invalidation

Cache Control/

D31−D0

TMSTDITDO

TCK

IEEE Test

Access Port

FERRIGNNE

Numeric Error

Reporting

Bus Arbitration

BREQ

HOLD

HLDA

BOFF

VOLDET

Clock Multiplier CLKMUL

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

PIN DESCRIPTIONS

The following paragraphs define the Am486DX2 CPU

pins (signals).

A31–A4/A3–A2

Address Lines (Inputs/Outputs)/(Outputs)

A31–A2, together with the byte enables BE3–BE0, de-

fine the physical area of memory or input/output space

accessed. Address lines A31−A4 are used to drive ad-

dresses into the microprocessor to perform cache line

invalidations. Input signals must meet setup and hold

times t22 and t23. A31–A2 are not driven during bus or

address hold.

A20M

Address Bit 20 Mask (Active Low; Input)

When asserted, the Am486DX2 microprocessor masks

physical address bit 20 (A20) before performing a look-

up to the internal cache or driving a memory cycle on

the bus. A20M emulates the address wraparound at

1Mbyte, which occurs on the 8086. A20M is active Low

and should be asserted only when the processor is in

Real mode. This pin is asynchronous but should meet

setup and hold times t20 and t21 for recognition in any

specific clock. For proper operation, A20M should be

sampled High at the falling edge of RESET.

ADS

Address Status (Active Low; Output)

ADS indicates that a valid bus cycle definition and ad-

dress are available on the cycle definition lines and ad-

dress bus. ADS is driven active in the same clock as the

addresses are driven. ADS is active Low and is not driv-

en during bus hold.

AHOLD

Address Hold (Active High; Input)

This request allows another bus master access to the

Am486DX2 microprocessor’s address bus for a cache

invalidation cycle. The Am486DX2 microprocessor

stops driving its address bus in the clock following

AHOLD going active. Only the address bus is floated

during address hold; the remainder of the bus remains

active. AHOLD is active High and is provided with a

small internal pull-down resistor. For proper operation,

AHOLD must meet setup and hold times t18 and t19.

BE3−BE0

Byte Enables (Active Low; Outputs)

These pins indicate active bytes during read and write

cycles. During the first cycle of a cache fill, the external

system should assume that all byte enables are active.

BE3 applies to D31–D24, BE2 applies to D23–D16, BE1

applies to D15–D8, and BE0 applies to D7–D0. BE3–

BE0 are active Low and are not driven during bus hold.

The Am486DX2 microprocessor provides four special

bus cycles to indicate that certain instructions have

been executed, or certain conditions have occurred in-

ternally. The special bus cycles (in Table 1) are defined

when the bus cycle definition pins are in the following

state: M/IO=0, D/C=0, and W/R=1. During these cycles,

the address bus is driven Low while the data bus is unde-

fined.

The external hardware must acknowledge these special

bus cycles by returning RDY and BRDY.

——————————————————————————————————————————————————————————————

BS8/BS16

Bus Size 8 (Active Low; Input)/

Bus Size 16 (Active Low; Input)

These pins cause the Am486DX2 microprocessor to run

multiple bus cycles to complete a request from devices

that cannot provide or accept 32 bits of data in a single

cycle. The bus sizing pins are sampled every clock. The

state of these pins in the clock before RDY is used by

the Am486DX2 microprocessor to determine the bus

size. These signals are active Low and are provided

with internal pull-up resistors. These inputs must satisfy

setup and hold times t14 and t15 for proper operation.

BLAST

Burst Last (Active Low; Output)

BLAST indicates that the next time BRDY is returned,

the burst bus cycle is complete. BLAST is active for both

burst and non-burst bus cycles. BLAST is active Low

and is not driven during bus hold.

BOFF

Backoff (Active Low; Input)

This input pin forces the Am486DX2 microprocessor to

float its bus in the next clock. The microprocessor floats

all pins normally floated during bus hold, but HLDA is

not asserted in response to BOFF. BOFF has higher

priority than RDY or BRDY; if both are returned in the

same clock, BOFF takes effect. The microprocessor re-

mains in bus hold until BOFF is negated. If a bus cycle

is in progress when BOFF is asserted, the cycle is re-

started. BOFF is active Low and must meet setup and

hold times t18 and t19 for proper operation.

Table 1. Special Bus Cycle Encoding

BE3BE2BE1BE0Special Bus Cycles

1110 Shutdown

1101 Flush

1011 Halt

0111 Write Back

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

BRDY

Burst Ready Input (Active Low; Input)

This input pin performs the same cycle during a burst

cycle that RDY performs during a non-burst cycle.

BRDY indicates that the external system has presented

valid data in response to a read or that the external

system has accepted data in response to write. BRDY

is ignored when the bus is idle and at the end of the first

clock in a bus cycle. BRDY is sampled in the second

and subsequent clocks of a burst cycle. The data pre-

sented on the data bus is strobed into the microproces-

sor when BRDY is sampled active. If RDY is returned

simultaneously with BRDY, BRDY is ignored and the

burst cycle is prematurely aborted. BRDY is active Low

and is provided with a small pull-up resistor. BRDY must

satisfy the setup and hold times t16 and t17.

BREQ

Internal Cycle Pending (Active High; Output)

BREQ indicates that the Am486DX2 microprocessor

has internally generated a bus request. BREQ is gen-

erated whether or not the Am486DX2 microprocessor

is driving the bus. BREQ is active High and is never

floated, except for three-state test mode (see FLUSH).

CLK

Clock (Input)

CLK is a 1x clock providing the fundamental timing for

the bus interface unit and is multiplied in accordance

with the CLKMUL pin to provide the internal frequency

for the Am486DX2 microprocessor. All external timing

parameters are specified with respect to the rising edge

of CLK.

CLKMUL

Clock Multiplier (Input)

This pin must be connected to VSS for proper operation.

D31–D0

Data Lines (Inputs/Outputs)

Lines D7–D0 define the least significant data byte and

lines D31–D24 define the most significant byte. These

signals must meet setup and hold times t22 and t23 for

proper operation on reads. The pins are driven during

the second and subsequent write cycle clocks.

D/C, M/IO, W/R

Data/Control, Memory/Input/Output, Write/Read

(Active High/Active Low; Output)

These are the primary bus definition signals. These sig-

nal are driven valid as the ADS signal is asserted. The

bus definition signals are not driven during bus hold and

follow the timing of the address bus (see Table 2).

The D/C bus cycle definition pin distinguishes memory

and I/O data cycles (D) from the control cycles (C): in-

terrupt acknowledge, halt, and instruction fetching.

The M/IO bus cycle definition pin distinguishes memory

cycles (M) from input/output cycles (IO).

The W/R bus definition pin distinguishes write cycles

from read cycles.

——————————————————————————————————————————————————————————————

Table 2. Bus Cycle Definition

——————————————————————————————————————————————————————————————

DP3–DP0

Data Parity (Active High; Inputs/Outputs)

Data parity is generated on all write data cycles using

the same timing as the data lines. Even parity informa-

tion must be driven back into the microprocessor on the

data parity pins with the same timing as read informa-

tion. This process ensures that the correct parity check

status is indicated. The signals read on these pins do

not affect program execution. Input signals must meet

setup and hold times t22 and t23. DP3–DP0 should be

connected to VCC through a pull-up resistor in systems

not using parity. DP3–DP0 are active High and are driv-

en during the second and subsequent clocks of write

cycles.

EADS

Valid External Address (Active Low; Input)

This pin indicates a valid external address has been

driven onto the Am486DX2 microprocessor address

pins. This address is used to perform an internal cache

invalidation cycle. EADS is active Low and is provided

with an internal pull-up resistor. EADS must satisfy set-

up and hold times t12 and t13, for proper operation.

FERR

Floating-Point Error (Active Low; Output)

Driven active when a floating-point error occurs. FERR

is similar to the ERROR pin on a 387 math coprocessor.

FERR is included for compatibility with systems using

DOS-type floating-point error reporting. FERR is active

Low, and is not floated during bus hold, except during

three-state test mode (see FLUSH).

FLUSH

Cache Flush (Active Low; Input)

FLUSH forces the Am486DX2 microprocessor to flush

its entire internal cache. FLUSH is active Low and need

only be asserted for one clock. FLUSH is asynchronous

but setup and hold times t20 and t21must be met for

M/IOD/CW/RBus Cycle Initiated

Interrupt Acknowledge

Halt/Special Cycle

I/O Read

I/O Write

Code Read

Reserved

Memory Read

Memory Write

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

recognition in any specific clock. FLUSH being sampled

Low in the clock before the falling edge of RESET caus-

es the Am486DX2 microprocessor to enter the

three-state test mode.

HLDA

Hold Acknowledge (Active High; Output)

HLDA goes active in response to a hold request pre-

sented on the HOLD pin. HLDA indicates that the

Am486DX2 microprocessor has given the bus to anoth-

er local bus master. HLDA is driven active in the same

clock that the Am486DX2 microprocessor floats its bus.

HLDA is driven inactive when leaving bus hold. HLDA

is active High and remains driven during bus hold. HLDA

is never floated except during three-state test mode

(see FLUSH).

HOLD

Bus Hold Request (Active High; Input)

This input pin allows another bus master complete con-

trol of the Am486DX2 microprocessor bus. In response

to HOLD going active, the Am486DX2 microprocessor

floats most of its output and input/output pins. HLDA is

asserted after completing the current bus cycle, burst

cycle, or sequence of locked cycles. The Am486DX2

microprocessor remains in this state until HOLD is deas-

serted. HOLD is active High and is not provided with an

internal pull-down resistor. HOLD must satisfy setup

and hold times t18 and t19for proper operation.

IGNNE

Ignore Numeric Error (Active Low; Input)

When this pin is asserted, the Am486DX2 microproces-

sor will ignore a numeric error and continue executing

non-control floating-point instructions. When IGNNE is

deasserted, the Am486DX2 microprocessor will freeze

on a non-control floating-point instruction if a previous

floating-point instruction caused an error. IGNNE has

no effect when the NE bit in Control Register 0 is set.

IGNNE is active Low and is provided with a small inter-

nal pull-up resistor. IGNNE is asynchronous but must

meet setup and hold times t20 and t21 to ensure recog-

nition in any specific clock.

INTR

Maskable Interrupt (Active High; Input)

INTR indicates an external interrupt has been generat-

ed. If the internal interrupt flag is set in EFLAGS, active

interrupt processing is initiated. The Am486DX2 micro-

processor generates two locked interrupt acknowledge

bus cycles in response to the INTR pin going active.

INTR must remain active until the interrupt acknowledg-

es have been performed. This ensures that the interrupt

is recognized. INTR is active High and is not provided

with an internal pull-down resistor. INTR is asynchro-

nous, but must meet setup and hold times t20 and t21

for recognition in any specific clock.

KEN

Cache Enable (Active Low; Input)

KEN is used to determine whether the current cycle is

cacheable. When the Am486DX2 microprocessor gen-

erates a cacheable cycle and KEN is active, the cycle

becomes a cache line fill cycle. Returning KEN active

one clock before RDY during the last read in the cache

line fill causes the line to be placed in the on-chip cache.

KEN is active Low and is provided with a small internal

pull-up resistor. KEN must satisfy setup and hold times

t14 and t15 for proper operation.

LOCK

Bus Lock (Active Low; Output)

LOCK indicates the current bus cycle is locked. The

Am486DX2 microprocessor does not allow a bus hold

when LOCK is asserted (but address holds are al-

lowed). LOCK goes active in the first clock of the first

locked bus cycle and goes inactive after the last clock

of the last locked bus cycle. The last locked cycle ends

when RDY is returned. LOCK is active Low and is not

driven during bus hold. Locked read cycles are not

transformed into cache fill cycles if KEN is active.

NMI

Non-Maskable Interrupt (Active High; Input)

A high NMI signal indicates that external non-maskable

interrupt occurred. NMI is rising edge sensitive, but must

be held Low for at least four-CLK periods before the

rising edge. NMI does not have an internal pull-down

resistor. NMI is asynchronous, but must meet setup and

hold times t20 and t21 for recognition in any specific clock.

PCD/PWT

Page Cache Disable/Page Write-Through

(Active High; Outputs)

The outputs reflect the state of the page attribute bits

PWT and PCD in the page table or page directory entry.

If paging is disabled or unpaged cycles occur, PWT and

PCD reflect the state of the PWT and PCD bits in Control

cycle definition pins (M/IO, D/C, and W/R). PWT and

PCD are active High and are not driven during bus hold.

PCD is masked by the Cache Disable Bit (CD) in Control

PCHK

Parity Status (Active Low; Output)

For read operations, the parity status is driven on the

PCHK pin one clock after RDY for data sampled at the

end of the previous clock. A parity error is indicated by

PCHK being Low. Parity status is only checked for en-

abled bytes as indicated by the byte enable and bus

size signals. PCHK is valid only in the clock immediately

after read data is returned to the microprocessor. At all

other times, PCHK is inactive High. PCHK is never float-

ed except during three-state test mode (see FLUSH).

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

PLOCK

Pseudo-Lock (Active Low; Output)

PLOCK indicates that the current bus transaction re-

quires more than one bus cycle to complete. Examples

of such operations are floating-point long reads and

writes (64 bits), segment table descriptor reads (64 bits),

and cache line fills (128 bits). The Am486DX2 micro-

processor drives PLOCK active until the addresses for

the last bus cycle of the transaction have been driven,

regardless of whether RDY or BRDY has been returned.

Normally, PLOCK and BLAST are inverse of each other.

However, during the first bus cycle of a 64-bit floating-

point write, both PLOCK and BLAST will be asserted.

PLOCK is a function of the BS8, BS16, and KEN inputs.

PLOCK should be sampled only if the clock RDY is re-

turned. PLOCK is active Low and is not driven during

bus hold.

RESET

Reset (Active High; Input)

This pin forces the Am486DX2 microprocessor to begin

execution at a known state. The microprocessor cannot

begin execution of instructions until at least 1 ms after

VCC and CLK have reached proper DC and AC specifi-

cations. The RESET pin should remain active during

this time to ensure proper microprocessor operation.

RESET is active High. RESET is asynchronous but

must meet setup and hold times t20 and t21for recogni-

tion in any specific clock.

RDY

Non-Burst Ready (Active Low; Input)

This input pin indicates that the current bus cycle is

complete. RDY indicates that the external system has

presented valid data on the data pins in response to a

read, or that the external system has accepted data from

the Am486DX2 microprocessor in response to a write.

RDY is ignored when the bus is idle and at the end of

the bus cycle’s first clock.

RDY is active during address hold. Data can be returned

to the processor while AHOLD is active.

RDY is active Low and is not provided with an internal

pull-up resistor. RDY must satisfy setup and hold times

t16 and t17 for proper chip operation.

TCK

Test Clock (Input)

Test Clock is an input to the Am486DX2 CPU and pro-

vides the clocking function required by the JTAG bound-

ary scan feature. TCK is used to clock state information

and data into and out of the component. State select

information and data are clocked into the component on

the rising edge of TCK on TMS and TDI, respectively.

Data is clocked out of the component on the falling edge

of TCK on TDO.

TDI

Test Data Input (Input)

TDI is the serial input used to shift JTAG instructions

and data into the component. TDI is sampled on the

rising edge of TCK, during the SHIFT-IR and the

SHIFT-DR TAP controller states. During all other tap

controller states, TDI is a “don’t care.”

TDO

Test Data Output (Output)

TDO is the serial output used to shift JTAG instructions

and data out of the component. TDO is driven on the

falling edge of TCK during the SHIFT-IR and SHIFT-DR

TAP controller states. At all other times, TDO is driven

to the high impedance state.

TMS

Test Mode Select (Input)

TMS is decoded by the JTAG TAP (Test Access Port)

to select the operation of the test logic. TMS is sampled

on the rising edge of TCK. To guarantee deterministic

behavior of the TAP controller, TMS is provided with an

internal pull-up resistor.

Upgrade Present (Active Low; Input)

The Upgrade Present pin forces the Am486DX2 CPU

to three-state all its outputs and enter the power-down

mode. When the Upgrade Present pin is sampled as-

serted by the CPU in the clock before the falling edge

of RESET, the power-down mode is enabled. UP has

no effect on the power-down status expect during this

edge. The CPU is also forced to three-state all of its

outputs immediately in response to this signal. The UP

signal must remain asserted in order to keep the pins

three-state. UP is active Low and is provided with an

internal pull-up resistor.

VOLDET

Voltage Detect (Output)

The voltage detect signal allows external system logic

to distinguish between a 5-V Am486 processor and the

3.3-V Am486DX2 processor. The signal is active Low

for a 3.3-V Am486DX2 processor.

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

Table 3. Output Pins

NameActive

LevelFloated At

BREQ

HLDA

BE3–BE0

PCD/PWT

W/R, D/C, M/IO

LOCK

PLOCK

ADS

BLAST

PCHK

A3–A2

FERR

VOLDET

High

Low

High

Low

High

Low

−

Three-State Test Mode

Bus Hold

Three-State Test Mode

Bus, Address Hold

Three-State Test Mode

Table 4. Input Pins

NameActive

LevelSynchronous/

Asynchronous

CLK

RESET

HOLD

AHOLD

EADS

BOFF

FLUSH

A20M

BS16, BS8

KEN

RDY

BRDY

INTR

NMI

IGNNE

CLKMUL

−

High

Low

High

Low

−

Asynchronous

Synchronous

Asynchronous

Synchronous

Asynchronous

−

Table 5. Input/Output Pins

NameActive

LevelFloated At

D31––D0

DP3–DP0

A31–A4

High

Bus Hold

Bus, Address Hold

Table 6. Test Pins

NameInput or OutputSampled/Driven On

TCK

TDI

TDO

TMS

Input

Output

Input

N/A

Rising Edge of TCK

Falling Edge of TCK

Rising Edge of TCK

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

CPU IDENTIFICATION CODES

The DX register always contains a component identifi-

cation at the conclusion of RESET. The upper byte of

DX (DH) will contain 04 and the lower byte of DX (DL)

will contain a CPU type/stepping identifier.

ARCHITECTURAL OVERVIEW

The Am486DX2 processor is a 32-bit architecture with

on-chip memory management and cache memory units.

It is a fully compatible member of the Am486 micropro-

cessor family.

On-chip cache memory allows frequently used data and

code to be stored on-chip, thereby reducing accesses

to the external bus. RISC design techniques are used

to reduce instruction cycle times. A burst bus feature

enables fast cache fills.

The Am486 CPU Memory Management Unit (MMU)

consists of a segmentation unit and a paging unit. Seg-

mentation allows management of the logical address

space by providing easy data and code relocatibility and

efficient sharing of global resources. The paging mech-

anism operates beneath segmentation and is transpar-

ent to the segmentation process. Paging is optional and

can be disabled by system software. Each segment can

be divided into one or more 4-Kbyte segments. To im-

plement a virtual memory system, the Am486DX2 mi-

croprocessor supports full restartability for all page and

segment faults.

Table 7. CPU ID

Component ID

(DH)Component ID

(DL)

04 32

Table 8. JTAG ID Code

Version CodePart Number

CodeManufacturer

Identity

00h 0432 01

Memory is organized into one or more variable length

segments, each up to 4 Gbytes (232 bytes) in size. A

segment can have attributes associated with it. These

attributes include its location, size, type (i.e., stack,

code, or data), and protection characteristics. Each task

on an Am486DX2 microprocessor can have a maximum

of 16,381 segments, each up to 4 Gbytes in size. Thus,

each task has a maximum of 64 Tbytes (terabytes) of

virtual memory.

The segmentation unit provides four levels of protection

for isolating and protecting applications and the operat-

ing system from each other. The hardware enforced pro-

tection allows high integrity system designs.

The Am486DX2 microprocessor has three modes of op-

eration: Real Address mode (Real mode), Virtual Ad-

dress mode (Protected mode), and within Protected

mode, tasks may be performed in Virtual 8086 mode.

In Real mode, the Am486DX2 microprocessor operates

as a very fast 8086. Real mode is required primarily to

set up the processor for Protected mode operation. Pro-

tected mode provides access to the sophisticated mem-

ory management paging and privilege capabilities of the

processor.

Within Protected mode, software can perform a task

switch to enter into tasks designated as Virtual 8086

mode tasks. Each Virtual 8086 task behaves with 8086

semantics, allowing 8086 software (an application pro-

gram or an entire operating system) to execute.

The on-chip cache is 8 Kbytes. It is four-way set asso-

ciative and follows a write-through policy. The on-chip

cache includes features that provide flexibility in exter-

nal memory system design. Individual pages can be

designated as cacheable or non-cacheable by software

or hardware. The cache can also be enabled and dis-

abled by software or hardware.

Finally, the Am486DX2 microprocessor has features

that facilitate high-performance hardware designs. The

2x clock multiplier improves execution performance

without increasing the board design complexity. This 2x

clock multiplier enhances all operations operating out

of the cache and/or not blocked by external bus assess-

es. The burst bus feature enables fast cache fills.

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

ELECTRICAL DATA

The following sections describe recommended electri-

cal connections for the Am486DX2 microprocessor

and its electrical specifications.

Power and Grounding

Power Connections

The Am486DX2 microprocessor is implemented in ad-

vanced submicron CMOS-process technology and has

modest power requirements. However, its high clock

frequency output buffers can cause power surges as

multiple output buffers drive new signal levels simulta-

neously. For clean, on-chip power distribution at high

frequency, 23 VCC and 28 VSS pins feed the Am486DX2

microprocessor.

Power and ground connections must be made to all

external VCC and GND pins of the Am486DX2 micropro-

cessor. On the circuit board, all VCC pins must be con-

nected on a VCC plane. All VSS pins must likewise be

connected on a GND plane.

Power Decoupling Recommendations

Liberal decoupling capacitance should be placed near

the Am486DX2 CPU. The Am486DX2 microprocessor,

driving its 32-bit parallel address and data buses at

high frequencies, can cause transient power surges,

particularly when driving large capacitive loads.

Low inductance capacitors and interconnects are rec-

ommended for best high-frequency electrical perfor-

mance. Inductance can be reduced by shortening cir-

cuit board traces between the Am486DX2 micropro-

cessor, and using decoupling capacitors as much as

possible. Capacitors specifically for PGA packages are

also commercially available.

System Clock Recommendations

The CLK input to the Am486DX2 processor should not

be driven until VCC has reached its normal operating

level (3.3 V). Once VCC has reached its normal operating

level, the Am486DX2 CPU can handle the clock fre-

quency for which it is specified and the oscillator/clock

driver should have locked onto its desired frequency.

Other Connection Recommendations

NC pins should always remain unconnected.

For reliable operation, always connect unused inputs to

an appropriate signal level. Active Low inputs should

be connected to VCC through a pull-up resistor. Pull-ups

in the range of 20 KΩ are recommended. Active High

inputs should be connected to GND.

Any pin designated as INC is electrically isolated and

has no special requirements.

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

Case Temperature under Bias...........−65°C to +11 0°C

Storage Temperature...........................−65°C to +150°C

Voltage on any pin

with respect to ground.............. −0.5 V to VCC +2.6 V

Supply voltage with

respect to VSS ...................................−0.5 V to +4.6 V

Stresses above those listed under Absolute Maximum Rat-

ings may cause permanent device failure. Functionality at or

above these limits is not implied. Exposure to Absolute Max-

imum Ratings for extended periods may affect device

reliability.

OPERATING RANGES

Commercial (C) Devices

TCASE.......................................................0°C to +85°C

VCC.......................................................... 3.3 V ± 0.3 V

Operating Ranges define those limits between which the

functionality of the device is guaranteed.

——————————————————————————————————————————————————————————————

DC CHARACTERISTICS over COMMERCIAL operating ranges

Functional Operating Range: VCC = 3.3 V ± 0.3 V. TCASE=0°C to +85°C.

Notes:

1. This parameter is measured at: Address, Data, BE3−BE04.0 mA

Definition, Control 5.0 mA

2. This parameter is measured at: Address, Data, BE3−BE0−1.0 mA

Definition, Control −0.9 mA

3. Typical supply current: 530 mA @ 66 MHz and 640 mA @ 80 MHz.

4. This parameter is for inputs without pull-ups or pull-downs and 0 ≤ VIN ≤ VCC.

5. This parameter is for inputs with pull-downs and VIH=2.4 V.

6. This parameter is for inputs with pull-ups and VIL=0.45 V.

7. Not 100% tested.

8. This parameter is for inputs without pull-ups or pull-downs and VCC ≤ VIN ≤ 5 V.

9. This parameter is for three-state outputs where VEXT is driven on the three-state output and 0 ≤ VEXT ≤ VCC.

10. This parameter is for three-state outputs where VEXT is driven on the three-state output and VCC ≤ VEXT ≤ 5 V.

Preliminary

SymbolParameter DescriptionNotesMinMaxUnit

VILInput Low Voltage−0.3+0.8V

VIHInput High Voltage2.0VCC+2.4 V

VOLOutput Low VoltageIOL=(Note 1)0.45 V

VOHOutput High VoltageIOH=(Note 2)2.4V

ICCPower Supply Current(Note 3) 66 MHz

(Note 3) 80 MHz660

800mA

ILIInput Leakage Current(Note 4)

(Note 8)±15

± 50 µA

µA

IIHInput Leakage Current(Note 5)200µA

IILInput Leakage Current(Note 6)−400µA

ILOOutput Leakage Current(Note 9)

(Note 10)±15

± 50 µA

µA

CIN Input Capacitance FC=1 MHz (Note 7)10 pF

CO I/O or Output CapacitanceFC=1 MHz (Note 7)14 pF

CCLK CLK CapacitanceFC=1 MHz (Note 7)12 pF

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

SWITCHING CHARACTERISTICS

The switching characteristics consist of output delays,

input setup requirements, and input hold requirements.

All switching characteristics are relative to the rising

edge of the CLK signal.

Switching characteristics measurement is defined by

Figures 2−9. Inputs must be driven to the voltage levels

indicated by Figure 2 when switching characteristics

are measured.

Am486DX2 microprocessor delays are specified with

minimum and maximum limits. The minimum

Am486DX2 processor delay times are hold times

provided to external circuitry. Am486DX2 CPU input

setup and hold times are specified as minimums,

defining the smallest acceptable sampling windows.

Within the sampling windows, a synchronous input

signal must be stable for correct Am486DX2

microprocessor operation.

P R E L I M I N A R Y

Am486DX2 Microprocessor

AMD

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges

Switching Characteristics at 66 MHz; TCASE=0°C to +85°C; CL=50 pF unless otherwise specified.

Note:

1.Not 100% tested. Guaranteed by design characterization.

Preliminary

SymbolParameter DescriptionNotesFigureMinMaxUnit

Operating Frequency8 33 MHz

t1CLK Period 2 30 125 ns

t1aCLK Period StabilityAdjacent Clocks0.1%∆

t2CLK High Time@ 2.0 V2 11 ns

t3CLK Low Time@ 0.8 V2 11 ns

t4CLK Fall Time 2 3 ns

t5CLK Rise Time 2 3 ns

t6A31−A2, PWT, PCD, M/IO, BE3−BE0, D/C,

W/R, ADS, LOCK, FERR, BREQ, HLDA

Valid Delay

7 3 14 ns

t7A31−A2, PWT, PCD, M/IO, BE3−BE0, D/C,

W/R, ADS, LOCK, FERR, BREQ, HLDA Float

Delay

(Note 1)8 20 ns

t8PCHK Valid Delay6 3 14 ns

t8aBLAST, PLOCK Valid Delay7 3 14 ns

t9BLAST, PLOCK Float Delay(Note 1)8 20 ns

t10D31−D0, DP3−DP0 Write Data Valid Delay7 3 14 ns

t11D31−D0, DP3−DP0 Write Data Float Delay(Note 1)8 20 ns

t12EADS Setup Time 4 5 ns

t13EADS Hold Time 4 3 ns

t14KEN, BS16, BS8 Setup Time 4 5 ns

t15KEN, BS16, BS8 Hold Time 4 3 ns

t16RDY, BRDY Setup Time 5 5 ns

t17RDY, BRDY Hold Time 5 3 ns

t18HOLD, AHOLD Setup Time 4 6 ns

t18a BOFF Setup Time 4 7 ns

t19HOLD, AHOLD, BOFF Hold Time 4 3 ns

t20RESET, FLUSH, A20M, NMI, INTR, IGNNE

Setup Time 3, 4 5 ns

t21RESET, FLUSH, A20M, NMI, INTR, IGNNE

Hold Time3, 4 3 ns

t22D31−D0, DP3−DP0, A31−A4 Read Setup Time 4, 5 5 ns

t23D31−D0, DP3−DP0, A31−A4 Read Hold Time4, 5 3 ns

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges

Switching Characteristics at 80 MHz; TCASE=0°C to +85°C; CL=50 pF unless otherwise specified.

Note:

1.Not 100% tested. Guaranteed by design characterization.

Preliminary

SymbolParameter DescriptionNotesFigureMinMaxUnit

Operating Frequency8 40 MHz

t1CLK Period 2 25 125 ns

t1aCLK Period StabilityAdjacent Clocks0.1%∆

t2CLK High Time@ 2.0 V2 9 ns

t3CLK Low Time@ 0.8 V2 9 ns

t4CLK Fall Time 2 3 ns

t5CLK Rise Time 2 3 ns

t6A31−A2, PWT, PCD, M/IO, BE3−BE0, D/C,

W/R, ADS, LOCK, FERR, BREQ, HLDA

Valid Delay

7 3 14 ns

t7A31−A2, PWT, PCD, M/IO, BE3−BE0, D/C,

W/R, ADS, LOCK, FERR, BREQ, HLDA Float

Delay

(Note 1)8 3 18 ns

t8PCHK Valid Delay6 3 16 ns

t8aBLAST, PLOCK Valid Delay7 3 18 ns

t9BLAST, PLOCK Float Delay(Note 1)8 3 16 ns

t10D31−D0, DP3−DP0 Write Data Valid Delay7 3 14 ns

t11D31−D0, DP3−DP0 Write Data Float Delay(Note 1)8 3 18 ns

t12EADS Setup Time 4 5 ns

t13EADS Hold Time 4 3 ns

t14KEN, BS16, BS8 Setup Time 4 5 ns

t15KEN, BS16, BS8 Hold Time 4 3 ns

t16RDY, BRDY Setup Time 5 5 ns

t17RDY, BRDY Hold Time 5 3 ns

t18HOLD, AHOLD Setup Time 4 6 ns

t18a BOFF Setup Time 4 8 ns

t19HOLD, AHOLD, BOFF Hold Time 4 3 ns

t20RESET, FLUSH, A20M, NMI, INTR, IGNNE

Setup Time 3, 4 5 ns

t21RESET, FLUSH, A20M, NMI, INTR, IGNNE

Hold Time3, 4 3 ns

t22D31−D0, DP3−DP0, A31−A4 Read Setup Time 4, 5 5 ns

t23D31−D0, DP3−DP0, A31−A4 Read Hold Time4, 5 3 ns

P R E L I M I N A R Y

Am486DX2 Microprocessor

AMD

Am486DX2 CPU AC Characteristics for Boundary Scan Test Signals at 25 MH z

VCC = 3.3 V ± 0.3 V; TCASE=0°C to +85°C; CL = 50 pF. All inputs and outputs are TTL Level.

Notes:

1. Rise/Fall times are measured between 0.8 V and 2.0 V. Rise/Fall times can be relaxed by 1 ns per 10-ns increase in TCK

period.

2. TCK period > CLK period.

3. Parameter measured from TCK.

SymbolParameter MinMaxUnitFigureNotes

t24TCK Frequency25 MHz1x Clock

t25TCK Period 40 nsNote 2

t26TCK High Time 10 nsat 2.0 V

t27TCK Low Time 10 nsat 0.8 V

t28TCK Rise Time 4 nsNote 1

t29TCK Fall Time 4 nsNote 1

t30TDI, TMS Setup Time 8 ns 9Note 3

t31TDI, TMS Hold Time 7 ns 9Note 3

t32TDO Valid Delay3 25 ns 9Note 3

t33TDO Float Delay36 ns 9Note 3

t34All Outputs (Non-Test) Valid Delay3 25 ns 9Note 3

t35All Outputs (Non-Test) Float Delay36 ns 9Note 3

t36All Inputs (Non-Test) Setup Time 8 ns 9Note 3

t37All Inputs (Non-Test) Hold Time 7 ns 9Note 3

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

Must be

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Change

Permitted

Will be

Steady

Will be

Changing

from H to L

Will be

Changing

from L to H

Changing,

State

Unknown

Center

Line is High-

Impedance

“Off” State

WAVEFORMINPUTSOUTPUTS

Figure 1. Change State Diagram

2.0 V

1.5 V

0.8 V

Figure 2. CLK Waveforms

17852B-095

P R E L I M I N A R Y

Am486DX2 Microprocessor

AMD

TxTxTx

CLK

RESET

t20

t21

RESETInitialization Sequence

Figure 3. Reset Setup and Hold Timing

CLK

EADS

BS8, BS16,

KEN

TxTxTxTx

BOFF,

AHOLD,

HOLD

RESET, FLUSH,

A20M, IGNNE,

INTR, NMI

A31−A4

(Read)

Figure 3. Input Setup and Hold Timin

17852A-099

t12t13

t15

t14

t18t19

t21

t22t23

t20

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

CLK

RDY, BRDY

T2TxTxTx

D31−D0

DP3−DP0

(Read)

1.5 V

Figure 4. RDY and BRDY Input Setup and Hold Timing

17852A-100

t16

t22

t17

t23

CLK

BRDY, RDY

PCHK

T2TxTxTx

Valid

Min

Max

Figure 5. PCHK Valid Delay Timing 17852A-101

D31−D0

DP3−DP0

(Read) t8

Valid

CLK

A31−A2, PWT, PCD,

BE3−BE0, M/IO,

D/C, W/R, ADS,

LOCK, FERR, BREQ,

HLDA

BLAST, PLOCK

TxTxTx

D31−D0, DP3−DP0,

(Write)

Min Max

Valid n +1

Min Max

Valid n +1

Valid n

Min Max

Valid n +1

17852A-102

Figure 6. Output Valid Delay Timing

t10

t8a

Valid n

P R E L I M I N A R Y

Am486DX2 Microprocessor

AMD

CLK

A31−A2, PWT, PCD,

BE3−BE0, M/IO,

D/C, W/R, ADS,

LOCK, FERR, BREQ,

HLDA

BLAST, PLOCK

TxTxTx

D31−D0,

DP3−DP0

(Write)

Valid

Figure 7. Maximum Float Delay Timing 17852A-103

t10

t8a

Min

t11

TCK

TDI, TMS

TDO

Output

Signals

Input

Signals

Figure 8. Test Signal Timing Diagram

17852B-104

t25

t30 t31

t32

t34

t35

t36 t37

t33

P R E L I M I N A R Y

AMD

Am486DX2 Microprocessor

Package Thermal Specifications

The Am486DX2 microprocessor is specified for opera-

tion when TCASE (the case temperature) is within the

range of 0°C to +85°C. TCASE can be measured in any

environment to determine whether the Am486DX2 mi-

croprocessor is within specified operating range. The

case temperature should be measured at the center of

the top surface opposite the pins.

The ambient temperature (TA) is guaranteed as long as

TCASE is not violated. The ambient temperature can be

calculated from θJC and θJA and from the following

equations:

TJ = TCASE + P • θJC

TA = TJ – P • θJA

TCASE = TA + P • [θJA – θJC]

where:

TJ, TA, TCASE= Junction, Ambient, and Case Tempera-

ture.

θJC, θJA = Junction-to-Case and Junction-to-Ambient

Thermal Resistance, respectively.

P = Maximum Power Consumption

The values for θJA and θJC are given in Table 9 for the

1.75 sq. in., 168-pin, ceramic PGA.

Table 10 shows the TA

allowable (without exceeding

TCASE) at various airflows and operating frequencies

(Clock). Note that TA is greatly improved by attaching

fins or a heat sink to the package. Heat sink dimen-

sions are shown in Figure 10. P (the maximum power

consumption) is calculated by using the maximum ICC

as tabulated in the DC Characteristics.

——————————————————————————————————————————————————————————————

*0.350″ high unidirectional heat sink (Al alloy 6063-T5, 40 mil fin width, 155 mil center-to-center fin spacing).

Table 9. Thermal Resistance (°C/W) θJC and θJA for the 66-MHz and 80-MHz Am486DX2 CPU

θJA vs. Airflow-ft/min. (m/sec)

θJC0 (0)200

(1.01)400

(2.03) 600

(3.04)800

(4.06)1000

(5.07)

No Heat Sink1.516.514.012.010.59.59.0

Heat Sink*2.012.07.05.04.03.53.25

Heat Sink* and fan2.05.04.64.23.83.53.25

Table 10. Maximum TA at Various Airflows in °C

Airflow-ft/min. (m/sec)

Clock0 (0)200

(1.01)400

(2.03)600

(3.04)800

(4.06)1000

(5.07)

TA without Heat Sink*66 MHz49.455.360.163.666.067.2

TA with Heat Sink66 MHz61.273.177.980.381.482.0

80 MHz56.270.676.479.280.781.4

TA with Heat Sink and

fan66 MHz77.978.879.880.781.482.0

80 MHz76.477.578.779.880.781.4

Figure 10. Heat Sink Dimensions

0.290″

0.100″

0.040″

1.53″

0.350″

0.060″

0.115″

17852B-113

P R E L I M I N A R Y

Am486DX2 Microprocessor

AMD

PHYSICAL DIMENSIONS

For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering.

1.735

1.765

1.735

1.765

Bottom View (Pins Facing Up)

Base Plane

Seating Plane

0.140

0.180

0.110

0.140

0.105

0.125

0.017

0.020

Side View

CGM 168

16734C

5/11/93 MH

0.025

0.045

1.595

1.605

1.595

1.605

Index

Corner

0.090

0.110

AMD, Am386, and Am486 are registered trademarks of Advanced Micro Devices, Inc.

FusionPC is a service mark of Advanced Micro Devices, Inc.

Microsoft and Windows are registered trademarks of Microsoft Corp.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

P R E L I M I N A R Y