512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 SST27SF512 / 010 / 0205.0V-Read 512Kb / 1Mb / 2Mb (x8) MTP flash memories Data Sheet FEATURES: * Organized as 64K x8 / 128K x8 / 256K x8 * 4.5-5.5V Read Operation * Superior Reliability - Endurance: At least 1000 Cycles - Greater than 100 years Data Retention * Low Power Consumption - Active Current: 20 mA (typical) - Standby Current: 10 A (typical) * Fast Read Access Time - 70 ns * Fast Byte-Program Operation - Byte-Program Time: 20 s (typical) - Chip Program Time: 1.4 seconds (typical) for SST27SF512 2.8 seconds (typical) for SST27SF010 5.6 seconds (typical) for SST27SF020 * Electrical Erase Using Programmer - Does not require UV source - Chip-Erase Time: 100 ms (typical) * TTL I/O Compatibility * JEDEC Standard Byte-wide EPROM Pinouts * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 14mm) - 32-pin PDIP for SST27SF010/020 * All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST27SF512/010/020 are a 64K x8 / 128K x8 / 256K x8 CMOS, Many-Time Programmable (MTP) low cost flash, manufactured with SST's proprietary, high performance SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. These MTP devices can be electrically erased and programmed at least 1000 times using an external programmer with a 12V power supply. They have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide memories. Device Operation Featuring high-performance Byte-Program, the SST27SF512/010/020 provide a Byte-Program time of 20 s. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years. Read The SST27SF512/010/020 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the SST27SF512 are offered in 32-lead PLCC, 32-lead TSOP, and 28-pin PDIP packages. The SST27SF010/020 are offered in 32-pin PDIP, 32-lead PLCC, and 32-lead TSOP packages. See Figures 3, 4, and 5 for pin assignments. (c)2008 Silicon Storage Technology, Inc. S71152-12-000 9/08 1 The SST27SF512/010/020 are a low cost flash solution that can be used to replace existing UV-EPROM, OTP, and mask ROM sockets. These devices are functionally (read and program) and pin compatible with industry standard EPROM products. In addition to EPROM functionality, these devices also support electrical Erase operation via an external programmer. They do not require a UV source to erase, and therefore the packages do not have a window. The Read operation of the SST27SF512/010/020 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming that CE# pin has been low and the addresses have been stable for at least TCE-TOE. When the CE# pin is high, the chip is deselected and a typical standby current of 10 A is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Byte-Program Operation Product Identification Mode The SST27SF512/010/020 are programmed by using an external programmer. The programming mode for SST27SF010/020 is activated by asserting 11.4-12V on VPP pin, VDD = 4.5-5.5V, VIL on CE# pin, and VIH on OE# pin. The programming mode for SST27SF512 is activated by asserting 11.4-12V on OE#/VPP pin, VDD = 4.5-5.5V, and VIL on CE# pin. These devices are programmed byteby-byte with the desired data at the desired address using a single pulse (CE# pin low for SST27SF512 and PGM# pin low for SST27SF010/020) of 20 s. Using the MTP programming algorithm, the Byte-Programming process continues byte-by-byte until the entire chip has been programmed. The Product Identification mode identifies the devices as the SST27SF512, SST27SF010 and SST27SF020 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode for SST27SF010/ 020, the programming equipment must force VH (11.4-12V) on address A9 with VPP pin at VDD (4.5-5.5V) or VSS. To activate this mode for SST27SF512, the programming equipment must force VH (11.4-12V) on address A9 with OE#/VPP pin at VIL. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Tables 3 and 4 for hardware operation. TABLE 1: Product Identification Chip-Erase Operation Address Data 0000H BFH SST27SF512 0001H A4H SST27SF010 0001H A5H SST27SF020 0001H A6H Manufacturer's ID The only way to change a data from a "0" to "1" is by electrical erase that changes every bit in the device to "1". Unlike traditional EPROMs, which use UV light to do the ChipErase, the SST27SF512/010/020 uses an electrical ChipErase operation. This saves a significant amount of time (about 30 minutes for each Erase operation). The entire chip can be erased in a single pulse of 100 ms (CE# pin low for SST27SF512 and PGM# pin for SST27SF010/ 020). In order to activate the Erase mode for SST27SF010/ 020, the 11.4-12V is applied to VPP and A9 pins, VDD = 4.55.5V, VIL on CE# pin, and VIH on OE# pin. In order to activate Erase mode for SST27SF512, the 11.4-12V is applied to OE#/VPP and A9 pins, VDD = 4.5-5.5V, and VIL on CE# pin. All other address and data pins are "don't care". The falling edge of CE# (PGM# for SST27SF010/020) will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FFH. Refer to Figures 13 and 14 for the flowcharts. Device ID T1.2 1152 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 2 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet SuperFlash Memory X-Decoder A15 - A0 Address Buffer Y-Decoder CE# OE#/VPP A9 Control Logic I/O Buffers DQ7 - DQ0 1152 B2.1 FIGURE 1: Functional Block Diagram - SST27SF512 SuperFlash Memory X-Decoder AMS - A0 Address Buffer Y-Decoder CE# OE# A9 I/O Buffers Control Logic VPP DQ7 - DQ0 PGM# AMS = A17 for SST27SF020, A16 for SST27SF010 1152 B3.2 FIGURE 2: Functional Block Diagram - SST27SF010/020 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 3 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 NC A13 A17 PGM# PGM# 1 A14 2 VDD VPP 3 VDD VPP 4 VDD NC A16 A16 A15 A15 A15 SST27SF010/020 A12 SST27SF512 A12 SST27SF010 A7 SST27SF020 A12 Data Sheet SST27SF512 SST27SF512 SST27SF010/020 32 31 30 29 A8 A14 6 28 A9 A13 A4 7 27 A11 A8 A4 A3 8 26 NC A9 A3 A2 9 25 OE#/VPP A11 A2 A1 10 24 A10 OE# A1 A0 11 23 CE# A10 A0 NC 12 22 DQ7 CE# DQ0 DQ0 13 21 14 15 16 17 18 19 20 DQ6 DQ7 NC DQ3 DQ4 DQ5 DQ5 DQ6 SST27SF010/020 DQ4 SST27SF512 DQ3 32-lead PLCC Top View VSS A5 VSS A5 DQ2 A6 DQ1 5 DQ2 A6 DQ1 A7 1152 32-plcc P1.5 FIGURE 3: Pin Assignments for 32-lead PLCC SST27SF020 SST27SF010 SST27SF512 A17 PGM# NC PGM# VPP A16 VPP A16 A11 A9 A8 A13 A14 NC NC VDD NC NC A15 A12 A7 A6 A5 A4 SST27SF512 SST27SF010 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View Die Up 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE#/VPP A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 SST27SF020 OE# OE# 1152 32-tsop P2.3 FIGURE 4: Pin Assignments for 32-lead TSOP (8mm x 14mm) (c)2008 Silicon Storage Technology, Inc. S71152-12-000 4 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet SST27SF020 SST27SF010 SST27SF512 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS SST27SF512 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-pin PDIP Top View 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD A14 A13 A8 A9 A11 OE#/VPP A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS SST27SF010 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SST27SF020 VDD PGM# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD PGM# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 1152 28-pdip P3.2 1152 32-pdip P4.2 FIGURE 5: Pin Assignments for 28-pin and 32-pin PDIP TABLE 2: Pin Description Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Program cycles The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low OE# Output Enable For SST27SF010/020, to gate the data output buffers during Read operation OE#/VPP Output Enable/VPP For SST27SF512, to gate the data output buffers during Read operation and high voltage pin during Chip-Erase and programming operation VPP Power Supply for Program or Erase For SST27SF010/020, high voltage pin during Chip-Erase and programming operation 11.4-12V To provide 5.0V supply (4.5-5.5V) VDD Power Supply VSS Ground NC No Connection Unconnected pins. T2.4 1152 1. AMS = Most significant address AMS = A15 for SST27SF512, A16 for SST27SF010, and A17 for SST27SF020 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 5 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE 3: Operation Modes Selection for SST27SF512 Mode CE# OE#/VPP A9 DQ Address Read VIL VIL AIN DOUT AIN Output Disable VIL VIH X1 High Z X Program VIL VPPH AIN DIN AIN Standby VIH X X High Z X Chip-Erase VIL VPPH VH High Z X Program/Erase Inhibit VIH VPPH X High Z X Product Identification VIL VIL VH Manufacturer's ID (BFH) Device ID (A4H) A15-A1=VIL, A0=VIL A15-A1=VIL, A0=VIH T3.2 1152 1. X can be VIL or VIH, but no other value. Note: VPPH = 11.4-12V, VH = 11.4-12V TABLE 4: Operation Modes Selection for SST27SF010/020 Mode CE# OE# PGM# A9 VPP DQ Address Read VIL VIL X1 AIN VDD or VSS DOUT AIN Output Disable VIL VIH X X Program VIL VIH VIL AIN VDD or VSS High Z AIN VPPH DIN AIN Standby VIH X X X VDD or VSS High Z X Chip-Erase VIL VIH VIL VH VPPH High Z X Program/Erase Inhibit VIH X X X VPPH High Z X Product Identification VIL VIL X VH VDD or VSS Manufacturer's ID (BFH) Device ID2 AMS3 - A1=VIL, A0=VIL AMS3 - A1=VIL, A0=VIH T4.2 1152 1. X can be VIL or VIH, but no other value. 2. Device ID = A5H for SST27SF010 and A6H for SST27SF020 3. AMS = Most significant address AMS = A16 for SST27SF010 and A17 for SST27SF020 Note: VPPH = 11.4-12V, VH = 11.4-12V (c)2008 Silicon Storage Technology, Inc. S71152-12-000 6 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 and VPP Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hole Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA 1. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Commercial AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . 10 ns Ambient Temp VDD VPP 0C to +70C 4.5-5.5V 11.4-12V Output Load . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns See Figures 11 and 12 TABLE 5: Read Mode DC Operating Characteristics for SST27SF512/010/020 VDD = 4.5-5.5V, VPP=VDD or VSS (TA = 0C to +70C (Commercial)) Limits Symbol Parameter IDD Min Max Units VDD Read Current 30 IPPR Test Conditions Address input=VILT/VIHT at f=1/TRC Min VDD=VDD Max mA VPP Read Current CE#=OE#=VIL, all I/Os open Address input=VILT/VIHT at f=1/TRC Min VDD=VDD Max, VPP=VDD 100 A CE#=OE#=VIL, all I/Os open ISB1 Standby VDD Current (TTL input) 3 mA CE#=VIH, VDD=VDD Max ISB2 Standby VDD Current (CMOS input) 100 A CE#=VDD-0.3 VDD=VDD Max ILI Input Leakage Current 1 A VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 A VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IH Supervoltage Current for A9 2.0 VDD+0.5 V VDD=VDD Max 0.2 V IOL=2.1 mA, VDD=VDD Min V IOH=-400 A, VDD=VDD Min 200 A CE#=OE#=VIL, A9=VH Max 2.4 T5.6 1152 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 7 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE 6: Program/Erase DC Operating Characteristics for SST27SF512 VDD=4.5-5.5V, VPP=VPPH (TA=25C5C) Limits Symbol Parameter IDD VDD Erase or Program Current IPP ILI Min Max Units Test Conditions 30 mA VPP Erase or Program Current 3 mA CE#=VIL, OE#/VPP=11.4-12V, VDD=VDD Max Input Leakage Current 1 A VIN=GND to VDD, VDD=VDD Max 10 A VOUT=GND to VDD, VDD=VDD Max 12 V CE#=OE#/VPP=VIL, 200 A CE#=OE#/VPP=VIL, A9=VH Max 12 V ILO Output Leakage Current VH Supervoltage for A9 IH Supervoltage Current for A9 VPPH High Voltage for OE#/VPP Pin 11.4 11.4 CE#=VIL, OE#/VPP=11.4-12V, VDD=VDD Max T6.5 1152 TABLE 7: Program/Erase DC Operating Characteristics for SST27SF010/020 VDD=4.5-5.5V, VPP=VPPH (TA=25C5C) Limits Symbol Parameter Min Max Units Test Conditions IDD VDD Erase or Program Current 30 mA CE#=PGM#=VIL, OE#=VIH, VPP=11.4-12V, VDD=VDD Max IPP VPP Erase or Program Current 3 mA CE#=PGM#=VIL, OE#=VIH, VPP=11.4-12V, VDD=VDD Max ILI Input Leakage Current 1 A VIN =GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 A VOUT =GND to VDD, VDD=VDD Max VH Supervoltage for A9 IH Supervoltage Current for A9 VPPH High Voltage for VPP Pin 11.4 11.4 12 V CE#=OE#=VIL, 200 A CE#=OE#=VIL, A9=VH Max 12 V T7.5 1152 TABLE 8: Recommended System Power-up Timings Symbol TPU-READ Parameter 1 TPU-WRITE1 Minimum Units Power-up to Read Operation 100 s Power-up to Write Operation 100 s T8.1 1152 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 9: Capacitance (TA = 25C, f=1 Mhz, other pins open) Parameter CI/O 1 CIN1 Description Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF T9.0 1152 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method NEND1 Endurance 1000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 T10.3 1152 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2008 Silicon Storage Technology, Inc. S71152-12-000 8 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet AC CHARACTERISTICS TABLE 11: Read Cycle Timing Parameters VDD = 4.5-5.5V (TA = 0C to +70C (Commercial)) Symbol Parameter Min Max Units TRC Read Cycle Time TCE Chip Enable Access Time TAA Address Access Time 70 ns TOE Output Enable Access Time 35 ns TCLZ1 CE# Low to Active Output 0 ns TOLZ1 OE# Low to Active Output 0 ns TCHZ1 CE# High to High-Z Output 25 ns TOHZ1 OE# High to High-Z Output 25 ns TOH1 Output Hold from Address Change 70 ns 70 ns 0 ns T11.3 1152 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12: Program/Erase Cycle Timing Parameters for SST27SF512 Symbol TAS TAH TPRT TVPS TVPH TPW TEW TDS TDH TVR TART TA9S TA9H Parameter Address Setup Time Address Hold Time OE#/VPP Pulse Rise Time OE#/VPP Setup Time OE#/VPP Hold Time CE# Program Pulse Width CE# Erase Pulse Width Data Setup Time Data Hold Time OE#/VPP and A9 Recovery Time A9 Rise Time to 12V during Erase A9 Setup Time during Erase A9 Hold Time during Erase Min 1 1 50 1 1 20 100 1 1 1 50 1 1 Max 30 500 Units s s ns s s s ms s s s ns s s T12.0 1152 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 9 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE 13: Program/Erase Cycle Timing Parameters for SST27SF010/020 Symbol TCES TCEH TAS TAH TPRT TVPS TVPH TPW TEW TDS TDH TVR TART TA9S TA9H Parameter CE# Setup Time CE# Hold Time Address Setup Time Address Hold Time VPP Pulse Rise Time VPP Setup Time VPP Hold Time PGM# Program Pulse Width PGM# Erase Pulse Width Data Setup Time Data Hold Time A9 Recovery Time for Erase A9 Rise Time to 12V during Erase A9 Setup Time during Erase A9 Hold Time during Erase Min 1 1 1 1 50 1 1 20 100 1 1 1 50 1 1 Max 30 500 Units s s s s ns s s s ms s s s ns s s T13.0 1152 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 10 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TAA TRC ADDRESS TCE CE# TOE OE# TOLZ TOH TOHZ TCHZ DQ7-0 HIGH-Z DATA VALID DATA VALID TCLZ 1152 F03.0 FIGURE 6: Read Cycle Timing Diagram for SST27SF512/010/020 ADDRESS (EXCEPT A9) CE# TEW DQ7-0 OE#/VPP VDD VSS TVPH TVPS VPPH TPRT VPPH TVR TVR TA9S A9 VIH VIL TART TA9H 1152 F04b.1 FIGURE 7: Chip-Erase Timing Diagram for SST27SF512 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 11 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet ADDRESS (EXCEPT A9) TCEH CE# OE# VIH DQ7-0 TVPS VPPH VPP VDD VSS TPRT VPPH A9 TVPH TVR TA9S VIH VIL TART TA9H TEW PGM# TCES 1152 F04c.1 FIGURE 8: Chip-Erase Timing Diagram for SST27SF010/020 ADDRESS VALID ADDRESS TAH TAS TPW CE# TDS DQ7-0 HIGH-Z TDH DATA VALID TVR TVPS VPPH OE#/VPP VDD VSS TVPH TPRT 1152 F05b.2 FIGURE 9: Byte-Program Timing Diagram for SST27SF512 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 12 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet ADDRESS ADDRESS VALID TAH TAS CE# TCEH OE# VIH TDH TDS DQ7-0 HIGH-Z DATA VALID TVPS VPPH VPP VDD VSS TPW TVPH TPRT PGM# 1152 F05c.1 TCES FIGURE 10: Byte-Program Timing Diagram for SST27SF010/020 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 13 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet VIHT VHT INPUT VHT REFERENCE POINTS OUTPUT VLT VLT VILT 1152 F06.0 AC test inputs are driven at VIHT (2.4 V) for a logic "1" and VILT (0.4 V) for a logic "0". Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% 90%) are <10 ns. Note: VHT - VHIGHTest VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 11: AC Input/Output Reference Waveforms VDD TO TESTER RL HIGH TO DUT CL RL LOW 1152 F07.1 FIGURE 12: A Test Load Example (c)2008 Silicon Storage Technology, Inc. S71152-12-000 14 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Start A9 = VH OE#/VPP = VPPH Erase 100ms pulse (CE# = VIL) OE#/VPP = VDD or VSS A9 = VIL or VIH Wait for OE#/VPP and A9 Recovery Time Read Device (CE# = OE# = VIL) No Compare All bytes to FFH Yes Device Passed Device Failed 1152 F08b.2 FIGURE 13: Chip-Erase Algorithm for SST27SF512 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 15 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Start A9 = VH, VPP = VPPH CE# = VIL, OE# = VIH Erase 100ms pulse (PGM# = VIL) PGM# = VIH A9 = VIL or VIH Wait A9 Recovery Time Read Device No Compare all bytes to FFH Yes Device Passed Device Failed 1152 F08c.1 FIGURE 14: Chip-Erase Algorithm for SST27SF010/020 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 16 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Start Erase* OE#/VPP = VPPH Address = First Location Program 20s pulse (CE# = VIL) Increment Address OE#/VPP = VDD or VSS Last Address? No Yes Wait for OE#/VPP RecoveryTime Read Device (CE# = OE# = VIL) Compare all bytes to original data No Yes Device Passed Device Failed 1152 F09b.2 * See Figure 13 FIGURE 15: Byte-Program Algorithm for SST27SF512 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 17 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet Start Erase* VPP = VPPH Address = First Location CE# = VIL, OE# = VIH Program 20s pulse (PGM# = VIL) Increment Address Last Address? No Yes Read Device Compare all bytes to original data No Yes Device Passed Device Failed 1152 F09c.1 * See Figure 14 FIGURE 16: Byte-Program Algorithm for SST27SF010/020 (c)2008 Silicon Storage Technology, Inc. S71152-12-000 18 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet PRODUCT ORDERING INFORMATION SST 27 XX SF 020 XX XXXX - 70 - XXX - 3C XX NH - XXX E X Environmental Attribute E1 = non-Pb Package Modifier H = 32 pins or leads Package Type N = PLCC P = PDIP W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0C to +70C Minimum Endurance 3 = 1,000 cycles Read Access Speed 70 = 70 ns Device Density - x8 Organization 020 = 2 Mbit 010 = 1 Mbit 512 = 512 Kbit Voltage Range S = 4.5-5.5V Product Series 27 = Many-Time Programmable Flash OTP/EPROM replacement with EPROM pinout 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". Valid combinations for SST27SF512 SST27SF512-70-3C-NHE SST27SF512-70-3C-WHE Valid combinations for SST27SF010 SST27SF010-70-3C-NHE SST27SF010-70-3C-WHE SST27SF010-70-3C-PHE Valid combinations for SST27SF020 SST27SF020-70-3C-NHE SST27SF020-70-3C-WHE SST27SF020-70-3C-PHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2008 Silicon Storage Technology, Inc. S71152-12-000 19 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet PACKAGING DIAGRAMS TOP VIEW Optional Pin #1 Identifier .048 .042 SIDE VIEW .495 .485 .453 .447 2 1 32 .112 .106 .020 R. MAX. .029 x 30 .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. 32-plcc-NH-3 FIGURE 17: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH (c)2008 Silicon Storage Technology, Inc. S71152-12-000 20 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0- 5 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 32-tsop-WH-7 FIGURE 18: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH (c)2008 Silicon Storage Technology, Inc. S71152-12-000 21 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet 32 CL Pin #1 Identifier 1 1.655 1.645 .075 .065 7 4 PLCS. Base Plane Seating Plane .625 .600 .550 .530 .200 .170 .050 .015 .080 .070 .065 .045 .022 .016 .100 BSC .150 .120 0 15 .012 .008 .600 BSC Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-pdip-PH-3 FIGURE 19: 32-pin Plastic Dual In-line Pins (PDIP) SST Package Code: PH (c)2008 Silicon Storage Technology, Inc. S71152-12-000 22 9/08 512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash SST27SF512 / SST27SF010 / SST27SF020 Data Sheet TABLE 14: Revision History Number Description Date 02 * 2002 Data Book Feb 2002 03 * Document Control Release (SST Internal): No technical changes Apr 2002 04 * Corrected IH Supervoltage Current for A9 from 100 A to 200 A in Tables 5, 6, and 7 Jul 2002 05 * Corrected the Test Conditions for IDD and IPPR in Table 5 on page 7 Sep 2003 06 * * Corrected the Max value for IPP from 1 mA to 3 mA (See Tables 6 and 7) Added MPNs for non-PB packages (See page 19) Nov 2003 07 * * 2004 Data Book Corrected caption for Figure 7 from "Read Cycle" to "Chip-Erase" Nov 2003 08 * Removed 256 Kbit parts - refer to EOL Product Data Sheet S71152(02) Apr 2004 09 * * Removed all 90 ns parts - refer to EOL Product Data Sheet S71152(03) Added RoHS compliance information on page 1 and in the "Product Ordering Information" on page 19 Added the solder reflow temperature to the "Absolute Maximum Stress Ratings" on page 7. Mar 2005 * 10 * Removed obsolete Latch-up parameter from Table 10 on page 8 May 2005 11 * Corrected VPP voltage from 11.4-12.6V to 11.4-12V Sep 2005 12 * * Removed leaded parts. See S71152(04) End-of-Life PG package and PG valid combination. See S71152(04) Sep 2008 Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2008 Silicon Storage Technology, Inc. S71152-12-000 23 9/08