AT25640B-SSHL-T - MICROCHIP TECHNOLOGY

AT25320B/AT25640B

SPI Serial EEPROM 32 Kbits (4,096 x 8)

and 64 Kbits (8,192 x 8)

Features

• Serial Peripheral Interface (SPI) Compatible

• Supports SPI Modes 0 (0,0) and 3 (1,1):

– Data sheet describes mode 0 operation

• Low-Voltage and Standard-Voltage Operation:

– 1.8V (VCC = 1.8V to 5.5V)

• Industrial Temperature Range -40°C to +85°C

• 20 MHz Clock Rate (5V)

• 32-Byte Page Mode

• Block Write Protection:

– Protect 1/4, 1/2 or entire array

• Write-Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data

Protection

• Self-Timed Write Cycle (5 ms Maximum)

• High Reliability:

– Endurance: 1,000,000 write cycles

– Data retention: 100 years

• Green (Pb/Halide-free/RoHS Compliant) Packaging Options

• Die Sales: Wafer Form and Bumped Wafers

Packages

• 8-Lead SOIC, 8-Lead TSSOP, 8-Pad UDFN, 8-Ball VFBGA and 8-Pad XDFN

Table of Contents

Features.......................................................................................................................... 1

Packages.........................................................................................................................1

1. Package Types (not to scale).................................................................................... 4

2. Pin Description.......................................................................................................... 5

2.1. Chip Select (CS)...........................................................................................................................5

2.2. Serial Data Output (SO)............................................................................................................... 5

2.3. Write-Protect (WP)....................................................................................................................... 5

2.4. Ground (GND).............................................................................................................................. 6

2.5. Serial Data Input (SI)....................................................................................................................6

2.6. Serial Data Clock (SCK)...............................................................................................................6

2.7. Suspends Serial Input (HOLD).....................................................................................................6

2.8. Device Power Supply (VCC)......................................................................................................... 6

3. Description.................................................................................................................7

3.1. Block Diagram.............................................................................................................................. 7

4. Electrical Characteristics........................................................................................... 8

4.1. Absolute Maximum Ratings..........................................................................................................8

4.2. DC and AC Operating Range.......................................................................................................8

4.3. DC Characteristics....................................................................................................................... 8

4.4. AC Characteristics........................................................................................................................9

4.5. Electrical Specifications..............................................................................................................11

5. Serial Interface Description..................................................................................... 13

6. Functional Description............................................................................................. 14

7. Timing Diagrams......................................................................................................17

8. Packaging Information.............................................................................................20

8.1. Package Marking Information.....................................................................................................20

9. Revision History.......................................................................................................31

The Microchip Web Site................................................................................................ 32

Customer Change Notification Service..........................................................................32

Customer Support......................................................................................................... 32

Product Identification System........................................................................................33

Microchip Devices Code Protection Feature................................................................. 34

AT25320B/AT25640B

Legal Notice...................................................................................................................34

Trademarks................................................................................................................... 34

Quality Management System Certified by DNV.............................................................35

Worldwide Sales and Service........................................................................................36

AT25320B/AT25640B

1. Package Types (not to scale)

8-Lead SOIC/TSSOP

(Top View)

CS 1

GND

VCC

HOLD

SCK

GND

VCC

SCK

8-Ball VFBGA

(Top View)

GND

VCC

SCK

8-Pad UDFN/XDFN

(Top View)

HOLD

AT25320B/AT25640B

Package Types (not to scale)

2. Pin Description

The descriptions of the pins are listed in Table 2-1.

Table 2-1. Pin Function Table

Name 8-Lead

SOIC

8-Lead

TSSOP

8-Pad

UDFN(1)

8-Pad

XDFN

8-Ball

VFBGA

Function

CS 1 1 1 1 1 Chip Select

SO 2 2 2 2 2 Serial Data Output

WP(2)3 3 3 3 3 Write-Protect

GND 4 4 4 4 4 Ground

SI 5 5 5 5 5 Serial Data Input

SCK 6 6 6 6 6 Serial Data Clock

HOLD(2)7 7 7 7 7 Suspends Serial Input

VCC 8 8 8 8 8 Device Power Supply

Note:

1. The exposed pad on this package can be connected to GND or left floating.

2. The Write-Protect (WP) and Hold (HOLD) pins should be driven high or low as appropriate.

2.1 Chip Select (CS)

The AT25320B/AT25640B is selected when the CS pin is low. When the device is not selected, data will

not be accepted via the SI pin, and the Serial Output (SO) pin will remain in a high-impedance state.

To ensure robust operation, the Chip Select (CS) pin should follow VCC upon power-up. It is therefore

recommended to connect CS to VCC using a pull-up resistor (less than or equal to 10 kΩ). After power-up,

a low level on CS is required prior to any sequence being initiated.

2.2 Serial Data Output (SO)

The Serial Data Output (SO) pin is used to transfer data out of the AT25320B/AT25640B. During a read

sequence, data is shifted out on this pin after the falling edge of the serial clock.

2.3 Write-Protect (WP)

The Write-Protect (WP) pin will allow normal read/write operations when held high. When the WP pin is

brought low and WPEN bit is set to a logic '1', all write operations to the STATUS register are inhibited.

WP going low while CS is still low will interrupt a write operation to the STATUS register. If the internal

write cycle has already been initiated, WP going low will have no effect on any write operation to the

STATUS register. The WP pin function is blocked when the WPEN bit in the STATUS register is set to a

logic '0'. This will allow the user to install the AT25320B/AT25640B in a system with the WP pin tied to

ground and still be able to write to the STATUS register. All WP pin functions are enabled when the

WPEN bit is set to a logic '1'.

AT25320B/AT25640B

Pin Description

2.4 Ground (GND)

The ground reference for the power supply. The Ground (GND) pin should be connected to the system

ground.

2.5 Serial Data Input (SI)

The Serial Data Input (SI) pin is used to transfer data into the device. It receives instructions, addresses

and data. Data is latched on the rising edge of the serial clock.

2.6 Serial Data Clock (SCK)

The Serial Data Clock (SCK) pin is used to synchronize the communication between a master and the

AT25320B/AT25640B. Instructions, addresses or data present on the SI pin are latched on the rising

edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input.

2.7 Suspends Serial Input (HOLD)

The HOLD pin is used in conjunction with the CS pin to pause the AT25320B/AT25640B. When the

device is selected and a serial sequence is underway, HOLD can be used to pause the serial

communication with the master device without resetting the serial sequence. To pause, the HOLD pin

must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought

high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored

while the SO pin is in the high-impedance state.

2.8 Device Power Supply (VCC)

The Device Power Supply (VCC) pin is used to supply the source voltage to the device. Operations at

invalid VCC voltages may produce spurious results and should not be attempted.

AT25320B/AT25640B

Pin Description

3. Description

The AT25320B/AT25640B provides 32,768/65,536 bits of Serial Electrically Erasable Programmable

Read-Only Memory (EEPROM) organized as 4,096/8,192 words of 8 bits each. The device is optimized

for use in many industrial and commercial applications where low-power and low-voltage operation are

essential.

The AT25320B/AT25640B is enabled through the Chip Select (CS) pin and accessed via a 3-wire

interface consisting of Serial Data Input (SI), Serial Data Output (SO) and Serial Clock (SCK). All

programming cycles are completely self-timed, and no separate erase cycle is required before write.

Block write protection is enabled by programming the STATUS register with one of four blocks of write

protection. Separate Program Enable and Program Disable instructions are provided for additional data

protection. Hardware data protection is provided via the WP pin to protect against inadvertent write

attempts to the STATUS register. The HOLD pin may be used to suspend any serial communication

without resetting the serial sequence.

3.1 Block Diagram

GND

Memory

System Control

Module

High-Voltage

Generation

Circuit

Address Register

and Counter

Write Protection

Control

VCC

SCK

Power-on

Reset

Generator

Row Decoder

Data Register

Pause

Operation

Control

STATUS Register

Data Output

Buffer

HOLD

1 page

EEPROM Array

Column Decoder

AT25320B/AT25640B

Description

4. Electrical Characteristics

4.1 Absolute Maximum Ratings

Operating temperature -55°C to +125°C

Storage temperature -65°C to +150°C

Voltage on any pin with respect to ground -1.0V to +7.0V

VCC 6.25V

DC output current 5.0 mA

ESD protection 2 kV

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification are not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

4.2 DC and AC Operating Range

Table 4-1. DC and AC Operating Range

AT25320B/AT25640B

Operating Temperature (Case) Industrial Temperature Range -40°C to +85°C

VCC Power Supply Low Voltage Grade 1.8V to 5.5V

4.3 DC Characteristics

Table 4-2. DC Characteristics (1)

Parameter Symbol Minimum Typical Maximum Units Conditions

Supply Voltage VCC1 1.8 — 5.5 V

Supply Voltage VCC2 2.5 — 5.5 V

Supply Voltage VCC3 4.5 — 5.5 V

Supply Current ICC1 — 7.5 10.0 mA VCC = 5.0V at 20 MHz,

SO = Open, Read

Supply Current ICC2 — 4.0 10.0 mA VCC = 5.0V at 20 MHz,

SO = Open, Read, Write

Supply Current ICC3 — 4.0 6.0 mA VCC = 5.0V at 5 MHz,

SO = Open, Read, Write

Standby Current ISB1 — <0.1 6.0(2)µA VCC = 1.8V, CS = VCC

AT25320B/AT25640B

Electrical Characteristics

Parameter Symbol Minimum Typical Maximum Units Conditions

Standby Current ISB2 — 0.3 7.0(2)µA VCC = 2.5V, CS = VCC

Standby Current ISB3 — 2.0 10.0(2)µA VCC = 5.0V, CS = VCC

Input Leakage IIL -3.0 — 3.0 µA VIN = 0V to VCC

Output Leakage IOL -3.0 — 3.0 µA VIN = 0V to VCC,

TAC = 0°C to +70°C

Input

Low-Voltage

VIL(3)-0.6 — VCC x 0.3 V

Input

High-Voltage

VIH(3)VCC x 0.7 — VCC + 0.5 V

Output

Low-Voltage

VOL1 — — 0.4 V 3.6V ≤ VCC ≤ 5.5V IOL = 3.0 mA

Output

High-Voltage

VOH1 VCC - 0.8 — — V 3.6V ≤ VCC ≤ 5.5V IOH = -1.6 mA

Output

Low-Voltage

VOL2 — — 0.2 V 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA

Output

High-Voltage

VOH2 VCC - 0.2 — — V 1.8V ≤ VCC ≤ 3.6V IOH = -100 µA

Note:

1. Applicable over recommended operating range from: TA = -40°C to +85°C, VCC = 1.8V to 5.5V

(unless otherwise noted).

2. Worst case measured at 85°C.

3. VIL min and VIH max are reference only and are not tested.

4.4 AC Characteristics

Table 4-3. AC Characteristics(1)

Parameter Symbol Minimum Maximum Units Conditions

SCK Clock Frequency fSCK 0 20 MHz VCC = 4.5V to 5.5V

0 10 MHz VCC = 2.5V to 5.5V

0 5 MHz VCC = 1.8V to 5.5V

Input Rise Time tRI — 2 µs VCC = 4.5V to 5.5V

— 2 µs VCC = 2.5V to 5.5V

— 2 µs VCC = 1.8V to 5.5V

Input Fall Time tFI — 2 µs VCC = 4.5V to 5.5V

— 2 µs VCC = 2.5V to 5.5V

AT25320B/AT25640B

Electrical Characteristics

Parameter Symbol Minimum Maximum Units Conditions

— 2 µs VCC = 1.8V to 5.5V

SCK High Time tWH 20 — ns VCC = 4.5V to 5.5V

40 — ns VCC = 2.5V to 5.5V

80 — ns VCC = 1.8V to 5.5V

SCK Low Time tWL 20 — ns VCC = 4.5V to 5.5V

40 — ns VCC = 2.5V to 5.5V

80 — ns VCC = 1.8V to 5.5V

CS High Time tCS 25 — ns VCC = 4.5V to 5.5V

50 — ns VCC = 2.5V to 5.5V

100 — ns VCC = 1.8V to 5.5V

CS Setup Time tCSS 25 — ns VCC = 4.5V to 5.5V

50 — ns VCC = 2.5V to 5.5V

100 — ns VCC = 1.8V to 5.5V

CS Hold Time tCSH 25 — ns VCC = 4.5V to 5.5V

50 — ns VCC = 2.5V to 5.5V

100 — ns VCC = 1.8V to 5.5V

Data In Setup Time tSU 5 — ns VCC = 4.5V to 5.5V

10 — ns VCC = 2.5V to 5.5V

20 — ns VCC = 1.8V to 5.5V

Data In Hold Time tH5 — ns VCC = 4.5V to 5.5V

10 — ns VCC = 2.5V to 5.5V

20 — ns VCC = 1.8V to 5.5V

HOLD Setup Time tHD 5 — ns VCC = 4.5V to 5.5V

10 — ns VCC = 2.5V to 5.5V

20 — ns VCC = 1.8V to 5.5V

HOLD Hold Time tCD 5 — ns VCC = 4.5V to 5.5V

10 — ns VCC = 2.5V to 5.5V

20 — ns VCC = 1.8V to 5.5V

Output Valid tV0 20 ns VCC = 4.5V to 5.5V

0 40 ns VCC = 2.5V to 5.5V

0 80 ns VCC = 1.8V to 5.5V

Output Hold Time tHO 0 — ns VCC = 4.5V to 5.5V

AT25320B/AT25640B

Electrical Characteristics

Parameter Symbol Minimum Maximum Units Conditions

0 — ns VCC = 2.5V to 5.5V

0 — ns VCC = 1.8V to 5.5V

HOLD to Output Low Z tLZ 0 25 ns VCC = 4.5V to 5.5V

0 50 ns VCC = 2.5V to 5.5V

0 100 ns VCC = 1.8V to 5.5V

HOLD to Output High Z tHZ — 40 ns VCC = 4.5V to 5.5V

— 80 ns VCC = 2.5V to 5.5V

— 200 ns VCC = 1.8V to 5.5V

Output Disable Time tDIS — 40 ns VCC = 4.5V to 5.5V

— 80 ns VCC = 2.5V to 5.5V

— 200 ns VCC = 1.8V to 5.5V

Write Cycle Time tWC — 5 ms VCC = 4.5V to 5.5V

— 5 ms VCC = 2.5V to 5.5V

— 5 ms VCC = 1.8V to 5.5V

Note:

1. Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,

CL = 1 TTL Gate and 30 pF (unless otherwise noted).

4.5 Electrical Specifications

4.5.1 Power-Up Requirements and Reset Behavior

During a power-up sequence, the VCC supplied to the AT25320B/AT25640B should monotonically rise

from GND to the minimum VCC level as specified in Table 4-1 with a slew rate no faster than 0.1 V/μs.

4.5.1.1 Device Reset

To prevent inadvertent write operations or any other spurious events from occurring during a power-up

sequence, the AT25320B/AT25640B includes a Power-on Reset (POR) circuit. Upon power-up, the

device will not respond to any instructions until the VCC level crosses the internal voltage threshold (VPOR)

that brings the device out of Reset and into Standby mode.

The system designer must ensure the instructions are not sent to the device until the VCC supply has

reached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is

greater than or equal to the minimum VCC level, the bus master must wait at least tPUP before sending the

first instruction to the device. See Table 4-4 for the values associated with these power-up parameters.

AT25320B/AT25640B

Electrical Characteristics

Table 4-4. Power-Up Conditions(1)

Symbol Parameter Min. Max. Units

tPUP Time required after VCC is stable before the device can accept instructions. 100 — µs

VPOR Power-on Reset Threshold Voltage. — 1.5 V

tPOFF Minimum time at VCC = 0V between power cycles. 500 — ms

Note:

1. These parameters are characterized but they are not 100% tested in production.

If an event occurs in the system where the VCC level supplied to the AT25320B/AT25640B drops below

the maximum VPOR level specified, it is recommended that a full power cycle sequence be performed by

first driving the VCC pin to GND in less than 1 ms, waiting at least the minimum tPOFF time and then

performing a new power-up sequence in compliance with the requirements defined in this section.

4.5.2 Pin Capacitance

Table 4-5. Pin Capacitance(1,2)

Symbol Test Conditions Max. Units Conditions

COUT Output Capacitance (SO) 8 pF VOUT = 0V

CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V

Note:

1. This parameter is characterized and is not 100% tested.

2. Applicable over recommended operating range from: TA = 25°C, fSCK = 1.0 MHz, VCC = 5.0V

(unless otherwise noted).

4.5.3 EEPROM Cell Performance Characteristics

Table 4-6. EEPROM Cell Performance Characteristics

Operation Test Condition Min. Max. Units

Write Endurance(1)TA = 25°C,VCC= 3.3V, Page Mode 1,000,000 — Write

Cycles

Data Retention(1)TA = 55°C 100 — Years

Note:

1. Performance is determined through characterization and the qualification process.

AT25320B/AT25640B

Electrical Characteristics

5. Serial Interface Description

Master: The device that generates the serial clock.

Slave: Because the Serial Clock (SCK) pin is always an input, the AT25320B/AT25640B

always operates as a slave.

Transmitter/

receiver:

The AT25320B/AT25640B has separate pins designated for data transmission (SO)

and reception (SI).

MSb: The Most Significant bit (MSb) is the first bit transmitted and received.

Serial Opcode: After the device is selected with CS going low, the first byte will be received. This

byte contains the opcode that defines the operations to be performed.

Invalid Opcode: If an invalid opcode is received, no data will be shifted into the

AT25320B/AT25640B, and the Serial Output (SO) pin will remain in a

high‑impedance state until the falling edge of CS is detected again. This will

reinitialize the serial communication.

Figure 5-1. SPI Serial Interface

Master:

Microcontroller

Slave:

AT25320B/

AT25640B

Data Out (MOSI)

Data In (MISO)

Serial Clock (SPI CK)

SS0

SS1

SS2

SS3

SCK

AT25320B/AT25640B

Serial Interface Description

6. Functional Description

The AT25320B/AT25640B is designed to interface directly with the synchronous Serial Peripheral

Interface (SPI) of the 6805 and 68HC11 series of microcontrollers.

The AT25320B/AT25640B utilizes an 8-bit instruction register. The list of instructions and their operation

codes are contained in Table 6-1. All instructions, addresses and data are transferred with the MSb first

and start with a high-to-low CS transition.

Table 6-1. Instruction Set

Instruction Name Instruction Format Operation

WREN 0000 X110 Set Write Enable Latch

WRDI 0000 X100 Reset Write Enable Latch

RDSR 0000 X101 Read STATUS Register

WRSR 0000 X001 Write STATUS Register

READ 0000 X011 Read Data from Memory Array

WRITE 0000 X010 Write Data to Memory Array

Write Enable

(WREN):

The device will power-up in the Write Disable state when VCC is applied. All

programming instructions must therefore be preceded by a Write Enable instruction.

Write Disable

(WRDI):

To protect the device against inadvertent writes, the Write Disable instruction disables

all programming modes. The WRDI instruction is independent of the status of the WP

pin.

Read STATUS

(RDSR):

The Read STATUS Register instruction provides access to the STATUS register. The

Ready/Busy and Write Enable status of the device can be determined by the RDSR

instruction. Similarly, the Block Write Protection bits indicate the extent of protection

employed. These bits are set by using the WRSR instruction.

Table 6-2. STATUS Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN X X X BP1 BP0 WEN RDY

Table 6-3. Read STATUS Register Bit Definition

Bit Definition

Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is READY.

Bit 0 = 1 indicates the write cycle is in progress.

Bit 1 (WEN) Bit 1= 0 indicates the device is not write enabled.

Bit 1 = 1 indicates the device is write enabled.

Bit 2 (BP0) See Table 6-4.

Bit 3 (BP1) See Table 6-4.

AT25320B/AT25640B

Functional Description

Bit Definition

Bits 4 – 6 are zeros when device is not in an internal write cycle.

Bit 7 (WPEN) See Table 6-5.

Bits 0 – 7 are ones during an internal write cycle.

Write

STATUS

(WRSR):

The WRSR instruction allows the user to select one of four levels of protection. The

AT25320B/AT25640B is divided into four array segments. One-quarter, one-half or all of

the memory segments can be protected. Any of the data within any selected segment

will therefore be read-only. The Block Write Protection levels and corresponding STATUS

The three bits BP0, BP1 and WPEN are nonvolatile cells that have the same properties and functions as

the regular memory cells (e.g., WREN, tWC, RDSR).

Table 6-4. Block Write-Protect Bits

Level STATUS Register Bits Array Addresses Protected

BP1 BP0 AT25320B AT25640B

00 0 None None

1(1/4) 0 1 0C00-0FFF 1800-1FFF

2(1/2) 1 0 0800-0FFF 1000-1FFF

3(All) 1 1 0000-0FFF 0000-1FFF

The WRSR instruction also allows the user to enable or disable the Write-Protect (WP) pin through the use

of the Write-Protect Enable (WPEN) bit. Hardware Write Protection is enabled when the WP pin is low

and the WPEN bit is set to a logic '1'. Hardware Write Protection is disabled when either the WP pin is

high or the WPEN bit is set to a logic '0'. When the device is Hardware Write-Protected, writes to the

STATUS register, including the Block Protect bits and the WPEN bit, and the block-protected sections in

the memory array are disabled. Writes are only allowed to sections of the memory that are not block-

protected.

Note: When the WPEN bit is Hardware Write-Protected, it cannot be set back to a logic '0' as long as

the WP pin is held low.

Table 6-5. WPEN Operation

WPEN WP WEN Protected Blocks Unprotected Blocks STATUS Register

0x0 Protected Protected Protected

0x1 Protected Writeable Writeable

1Low 0Protected Protected Protected

1Low 1Protected Writeable Protected

xHigh 0Protected Protected Protected

xHigh 1Protected Writeable Writeable

AT25320B/AT25640B

Functional Description

Read

Sequence

(READ):

Reading the AT25320B/AT25640B via the Serial Output (SO) pin requires the following

sequence. After the CS line is pulled low to select a device, the READ instruction is

transmitted via the SI line followed by the byte address to be read (A15 – A0, see Table

6-6). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at the

specified address is then shifted out onto the SO line. If only one byte is to be read, the

CS line should be driven high after the data comes out. The read sequence can be

continued since the byte address is automatically incremented and data will continue to be

shifted out. When the highest address is reached, the address counter will roll over to the

lowest address allowing the entire memory to be read in one continuous read cycle.

Write

Sequence

(WRITE):

In order to program the AT25320B/AT25640B, two separate instructions must be

executed. First, the device must be write enabled via the WREN instruction. Then a

WRITE instruction may be executed. Also, the address of the memory location(s) to be

programmed must be outside the protected address field location selected by the Block

Write Protection level. During an internal write cycle, all instructions will be ignored except

the RDSR instruction.

A WRITE instruction requires the following sequence. After the CS line is pulled low to

select the device, the WRITE instruction is transmitted via the SI line followed by the byte

address (A15 – A0) and the data (D7 – D0) to be programmed (see Table 6-6).

Programming will start after the CS pin is brought high. The low-to-high transition of the

CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSb)

data bit.

The Ready/Busy status of the device can be determined by initiating a Read STATUS

write cycle has ended. Only the RDSR instruction is enabled during the write programming

cycle.

The AT25320B/AT25640B is capable of a 32-byte page write operation. After each byte of

data is received, the five low-order address bits are internally incremented by one; the

high-order bits of the address will remain constant. If more than 32 bytes of data are

transmitted, the address counter will rollover and the previously written data will be

overwritten. The AT25320B/AT25640B is automatically returned to the write disable state

at the completion of a write cycle.

Note: If the device is not write enabled, the device will ignore the WRITE instruction and

will return to the Standby state, when CS is brought high. A new CS falling edge is

required to reinitiate the serial communication.

Table 6-6. Address Key

Address AT25320B AT25640B

ANA11–A0A12–A0

Don’t Care Bits A15–A12 A15–A13

AT25320B/AT25640B

Functional Description

7. Timing Diagrams

Figure 7-1. Synchronous Data Timing (for Mode 0)

tDIS

tHO

tCSH

tCS

VOH

VOL

Valid In

tWH

VIH

VIL

tCSS

tWL

SCK

VIL

VIH

VIL

tSU

High Z High Z

Figure 7-2. WREN Timing

SCK

WREN Opcode

High Z

Figure 7-3. WRDI Timing

SCK

WRDI Opcode

High Z

AT25320B/AT25640B

Timing Diagrams

Figure 7-4. RDSR Timing

SCK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

7 6 5 4 3 2 1 0

Data Out

High-Impedance

MSB

Figure 7-5. WRSR Timing

SCK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction Data In

High-Impedance

7 6 5 4 3 2 1 0

(1)

Note: This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid sequence.

Figure 7-6. Read Timing

...

8 9 10

15 14 13

11 20 21 22 23 24 25 26 27 28 29 30

High-Impedance

Instruction

Byte Address

MSB

Data Out

SCK

AT25320B/AT25640B

Timing Diagrams

Figure 7-7. Write Timing

...

8 9 10

15 14 13

11 20 21 22 23 24 25 26 27 28 29 30 31

High-Impedance

SCK

Instruction Byte Address Data In

(1)

Note: This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid sequence.

Figure 7-8. HOLD Timing

tCD

HOLD

SCK

tHZ

tLZ

tHD

tCD

AT25320B/AT25640B

Timing Diagrams

8. Packaging Information

8.1 Package Marking Information

AT25320B and AT25640B: Package Marking Information

Catalog Number Truncation

AT25320B Truncation Code ###: 5BB

AT25640B Truncation Code ###: 5CB

Date Codes Voltages

YY = Year Y = Year WW = Work Week of Assembly % = Minimum Voltage

16: 2016 20: 2020 6: 2016 0: 2020 02: Week 2 L: 1.8V min

17: 2017 21: 2021 7: 2017 1: 2021 04: Week 4

18: 2018 22: 2022 8: 2018 2: 2022 ...

19: 2019 23: 2023 9: 2019 3: 2023 52: Week 52

Country of Origin Device Grade Atmel Truncation

CO = Country of Origin H or U: Industrial Grade AT: Atmel

ATM: Atmel

ATML: Atmel

Lot Number or Trace Code

NNN = Alphanumeric Trace Code (2 Characters for Small Packages)

8-lead SOIC

YYWWNNN

###% CO

ATMLHYWW

8-lead TSSOP

YYWWNNN

###%CO

ATHYWW ###

NNN

8-pad XDFN

8-pad UDFN

###

NNN

2.0 x 3.0 mm Body 2.35 x 3.73 mm Body

8-ball VFBGA

1.8 x 2.2 mm Body

Note 2: Package drawings are not to scale

Note 1: designates pin 1

###U

WWNNN

AT25320B/AT25640B

Packaging Information

0.25 C A–B D

SEATING

PLANE

TOP VIEW

SIDE VIEW

VIEW A–A

0.10 C

Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

NOTE 5

NX b

0.10 C A–B

H 0.23

(L1)

R0.13

VIEW C

SEE VIEW C

NOTE 1

AT25320B/AT25640B

Packaging Information

Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Foot Angle 0° - 8°

15°-5°

Mold Draft Angle Bottom

15°-5°

Mold Draft Angle Top

0.51-0.31

Lead Width

0.25-0.17

Lead Thickness

1.27-0.40LFoot Length

0.50-0.25hChamfer (Optional)

4.90 BSCDOverall Length

3.90 BSCE1Molded Package Width

6.00 BSCEOverall Width

0.25-0.10

Standoff

--1.25A2Molded Package Thickness

1.75--AOverall Height

1.27 BSC

Pitch

8NNumber of Pins

MAXNOMMINDimension Limits

MILLIMETERSUnits

protrusions shall not exceed 0.15mm per side.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic

4. Dimensioning and tolerancing per ASME Y14.5M

Notes:

Footprint L1 1.04 REF

5. Datums A & B to be determined at Datum H.

AT25320B/AT25640B

Packaging Information

RECOMMENDED LAND PATTERN

Microchip Technology Drawing C04-2057-SN Rev B

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Dimensioning and tolerancing per ASME Y14.5M1.

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Dimension Limits

Units

CContact Pad Spacing

Contact Pitch

MILLIMETERS

1.27 BSC

MIN

MAX

5.40

Contact Pad Length (X8)

Contact Pad Width (X8)

1.55

0.60

NOM

SILK SCREEN

AT25320B/AT25640B

Packaging Information

Packaging Diagrams and Parameters

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 2.90 3.00 3.10

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0.30

NOTE 1

1 2

L1 L

Microchip Technology Drawing C04-086B

AT25320B/AT25640B

Packaging Information

DS00049BC-page 96 2009 Microchip Technology Inc.

Packaging Diagrams and Parameters

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

AT25320B/AT25640B

Packaging Information

0.10 C

(DATUM B)

(DATUM A)

SEATING

PLANE

2X TOP VIEW

SIDE VIEW

NOTE 1

0.10 C A B

0.10 C

0.08 C

Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 1 of 2

For the most current package drawings, please see the Microchip Packaging Specification locate d a t

http://www.microchip.com/packaging

Note:

8-Lead Ultra Thin Plastic Dual Flat, No Lead Packag e (Q4B) - 2x3 mm Body [UDFN]

Atmel Legacy YNZ Package

E2 K

L8X b

0.10 C A B

0.05 C

(A3)

BOTTOM VIEW

AT25320B/AT25640B

Packaging Information

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.

Package is saw singulated

Dimensioning and tolerancing per ASME Y14.5M

For the most current package drawings, please see the Microchip Packaging Specification locate d a t

http://www.microchip.com/packaging

Note:

Number of Ter m inals

Overall He ig ht

Terminal Width

Overall Width

Terminal Length

Exposed Pad Width

Terminal Thickness

Pitch

Standoff

Units

Dimension Limit s

N0.50 BSC

0.152 REF

1.20

0.35

0.18

0.50

0.00

0.25

0.40

1.30

0.55

0.02

3.00 BSC

MILLIMETERS

MIN NOM

1.40

0.45

0.30

0.60

0.05

MAX

K-0.20 -Terminal-to-Exposed-Pad

Overall Length

Exposed Pad Length D

D2 1.40 2.00 BSC

1.50 1.60

Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 2 of 2

8-Lead Ultra Thin Plastic Dual Flat, No Lead Packag e (Q4B) - 2x3 mm Body [UDFN]

Atmel Legacy YNZ Package

AT25320B/AT25640B

Packaging Information

RECOMMENDED LAND PATTERN

Dimension Limit s

Units

Optional Center Pad Width

Optional Center Pad Length

Contact Pitch

X2 1.40

1.60

MILLIMETERS

0.50 BSC

MIN

EMAX

Cont act Pad Length (X8)

Contact Pad Width (X8 ) Y1

X1 0.85

0.30

NOM

CContact Pad Spacing 2.90

Cont act Pad to Center Pad (X8) G1 0.20

Thermal Via Diamete r V

Thermal Via Pitch EV 0.30

1.00

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Dimensi oning and tolerancing per ASME Y14.5M

For best soldering results, thermal vias, if used, should be filled or ten t ed to a v o i d solder loss dur in g

reflow process

For the most current package drawings, please see the Microchip Packaging Specification locate d a t

http://www.microchip.com/packaging

Note:

Microchip Technolo gy Drawing C04-21 35 5-Q4 B Re v A

8-Lead Ultra Thin Plastic Dual Flat, No Lead Packag e (Q4B) - 2x3 mm Body [UDFN]

Atmel Legacy YNZ Package

SILK SCREEN X1

ØV

Contact Pad to Contact Pad (X6) G2 0.33

AT25320B/AT25640B

Packaging Information

DRAWING NO. REV. TITLE GPC

8U2-1 G

6/11/13

8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,

Very Thin, Fine-Pitch Ball Grid Array Package

(VFBGA)

GWW

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.81 0.91 1.00

A1 0.15 0.20 0.25

A2 0.40 0.45 0.50

b 0.25 0.30 0.35

D 2.35 BSC

E 3.73 BSC

e 0.75 BSC

e1 0.74 REF

d 0.75 BSC

d1 0.80 REF

2. Dimension 'b' is measured at the maximum solder ball diameter.

1. This drawing is for general

3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.

Notes:

d0.08 C

f0.10 C

Øb

j n 0.15 mC A B

jn0.08 mC

(4X)

d0.10

A1 BALL

PAD

CORNER

SIDE VIEW

TOP VIEW

(e1)

2 1

A1 BALL PAD CORNER

(d1)

8 SOLDER BALLS

BOTTOM VIEW

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging.

AT25320B/AT25640B

Packaging Information

GPC DRAWING NO.

REV. TITLE

COMMON DIMENSIONS

(Unit of Measure = mm)

DTP

SYMBOL MIN NOM MAX NOTE

–

0.00

1.70

2.10

0.15

0.26

–

1.80

2.20

0.20

0.40 TYP

1.20 REF

0.30

0.40

0.05

1.90

2.30

0.25

0.35

End View

8ME1 B

9/10/2012

8ME1, 8-pad (1.80mm x 2.20mm body)

Extra Thin DFN (XDFN)

Top View

657

PIN #1 ID

0.10

0.15

PIN #1 ID

Side View

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging.

AT25320B/AT25640B

Packaging Information

9. Revision History

Atmel Document 8535 Revision A (April 2008)

Initial document release.

Atmel Document 8535 Revision B (July 2008)

Modified ‘Endurance’ parameter on page 6.

Atmel Document 8535 Revision C (May 2009)

Added Part Marking information; changed to Preliminary status.

Atmel Document 8535 Revision D (August 2009)

Changed Catalog Numbering. Added new Part Marking Information.

Atmel Document 8535 Revision E (April 2010)

Updated Ordering Code Detail, Ordering Information, template.

Atmel Document 8535 Revision F (June 2010)

Updated 8A2 and 8S1 package drawings. Remove Preliminary.

Atmel Document 8535 Revision G (November 2012)

Updated part markings to single page part marking. Updated package drawings. Replaced 8A2 package

with 8X package. Update template and Atmel logos.

Atmel Document 8535 Revision H (January 2015)

Added the UDFN Expanded Quantity Option. Updated the 8X, 8MA2, and 8ME1 package outline

drawings and the ordering information.

Revision A (June 2018)

Updated to the Microchip template. Microchip DS20005993A replaces Atmel document 8535. Updated

Part Marking Information. Added ESD rating. Removed lead finish designation. Added POR

recommendations section. Updated trace code format in package markings. Updated section content

throughout for clarification. Updated the SOIC, TSSOP, and UDFN package drawings to the Microchip

equivalents.

AT25320B/AT25640B

Revision History

The Microchip Web Site

Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as

a means to make files and information easily available to customers. Accessible by using your favorite

Internet browser, the web site contains the following information:

•Product Support – Data sheets and errata, application notes and sample programs, design

resources, user’s guides and hardware support documents, latest software releases and archived

software

•General Technical Support – Frequently Asked Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant program member listing

•Business of Microchip – Product selector and ordering guides, latest Microchip press releases,

listing of seminars and events, listings of Microchip sales offices, distributors and factory

representatives

Customer Change Notification Service

Microchip’s customer notification service helps keep customers current on Microchip products.

Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata

related to a specified product family or development tool of interest.

To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on

“Customer Change Notification” and follow the registration instructions.

Customer Support

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.

Local sales offices are also available to help customers. A listing of sales offices and locations is included

in the back of this document.

Technical support is available through the web site at: http://www.microchip.com/support

AT25320B/AT25640B

Product Identification System

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

Device Package Package

Drawing

Code

Package

Option

Shipping Carrier

Option

Device Grade

AT25320B-SSHL-B SOIC SN SS Bulk (Tubes) Industrial

Temperature

(-40°C to 85°C)

AT25320B-SSHL-T SOIC SN SS Tape and Reel

AT25640B-SSHL-T SOIC SN SS Tape and Reel

AT25320B-XHL-B TSSOP ST X Bulk (Tubes)

AT25640B-XHL-T TSSOP ST X Tape and Reel

AT25320B-MAHL-E UDFN Q4B MA Tape and Reel

AT25640B-MAHL-T UDFN Q4B MA Tape and Reel

AT25640B-MAHL-E UDFN Q4B MA Tape and Reel

AT25640B-CUL-T VFBGA 8U2-1 C Tape and Reel

AT25320B-MEHL-T XDFN 8ME1 ME Tape and Reel

AT25320B/AT25640B

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the

market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of

these methods, to our knowledge, require using the Microchip products in a manner outside the

operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is

engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their

code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the

code protection features of our products. Attempts to break Microchip’s code protection feature may be a

violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software

or other copyrighted work, you may have a right to sue for relief under that Act.

Legal Notice

Information contained in this publication regarding device applications and the like is provided only for

your convenience and may be superseded by updates. It is your responsibility to ensure that your

application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY

OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS

CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life

support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,

indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting

from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual

property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings,

BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,

Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA,

SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight

Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,

chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController,

dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi,

AT25320B/AT25640B

motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient

Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL

ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

ISBN: 978-1-5224-3161-9

Quality Management System Certified by DNV

ISO/TS 16949

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer

fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC®

DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design and manufacture of development

systems is ISO 9001:2000 certified.

AT25320B/AT25640B

AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Austin, TX

Tel: 512-257-3370

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Tel: 774-760-0087

Fax: 774-760-0088

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Tel: 630-285-0071

Fax: 630-285-0075

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Tel: 972-818-7423

Fax: 972-818-2924

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Tel: 248-848-4000

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Tel: 281-894-5983

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Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

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Tel: 949-462-9523

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Tel: 951-273-7800

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Tel: 919-844-7510

New York, NY

Tel: 631-435-6000

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Tel: 408-735-9110

Tel: 408-436-4270

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

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Tel: 61-2-9868-6733

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Tel: 86-10-8569-7000

China - Chengdu

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China - Chongqing

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China - Dongguan

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Tel: 86-20-8755-8029

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Tel: 86-29-8833-7252

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Tel: 86-756-3210040

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Tel: 49-89-627-144-0

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Italy - Milan

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Tel: 44-118-921-5800

Fax: 44-118-921-5820

Worldwide Sales and Service