TOSHIBA TC74VHC161, 163F/FN/FS/FT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74VHC161F, TC74VHC161FN, TC74VHC161FS, TC74VHC161FT TC74VHC163F, TC74VHC163FN, TC74VHC163FS, TC74VHC163FT SYNCHRONOUS PRESETTABLE 4 - BIT COUNTER TC74VHC161F /FN/FS/FT BINARY, ASYNCHRONOUS CLEAR TC74VHC163F /FN/FS/FT_ BINARY, SYNCHRONOUS CLEAR The TC74VHC 161 and 163 are advanced high speed CMOS SYNCHRONOUS PRESETTABLE 4 BIT BINARY COUNTERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low 16 Re =a 1 power dissipation. 1 The CK input is active on the rising edge. Both LOAD and F (SOP16-P-300-1.27) = FN (SOL16-P-150-1.27) CLR inputs are active on low logic level. Weight: 0.18g(TYP.) Weight : 0.13g (TYP.) Presetting of each ICs is synchronous to the rising edge of CK The clear function of the TC74VHC163 is synchronous to CK, while the TC74VHC161 are cleared asynchronously. 16 16 Two enable inputs (ENP and ENT) and CARRY OUTPUT are provided to enable easy cascading of counters, which 1 eas . 2 : . 1 facilitates easy implementation of n - bit counters without FS (SSOP16-P-225-0.658) FT (TSSOP16-P-0044-0.65) using external gates. Weight : 0.07; P. Weight : 0.06g (TYP An input protection circuit ensures that 0 to 7V can be sight : 0.679 (TYP) sight 0.065 CYP) applied to the input pins without regard to the supply PIN ASSIGNMENT voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. CLR 16 i ScRy cK 2 13 OUTPUT FEATURES ; A3 14 QA High Speed --------sssseesereeseeeeseeees fax = 185MHz (typ.) at Voc =5V Ba 13 QB Low Power Dissipation :+---+-++-+-- loc = 4uA(Max.) at Ta = 25C cs 12 QC * High Noise Immunity-::-+-----++ Van = Vai = 28% Voc (Min.) D6 11. QD Power Down Protection is provided on all inputs. Balanced Propagation Delays--- toty=toHL ENP 7 10 ENT Wide Operating Voltage Range:- Vcc (opr) = 2V~5.5V GND 8 9 LOAD @ LOW Noise --erecsstrersesesresssseserenseeee Vowp = 0.8V (Max.) e Pin and Function Compatible with 74ALS161/163 (TOP VIEW) IEC LOGIC SYMBOL TC7AVHC161 TC74VHC163 cr =0 aR sct=0 M2 O5) carry reno M2 (15) G3 =1 OUTPUT ents oe 3CT = 159 SutpUT G4 ENP 2 G4 C5/2,3,4+ cx 21 C5/2,3,4 + 1 c Qn @) (14) . QB A@ pee, Tay Oe c ac ct a (2) Oc D Qo p LT od 961001 EBA2 @ TOSHIBA is continually working to imprave the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, te observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as. set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. m3 1997-01-30 1/10TOSHIBA TRUTH TABLE TC74VHC161,163F/FN/FS/FT TC74VHC161 TC74VHC163 [__ INPUTS INPUTS OUTPUTS FUNCTION CLR | LD {ENP|ENT| CK [CLR] LD | ENP|ENT| CK [QA] QB | Qc [OD L x x x x L XxX X xX L L L L RESET TO 0 H/{[LteC]x |x fff>Hi{jtelxi] x] fpalsp]ci]o PRESET DATA H H x L H H xX L | 4 NO CHANGE NO COUNT H H L x a H L x | NO CHANGE NO COUNT HIT HEH] HIF tat aH] ada COUNT UP COUNT H x x x Lb x x xX Xx L NO CHANGE NO COUNT Note X : Dont Care A, B, C, D: Logic Level of Data Inputs Carry : CARRY = ENT-QA- QB-QC-QD TIMING CHART CLR | " A WA DON'T CARE UNTILLOAD GOESLOW ss YY 3 UW WWW WWWWTWTWMVV@CT@WVCC0WX@V@YVH@W0 INPUTS Ya WM @/@@E@@q@e@Eq@H#LI 0 YYZ MMe eee EEE ENP i ae ee ENT nn ! | a e/g 3a Hy OUTPUTS i i a YAA | i C/o : cw ji ff | 11201130 14150 1 21 a a & COUNT t INHIBIT > ASYNC SYNC PRESET CLEAR CLEAR (161) (163) 3 The Pepa, described inthis docu oresenved iy a i ouule gareng pplication: of rece cesar No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 214 1997-01-30 2/10TOSHIBA TC74VHC161,163F/FN/FS/FT SYSTEM DIAGRAM cLR ENP ENT LOAD CK * TRUTH TABLE OF INTERNAL F/F TC74VHC161 TC74VHC163 DICK; R{Q;Q{DICK] RIQ{Q X/X]HP LT HPX {FPP LH LI Fy Ly uJ H| ey PF] eypuyk . Hi FleyaHletat ry edule X: Don't Care X [LL] Lb Jrocuance| X [L_ | X [no cuance 215 1997-01-30 3/10TOSHIBA TC74VHC161, 163F/FN/FS/FT ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL VALUE UNIT Supply Voltage Range Vec 0.5~7.0 Vv DC Input Voltage Vin -0.5~7.0 Vv DC Output Voltage Vout 0.5~Vec + 0.5 Vv Input Diode Current lik 20 mA Output Diode Current lox +20 mA DC Output Current lout #25 mA DC Ve/Ground Current lec +50 mA Power Dissipation Py 180 mw Storage Temperature Tstg ~65~150 C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL VALUE UNIT Supply Voltage Vee 2.0~5.5 Vv Input Voltage Vin O~5.5 Vv Output Voltage Vout 0~Vec Vv Operating Temperature Topr 40~85 C O~ 100 (Vcc = 3.3 + 0.3V) Input Rise and Fall Time dt/dv 0~20 (Vec= 5+40.5V) ns/V DC ELECTRICAL CHARACTERISTICS Ta =25C Ta = 40~85C PARAMETER SYMBOL TEST CONDITION Voc UNIT (V) | MIN. | TYP. | MAX.) MIN. | MAX. High - Level V 20[150/ - [ - [rso] | Input Voltage 'H 30> Vecx0.7| WWeex 0.7} = Low - Level Vy 2 ee ee a ee Input Voltage de 3.0 _ WMex0.3] - Meex0.3 2.0 1.9 2.0 _ 1.9 _ : = low = 7 50nA 3.0 2.9 3.0 _ 2.9 High - Level Vin OH Me 7 Vv Output Voltage Vou Vicorv 45] 44 | 45 44 HOT Vit lop= ~4mA =| 3.01 2.58 | - |248] - lon = 8mMA 4.5 | 3.94 - - 3.80 _ 2.0 _- 0.0 0.1 - 0.1 Low Level va [v= fewsoma 32] = | 88 fat | = [at] y Output Voltage OL Vv V : : : Ori, lo. = 4mA 30] | 036] | 0.44 lop = 8MA 4.5 - ~ 0.36 _ 0.44 Input Leakage Current tin Vin=5.5V or GND O~5.5) ~_ +0.1 _ +1.0 A Quiescent Supply Current | ec | Vin = Vcc or GND 55] | | 40 | | 400 | * 216 1997-01-30 4/10TOSHIBA TC74VHC161,163F/FN/FS/FT TIMING REQUIREMENTS (Input t,=t=3ns) Ta =25 Ta = 40~85 PARAMETER SYMBOL | TEST CONDITION . c 8 s UNIT Vec(V) LIMIT LIMIT Minimum Pulse Width tw) Fig. 1 3.3+0.3 5.0 5.0 (CK) tw(H) , 5.0+0.5 5.0 5.0 Minimum Pulse Width t Fig. 4 3.340.3 5.0 5.0 (CiR)* wi) " 5.0+0.5 5.0 5.0 Minimum Set-up Time t Fig. 2 3.340.3 5.5 6.5 (A,B,C, D) s . 5.0+0.5 4.5 45 Minimum Set-up Time . 3.3+0.3 8.0 9.5 joan Fig. 2 (TOADS ts 9 5.0+0.5 5.0 6.0 Minimum Set-up Time Fig. 3 3.340.3 7.5 9.0 (ENT, ENP) ts 'g- 5.0+0.5 5.0 6.0 ns Minimum Set-up Time t Fig. 5 3.340.3 4.0 4.0 (CIR )** s . 5.0+0.5 3.5 3.5 . 3.3+0.3 1.0 1.0 Minimum Hold Time th Fig. 2,3 50+05 10 1.0 Minimum Hold Time t Fig. 5 3.3+40.3 1.0 1.0 (CIR )** hoy . 5.0+0.5 1.5 1.5 Minimum Removal Time t Fig. 4 3.340.3 2.5 2.5 (CER)* rem . 5.00.5 15 15 * for TC74VHC161 only ** for TC74VHC163 only 217 1997-01-30 5/10TOSHIBA TC74VHC161, 163F/FN/FS/FT AC ELECTRICAL CHARACTERISTICS ( Input t, = t= 3ns) . TEST CONDITION = 25 = 40~85 PARAMETER SYMBOL ST CONDITIO passe Pa 80 85C UNIT Vec(V) | CL (pF) | MIN. | TYP. | MAX. | MIN. | MAX. . 33t03, > | | 83] 128] 10 | 15.0 Propagation Delay Time oa Fig. 1,2 50 = 10.8 | 16.3 | 1.0 | 18.5 (CK-Q) 50+05+- 2 _ 43 8.1} 1.0 9.5 50 7 6.4 | 10.1 1.0 411.5 t 3.3403 15 _ 8.7 | 13.6 1.0 16.0 Propagation Delay Time tur Fig. 1 50 ~ 11.2 | 17.1 | 1.0 | 19.5 (CK-CARRY, Count Mode) | 50t05- | 49 | 81} 10 | 95 50 = 6.4 | 10.1 1.0 11.5 ' 3.3+03 15 ~ 11.0 | 17.2 1.0 20.0 Propagation Delay Time tun Fig. 2 30 = 13.5 | 20.7 | 1.0 | 23.5 (CK-CARRY, Preset Mode) | 5.0+05 2 = 6.2 | 10.3 | 1.0 | 12.0 50 = 7.7 | 12.3 1.0 14.0 | ns 3.3403 15 _ 7.5 | 12.3 1.0 14.5 Propagation Delay Time etn Fig. 6 30 _ 10.5 | 15.8 | 1.0 | 18.0 (ENT - CARRY) P 5.0+05 15 ~ 49 8.1 1.0 9.5 50 _ 6.4 | 10.1 1.0 11.5 33+03/ 5 | | 891 136 [ 10 | 160 Propagation Delay Time toa | Fig. 50 [ita] i171] 10 | 195 (CLR-Q)* 5.0+05 15 - 5.5 9.0 1.0 10.5 50 _ 7.0 11.0 1.0 12.5 33to3- 0 | | 84 [132 [10 | 155 Propagation Delay Time toHL Fig. 4 50 = 10.9 | 16.7 | 1.0 | 19.0 (CLR - CARRY )* 5.0+05 15 _ 5.0 8.6 1.0 10.0 50 = 6.5 | 10.6 1.0 12.0 3320355 ss- as [= 50 | = Maximum Clock Frequency fax 15 7351 185 = 115 MHz 5.040.5 50 95 125 _ 85 = Input Capacitance Cin _ 4 10 _ 10 pF Power Dissipation Capacitance Cpep (Note 1) _ 23 ~ _ _ Note (1) Cpp is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation : lec topr) = C po * Vee fin + bec When the outputs drive a capacitive load, total current consumption is the sum of Cpp, and Alec which is obtained from the following formula: Coa Cog Cac Cap Cco Alec =fex + Vee ( 2 + Q + g + Q + ) 2 4 8 16 16 Caa~Cap and Cco are the capacitances at QA~QD and CARRY OUT, respectively. fck is the input frequency of the CK. (2) *for TC74VHC161 only 218 1997-01-30 6/10TOSHIBA SWITCHING CHARACTERISTICS TEST WAVEFORM TC74VHC161, 163F/FN/FS/FT COUNT MODE (Fig. 1) te tt Vee cK 50% (sos \ / a GND Vou Q, CARRY 50% 50% Vor tou toa PRESET MODE (Fig. 2) Vec LOAD GND Vee cK GND Vou Q CARRY (Fig. 3) _. Vee ENP 50% 50% / 50% ENT tt hth | Vec Vou CARRY 50% 50% GND Vou tan tout 1 CLEAR MODE (TC74VHC161) (Fig. 4) So Vee 50% LH} GND tw Vee GND trem e_ Von CARRY 50% test oo Ve CLEAR MODE (TC74VHC163) (Fig. 5) 50% am ciR GND Vee CK GND Vou Q, CARRY Vor CASCADE MODE (Fix Maximum Count) J UN com Vee ENT ] 50% GND (Fig. 6) GND Vo. 1997-01-30 7/10TOSHIBA TC74VHC161, 163F/FN/FS/FT NOISE CHARACTERISTICS (Input t,=t;=3ns) TEST NDITION = 25 PARAMETER SYMBOL co Tas 25 UNIT Vee (V) TYP. MAX. Quiet Output _ Maximum Dynamic Vo, Vor C. = 50pF 5.0 0.4 0.8 Vv Quiet Output _ _ _ Minimum Dynamic Vo, Vow C. = 50pF 5.0 0.4 0.8 v Minimum High Level _ _ Dynamic Input Voltage Vio C. = SOpF 5.0 3.5 v Maximum Low Level Dynamic Input Voltage Vio C. = SOpF 5.0 ~ 1.5 Vv INPUT EQUIVALENT CIRCUIT INPUT TYPICAL APPLICATION PARALLEL CARRY N-BIT COUNTER H: COUNT aa L: DISABLE INPUTS INPUTS INPUTS f i IDA BC OD IDA BC OD IDA BC OD Lene L_lenp ENP H: COUNT cA RRY |- --- > NEX L = DISABLE ENT RRY ENT CARRY ENT CARRY T STAGE {ck cK lck CLR QA QB QC ? CLR * * 7 Qp CLR * * r - Ux ,_~_" U_" eos OUTPUTS OUTPUTS OUTPUTS CLR: , , CK _ 220 7997-01-30 8/10